| Commit message (Collapse) | Author | Age | Files | Lines |
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And start wiring to x86_power so it can detect AC state changes
(needed to enable/disable turbo).
*YES*, this compiles for BDS/Daisy now...
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9069
TEST=plug/unplug AC power and look for "x86 AC on" / "x86 AC off" in debug log
Change-Id: I8399fab9637d6635a1c615f07448fd45b86bc25f
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This would throttle proto1 systems, if it weren't for a HW bug which
means we don't have prochot control over proto1 systems at all.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8982
TEST=system still boots
Change-Id: Ie42c034141f24795ec2bfee592e194001d3cd174
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Open drain cleanup minimizes leakage and signal glitching on shared
reset/signal lines, and is tidier than explicitly switching the
signals between inputs/outputs.
Touchscreen and lightbar are powered by +5VALW so their signals need
to be dropped when +5VALW is off to avoid leakage, and so they see a
clean reset signal when they're powered up.
Moved +5VALW power-on to S5-S3 transition, to minimize power draw in
S5. This also ensures that 5VALW-powered devices get reset when the
device bounces through S5. (No effect on proto1, where 5VALW is not
under EC control.)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9172
TEST=boot and shutdown system; still works.
Change-Id: Ia4bf0703292a189c324ce283d1e79a33776ee40f
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This saves ~70mw of power.
To make this work, I also had to stretch the power button signal to
give the system a chance to come back up when the user taps the power
button.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9574
TEST=manual
For each of the following tests, wait ~15 sec after the system is
powered off to give it a chance to drop DPWROK.
1) tap power button -> system turns on
2) hold power button 1 sec -> system turns on
3) open lid -> system turns on
4) silego reset (power+refresh, or power+esc on proto1) -> system stays off
5) silego recovery (power+esc+refresh) -> system turns on
6) hold down power button and type 'reboot' on EC console -> system turns on
7) type 'powerbtn' on EC console -> system turns on
Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
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This is cleaner than having x86_power explicitly know about everything
else in the system that cares about power transitions.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=boot and shutdown system; still works. Mouse powered to system is off in S5.
Change-Id: Ib673ca2d9edd5473334e7604e98b99b02b768419
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8932
TEST=manual
1) gpioget with system off -> ENABLE_WLAN = 0, RADIO_ENABLE_* = 0
2) gpioget with system on -> ENABLE_WLAN = 1, RADIO_ENABLE_* = 1
Change-Id: I397a195b4539083c622b85d63703c334cae931fb
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Disable USB ports when system is down and set USB ports to standard
downstream mode when system is up or sleeping.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:9249
TEST=Plug in a phone and see it charge when system is on.
Turn off the system and see it stop charging.
Change-Id: I02850dee7051ed6589e0f176a933069203f0efdf
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1.
Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
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The EVT boards will have an enable signal for the +5V always-on rail
connected to GPIO PK4.
Just turn it on at startup to ensure that EVT boards will run out of the
box with the current EC firmware.
(PK4 is a test point on proto-1 board, this should be harmless).
We can later implement fancier power saving scheme by enabling it only
when we enter S3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9284
TEST=boot Linux kernel on Link proto-1 and Link-1 proto-1 reworked with
+5V Always-on enable on PK4.
Change-Id: I26527480c7cd364f3fabcaabaadd079a332f9c1c
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This completes console output cleanup. The remaining calls to
uart_puts() and uart_printf() actually need to be that way.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7464
TEST=manual
Change-Id: Ib1d6d370d30429017b3d11994894fece75fab6ea
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This adds a 'ch' command which prints/sets which channels are active
This handles all the async output; the remaining debug commands will
be refactored to use ccprintf() / ccputs() in a followup CL.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7464
TEST=manual
ch --> all channels active
ch 0x100 -> just port80 active
powerbtn -> system boots; only port 80 codes shown on console
Change-Id: I9efc43acec919b62b78c2c82c61946d32380adfe
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=power system on; should still boot
Change-Id: I2e6c1f1cb4ffabf37d3113faca900da17c1353e9
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7832
TEST=manual
1. Power on system
2. From ec console: kblight 100
3. Use a magnet next to the left shift key to trigger the lid switch. Screen and keyboard should go dark.
4. Remove the magnet and they should light up again.
Change-Id: I298ea94930976153d8dcd102316b010ee28cd747
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I need to clean up the console commands and provide the same functionality
via ectool, but this is a good starting point.
BUG=chrome-os-partner:7839
TEST=manual
Power up the CPU. The lights should blink.
Change-Id: Ic05a171d2b647551f1cfc7d6b2fd101088cac137
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7461
TEST=manual
make BOARD={bds,link,daisy}
make tests
flash link system and make sure it boots
Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
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In addition, it's not necessary for VGFX_CORE to be enabled for the
system to be in S0; just CPU_CORE is sufficient.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8725
TEST=boot system via power button; should boot normally
Change-Id: Iea32837b698845355f7fa6bd2eaca9fd95f6726b
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8724
TEST=if timestamps show up in the debug output, it works
Change-Id: I5264a3a40a07a824cc15b39a7bd81f2db02a3c13
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BUG=chrome-os-partner:8718
TEST=manual
1) Use 'reboot' command from console to boot image. Should end up in
image A, with last reset reason soft cold. 'sysinfo' should show we
jumped to this image.
2) sysjump RO. Should end up in RO; otherwise same as 1)
3) reboot using Power+Esc+Reload. Should end up in image RO, with last
reset reason reset pin. 'sysinfo' should show we did not jump to this
image.
4) sysjump A. Should end up in A with reset reason reset pin.
'sysinfo' should show we jumped here.
Change-Id: I2dd5595eab4ba2c91bfe8b2b2e9677d7732aca63
Signed-off-by: Randall Spangler <rspangler@chromium.org>
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This is necessary at init-time for verified boot to jump from RO to
one of the RW images.
It's also used by factory EC update to update one image and then jump
to the updated image to finish the update. In this case, the x86 does
NOT reboot.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8449
TEST=manual
1) power on x86 and log in
2) sysjump a --> system is in a; x86 has not rebooted
3) sysjump ro --> system is back in RO; x86 has not rebooted
4) reboot -> system is in RO; x86 HAS rebooted
Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
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This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
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Keyboard reset now triggers a cold reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then do 'x86reset cold' for a cold reset or
'x86reset warm' for a warm reset. Check x86 debug console to see that
coreboot detects the warm (soft) reset.
Change-Id: I00930d9f5df98365277cd5c7f2eb8f135c4e4398
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(new method, and x86reset command to call it)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8460
TEST=manual: powerbtn, wait for system to boot, x86reset
Change-Id: Iad3f5c268b334e8d0ec1adfa2878f9e9d5927b9f
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Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
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...since x86_power_in_S0() is a terrible function to have implemented
for gaia chipsets, and I need to add more detectable states for lid
switch handling anyway.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I0c90c6875b27d1bf23f093e88e34eabf2a8c86e4
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BUG=chrome-os-partner:8277
TEST=manual
On EC console:
hostevent set 0x1e
From root shell:
ectool eventget --> should return 0x1e
ectool eventclear 0x02
ectool eventget --> should return 0x1c
ectool queryec --> should return event 3
ectool queryec --> should return event 4
ectool queryec --> should return event 5
ectool queryec --> should return no event pending
ectool eventsetsmimask 0x1200
ectool eventsetscimask 0x0034
ectool eventgetsmimask --> should return 0x1200
ectool eventgetscimask --> should return 0x0034
On EC console:
hostevent --> should show raw=0 SMI mask = 0x1200 SCI mask = 0x34
Change-Id: I33042fa80c0b148cd63209a94a184af493e25ed3
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(implementation of APIs still todo)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8242
TEST=none
Change-Id: Idbd38c4e873e95382ae815e1d5b827d95396be8f
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I1be67004edb23ccd18ad434c9340bfbecc22e7c4
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8231
TEST=manual:
gpioget PCH_RCINn --> should return 0
powerbtn --> should turn system on
gpioget PCH_RCINn --> should return 1
Change-Id: I6801bc2e5801ecac53a50b99cf802c00295faf0b
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This change broke the tree.
This reverts commit 1d1a38a6ccc352c3f9e1c5636def9dd63bf5951b
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8231
TEST=manual:
gpioget PCH_RCINn --> should return 0
powerbtn --> should turn system on
gpioget PCH_RCINn --> should return 1
Change-Id: I8e58e2b6a48c811d5e57549bdcaea27bca964c08
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But only if the system is in S0.
Approved at internal gerrit: 11595.
BUG=none
TEST=tested on bds.
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Supports turning system on and off via power button.
Also added 'powerbtn' command, which sends a power button press of the
specified duration, and deprecated the 'x86power s0' command, since
pressing the power button is a more correct way of powering on/off the
system.
Note that current coreboot doesn't seem to boot reliably; when it
fails, the x86 asks for S5 and then S0 a second later. It boots about
every 3rd try. No indication this is due to the EC; the EC just was
ignoring these requests until this CL.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7851
TEST=reboot, 'powerbtn', system should power on
'powerbtn', system should power off
'powerbtn 5000', system should power off regardless of previous state
press power button, system should power on
press power button again, system should power off
hold power button 8 sec, system should power off regardless of previous state
Change-Id: I89f419553289b20c78a57bc8cb1699932b095aa1
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7850
TEST=reboot, press power button; system should turn on
reboot, type 'x86power s0'; system should also turn on
Change-Id: Iac114c2655240d8aba81283d12f667f8e64d3ad3
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7906
TEST=from ec console, 'x86power s0' should power the system on reliably.
Change-Id: Idebfc8b4e86587b540934d245649f912ccb4aa95
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To assist in x86 chipset bringup, there are 4 GPIOs we weren't
printing state transitions for.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=reboot; should see state transitions in the high nibble (mask 0xF000), for example:
[x86 power state 1 = S5, in 0x2001]
[x86 power state 1 = S5, in 0x3001]
[x86 power state 1 = S5, in 0x7001]
Change-Id: I0527e4698425d845e8b08589e89592f95d8bee41
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Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=x86power s0; should turn on all power rails (check via gpioget)
Change-Id: I284ac2104e02748ed69408873fbcebb9d54cdcff
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For bringup, this powers on the x86 unconditionally.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7528
TEST=none
Change-Id: Ib23e56d38ab42f8d8a4dbd1ba9dce12f0c3eeec9
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