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* USB-PD: Add hook for PD connect eventDaisuke Nojiri2019-05-082-0/+6
| | | | | | | | | | | | | | | | This patch adds a hook for USB PD connect event. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/127228934 BRANCH=none TEST=buildall. Verify a hook is called on BC12 charger connection. Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3 Reviewed-on: https://chromium-review.googlesource.com/1597794 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_pd_protocol.c: exiting from try.src to attach.srcRuibin Chang2019-05-071-10/+34
| | | | | | | | | | | | | | | | | | | | The port shall transition to Attached.SRC when the SRC.Rd state is detected on exactly "one of the CC1 or CC2 pins" for at least tTryCCDebounce. See TypeC v1.4 spec 4.5.2.2.10.2 Exiting from Try.SRC State. BRANCH=None BUG=b:130615676 TEST=1.Ampton with apple type-c adapter 2.Ellisys USB-PD test Change-Id: I461c53e2b8d9189f290956964754ae5b1a11a950 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1564499 Commit-Ready: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pd_protocol: Don't clear PD flags while debouncing.Aseda Aboagye2019-05-041-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PD_FLAGS_TRY_SRC flag was being cleared every time we entered the *_DISCONNECTED state. However, this would lead to a case where if the state machine was debouncing the CC lines and decided to re-enter the SRC_DISCONNECTED state, the Try.Src flag would be cleared and the state machine would not transition to the TryWait.SNK state after timing out. We shouldn't clear any flags when transitioning back to the disconnected state from the debounce state as the two states here are really the same states in the state diagram. This commit simply only clears the PD flags when we're transitioning to the disconnected state but not from a debounce state. This also keeps the Try.Src flag set if the previous state was a debounce as it means the state machine decided it didn't meet the condition to exit and should continue waiting before transitioning to TryWait.SNK. BUG=b:115452695 BRANCH=master TEST=Flash nocturne; boot to S0, plug in Apple 87W USB-C charger with eMarked cable, verify we form an explicit 45W contract. Change-Id: I6d8f5d69b8bd0d25ac7af008bbbe91f2658cdfe2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1286299 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 1f30c7483fa5621e9d67c5977709dce73f31a66d) Reviewed-on: https://chromium-review.googlesource.com/1591483 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
* ish: preserve panic data across resetJack Rosenthal2019-05-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit stores panic data across reset by storing panic data in the last 256 bytes of AON memory (before AON ROM). > crash divzero ========== PANIC ========== Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E Resetting system... =========================== ... ISH reset ... > panicinfo Saved panic data: (NEW) Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E BUG=b:129425206 BRANCH=none TEST=see console output above (on arcada_ish) Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1593418 Reviewed-by: Jett Rink <jettrink@chromium.org>
* 7-seg display: Add config to display port80 msg and power statesAyushee2019-05-031-0/+7
| | | | | | | | | | | | | | | | | Adding this CL to display port80 message and power states of EC & SOC on the 7-segment display. BRANCH=None BUG=b:130738086 TEST=Manually tested on intelrvp, able to verify the power states and port80 message displayed on the 7 segment display Change-Id: I4437cfcd60662c8637e406e425f98fad1a4ba7ed Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1575433 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add buffer_units_mask member into struct queueNamyoon Woo2019-05-021-9/+9
| | | | | | | | | | | | | | "q->buffer_units - 1" is performed many times to wrap head and/or tail. It should be calculated once. BUG=None BRANCH=cr50 TEST=None Change-Id: I9714147d5a97afd7aaba00d31a8b10bad50d0942 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1572444 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* usb: add inline helper method for CC linesJett Rink2019-05-023-44/+15
| | | | | | | | | | | | | | | | Expressing logic for CC lines can get very verbose. Add helper inline methods that logical describe the condition we are testing to clean up call sites. BRANCH=none BUG=none TEST=Builds, no functional change. Change-Id: I48c117437bc14f3c55473df7f7c778b55af2706d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1589906 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Sam Hurst <shurst@google.com>
* pinweaver: fix memory leak introduced when moving to new nevmemVadim Bendebury2019-05-021-4/+3
| | | | | | | | | | | | | | | | | | Not all code paths were covered which results in leaking memory allocated for temporary storage of pinweaver variables. With this patch there memory is returned to the heap in all cases. BRANCH=cr50, cr50-mp BUG=b:69907320 TEST=multiple successive reboots of the Chromebook do not cause Cr50 resets due to memory allocation failures any more. Change-Id: I432bf44e25ce2a99df9ad580b350984f4b133b2c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1588876 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* nvmem: protect flash accesses with a mutexVadim Bendebury2019-05-021-5/+85
| | | | | | | | | | | | | | | | | | | Multiple tasks could be trying to modify NVMEM concurrently. To avoid data corruption add a mutex which guarantees that only one thread of execution has access to the flash storing NVMEM objects. Various paths accessing flash contents are now protected by the same mutex. Mutex control functions are put in wrappers, which makes it easier to add debugging code when needed. BRANCH=cr50, cr50-mp BUG=b:69907320, b:130828517 TEST=attempts to take a device through RMA open do not fail any more. Change-Id: I6424477dced20d00f6165006cd3b3968433be6d0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1584586 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* nvmem: populate default tpm objects after wipeoutVadim Bendebury2019-05-011-2/+4
| | | | | | | | | | | | | | | | | | | | | | TPM memory wipe code is removing all TPM objects from the flash, including the reserved objects, which are supposed to be always present. The assumption was that the Cr50 would be reset after the wipe out and the initialization code would populated the reserved objects with default values. But in fact Cr50 reset is not guaranteed after TPM wipeout, so it is better to call the init function explicitly to make sure that all reserved objects are in the flash at all times. BRANCH=cr50, cr50-mp BUG=b:69907320 TEST='dump' command ran on the Cr50 console after RMA open shows all reserved objects present. Change-Id: Id9e227de0995c6491da9f38fc8ca11df3661c71f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1584658 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* battery: Consolidate battery_manufacturer_nameDaisuke Nojiri2019-05-011-0/+11
| | | | | | | | | | | | | | | | | | | | | Currently, the battery_manufacturer_name API is implemented individually by each chip. This patch consolidate the definitions. It also allows a board to return custom manufacturer names. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129599895 BRANCH=none TEST=buildall Change-Id: Ib0f60c9be71fea31658ab284a915d73341b9145e Reviewed-on: https://chromium-review.googlesource.com/1590039 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nvmem: add test of recovery from interrupted savesVadim Bendebury2019-05-011-0/+5
| | | | | | | | | | | | | | Add a test which introduces corrupted objects in the flash and verifies that the initialization function is able to recover. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST='make run-nvmem' succeeds Change-Id: Ibb7d8181dfdeb097b79087cdae824564ec28921f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1590044 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: fix delimiter creation during setvar()Vadim Bendebury2019-05-011-16/+54
| | | | | | | | | | | | | | | | | | | | The (key, value) objects should not be treated differently from TPM objects when initializing NVMEM from some inconsistent state. Saving of a modified (key, value) object should include the 'incomplete delimiter' phase when the new value has been already saved, but the old value has not yet been eliminated. Added tests verifying various failure modes. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST='make run-nvmem' succeeds Change-Id: Ia53b6cfa2edd59fef28ace6978d752ca3cfbb2aa Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1590043 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: add logging and restart on app_cipher failuresVadim Bendebury2019-05-011-2/+5
| | | | | | | | | | | | | | | Just in case there is a failure when encrypting or decrypting NVMEM objects, add code which detects problems, reports them in the flash log and reboots. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST=none Change-Id: I22e55941f459b5b45bf4b23781b20601a56b40d8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1590042 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* common: led_pwm: Enable pwm modules for each channels of LEDs.Mulin Chao2019-05-011-1/+21
| | | | | | | | | | | | | | | | | | | | | Since pwm_set_raw_duty() won't enable pwm module when its duty is not zero automatically after CL 1475096 was merged, this CL enables all pwm modules used by LEDs in init_leds_off(). Then we can see pwm output signals when set_led_color() is executed. BRANCH=none BUG=b:123552920 TEST=No build errors for npcx7 series. LED light was observed on grunt when a charger is plugged in. Change-Id: Icd2d19d24dc0354519561f145244f9ae8e9af93b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1575883 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
* Flapjack: Disable charging from BC 1.2 charger as USB-C chargerDaisuke Nojiri2019-04-301-1/+2
| | | | | | | | | | | | | | | | | | | | | Currently, if a charger shows Rp=USB on USB-C port, the charge manager chooses it and sets the max current to 500 mA even if it can provide higher power as a BC 1.2 charger. This patch introduces CONFIG_USBC_DISABLE_CHARGE_FROM_RP_DEF. When it's defined, a BC 1.2 charger won't be recognized as a USB-C charger. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/131353444 BRANCH=none TEST=Charge Flapjack from BC 1.2 charger on USB-C port. Change-Id: I50969973026185dd2aecdb768985cd116c1d32f7 Reviewed-on: https://chromium-review.googlesource.com/1586580 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* motion sense: Calculate loop time based on sensor needsMathew King2019-04-271-67/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the motion sense loop bases its sleep time based on the fastest active sensor. This method has several flaws: 1. It does not take into account any task switching overhead 2. With a mix of interrupt driven and forced sensors the sleep time gets recalculated every time there is an interrupt causing the loop to oversleep 3. If multiple sensors do not have rates that are in sync the timing of the slower sensor will be off. For example if there was a sensor running at 50 Hz and one running at 20 Hz the slower sensor would end up being sampled at about 16 Hz instead of 20 Hz This change calculates an ideal read time for every forced mode sensor and calculates the sleep time based on the nearest read time. Every time a sensor is read the next read time is calculated based on the ideal read time not the actual read time so that reading does not drift because of system load or other overhead. BUG=b:129159505 TEST=Ran sensor CTS tests on arcada, without this change the magnetometer was failing 50 Hz tests at about 38 Hz with 30% jitter with this change in place 50 Hz was spot on with about 10% jitter BRANCH=none Change-Id: Ia4fccb083713b490518d45e7398eb3be3b957eae Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1574786 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ccd: delay sleep while opening ccdMary Ruthven2019-04-272-16/+11
| | | | | | | | | | | | | | | | | Cr50 may enter deep sleep while wiping the TPM. This change adds a sleep delay before opening ccd. BUG=b:130646257 BRANCH=cr50 TEST=manual dut-control cold_reset:on run ccd open make sure ccd is open even after entering deep sleep Change-Id: Id44b608702b664621bd2441f62a03ba6428135cf Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1585606 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* cr50: Support legacy U2F key handlesLouis Collard2019-04-251-5/+48
| | | | | | | | | | | | | | | | | | | | | | The new U2F functions make use of a new key derivation scheme. This adds a flag clients can specify that allows the new functions to also sign requests using a legacy key handle. This will allow continued support of legacy key handles in Chrome OS whilst allowing the legacy code to be removed from cr50. BUG=b:112603199, b:123161715 TEST=with new cr50 and u2fd patched to send new param: - register legacy key handle with Google - restart u2fd with user keys and no fallback - check login fails - restart u2fd with user keys and fallback - check login succeeds Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: Ib3164e9c0856d51b958fa8db181153b5b2227850 Reviewed-on: https://chromium-review.googlesource.com/1580622 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* tasks: convert TASK_EVENT_CUSTOM macro to bitJett Rink2019-04-246-11/+11
| | | | | | | | | | | | | | | | | | | | | We should ensure that all custom task definition are non-zero and fit with the globally defined events. Add compile time check and change semantics to specify bit number (instead of making all callers use the BIT macro). This also fixes an error with TASK_EVENT_PHY_TX_DONE for ITE being 0. The bug that made that happen hasn't landed on any firmware branches that use it though. BRANCH=none BUG=none TEST=builds Cq-Depend:chrome-internal:1178968,chrome-internal:1178952 Change-Id: I5e1d1312382d200280c548e9128e53f4eddd3e61 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570607 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-241-15/+2
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* cleanup: update TASK_EVENT_CUSTOM usageJett Rink2019-04-231-11/+10
| | | | | | | | | | | | | | | | | | The lightbar.c uses the TASK_EVENT_CUSTOM macro in a non-standard way comparing it to the rest of the code base. Update the style in preparation for changing the TASK_EVENT_CUSTOM macro to be a BUILD_CHECK_INLINE macro. Without this cleanup CL, this code breaks. BRANCH=none BUG=none TEST=builds Change-Id: I4fdbb35a2aeeb1f8718b22c017607aee5fa1730a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570606 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* P9221: Add P9221 driverTony Zou2019-04-222-1/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds P9221 driver and enable it for Flapjack. The driver originates from https://android.googlesource.com/kernel /msm/+/android-msm-bluecross-4.9-pie-qpr1/drivers/power/supply/qcom /p9221_charger.c CQ-DEPEND=CL:1445133 CL:1551583 BRANCH=none BUG=b:126162615 TEST=Verify charging from PD and WPC as follows: 1. Charge with PD charger. Place DUT on WPC charger. -> PD charger continues to charge. 2. Unplug PD charger. -> WPC starts charging as GPP. 3. Plug PD charger. -> PD charger starts charging at 2A@9V TEST=Verify OTG and WPC functionality as follows: 1. Plug fan to USB port: -> Fan spins 2. Place DUT on WPC charger: -> WPC starts charging as GPP. Fan continues to spin. 3. Remove DUT from WPC charger: -> Fan continues to spin. 4. Do 1 and 2 then unplug USB fan: -> WPC starts charging. TEST=/sys/class/power_supply/CROS_USBPD_CHARGER0/usb_type is BrickID /sys/class/power_supply/sbs-12-000b/status is ok Change-Id: I5fbd0237cedd8095f98582c39973d432e733f2cd Signed-off-by: Tony Zou <zoutao@huaqin.corp-partner.google.com> Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1448193 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* factory_mode: refactor factory_enable_failedMary Ruthven2019-04-221-17/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor factory_enable_failed, so cr50 always resets if a reset is requested. This change also renames factory_enable_failed to be more specific. It renames ccd_hook_active to wait_for_factory_ccd_change so it's obvious what the variable is doing. It's waiting for the ccd_config change after we enable factory mode. Enabling factory mode can fail in a lot of ways, but by the time we called factory_enable_failed, the failure is specifically about saving the config. This change renames the function, so the failure is a bit more specific. If a reset is required, always reset the system even if saving the factory config failed. ccd_reset_factory_failed is triggered if the ccd changed hook isn't triggered quickly enough or if cr50 fails to save the ccd config. Cr50 has already wiped the TPM and has most likely saved some if not all of the factory mode state. Cr50 should still reset even if the config isn't saved to be safe. enable_ccd_factory_mode isn't used in the process to enable factory mode during init, so this change won't cause a cr50 reboot loop from cr50 trying and failing to enable factory mode during init. This only affects the RMA and factory mode enable vendor commands. BUG=b:129956462 BRANCH=cr50 TEST=Use rma and factory mode vendor commands to enable factory mode. Change-Id: Ib8a502297040296fb0a2250a9e8945af330d4334 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1572450 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* common: led_onoff_states: add new LED state for fully charged in S5Devin Lu2019-04-201-3/+20
| | | | | | | | | | | | | | | | Synchronize with CL:1419477 to common/led_onoff_states. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ibb5d9150f03cb7a584d7439bc47d5b59de856502 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1556859 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ccd: make ccd open error more meaningfulMary Ruthven2019-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | | Right now if 'ccd open' from the console fails, it pretty much always fails with "nopwd". This error is pretty meaningless, because you can't even set the password until you open ccd. This change suggests removing the battery or sending the open command from the AP in dev mode if ccd open fails. This error should help people remember their device needs to be in dev mode and open needs to be sent from the AP. BUG=b:73170050 BRANCH=cr50 TEST=try 'ccd open' from the console. Verify the error message is changed. Change-Id: I32ca72ed00e03e62d73942961137591dc69bc8fa Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1572156 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* common/usbc_ppc: Fix potential illegal memory access.Tim Wawrzynczak2019-04-191-1/+3
| | | | | | | | | | | | | | | Recent coverity scan indicated a potential illegal memory access in ppc_enter_low_power_mode(). This patch fixes it. BUG=none BRANCH=none TEST=Compiled Change-Id: I0df1ca23340cd4466f8e71349b89ca1ab68aadbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1574099 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* CBI: Allow board to compose data from other sourcesDaisuke Nojiri2019-04-191-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the source of CBI data is only EEPROM. This patch allows CBI data to be composed from other sources such as ADC or some chip register. cbi_board_override is called by CBI library when data is being requested. Boards can implement this callback to add additional bits or bytes to the data. A board itself may need to get CBI data first to manipulate data properly. For such a case, a board can return EC_ERROR_BUSY to inform the callers that the data is not fully ready while a board itself can accept EC_ERROR_BUSY as an expected value. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129569858 BRANCH=none TEST=Read LCM_ID properly Change-Id: Ie1f962c64c8d1461a6c171bc6c6d0c855c82e945 Reviewed-on: https://chromium-review.googlesource.com/1572439 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Common: move for loop initial declarationDiana Z2019-04-181-2/+6
| | | | | | | | | | | | | | | While builds on cros/master allow variables to be initially declared in for loop statements, builds on firmware branches (ex. octopus) may not. BUG=None BRANCH=octopus TEST=builds on master, builds picked to octopus branch Change-Id: I450d8c564b508a5f51a7784ce67b0664ab97d8ba Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570609 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* util/ectool, common/system: Share sysmbol reset_flag_desc.Yilun Lin2019-04-181-10/+10
| | | | | | | | | | | | | | | | | There were two symbols reset_flag_desc and reset_flag_strings used in two separated places: host binary ectool and device. This CL combines these two symbols to reduce maintance efforts. TEST=make buildall -j BRANCH=None BUG=None Change-Id: I3b5731ab08804f46629d6e43466dce963bd86a69 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1514395 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* led_pwm: use NEAR_FULL_COLOR when discharging-on-acCaveh Jalali2019-04-181-1/+2
| | | | | | | | | | | | | | | | | | | | | | when CONFIG_PWR_STATE_DISCHARGE_FULL is enabled for a board, the charge state machine can enter a special PWR_STATE_DISCHARGE_FULL state used to indicate that we're on AC but powering the system from the battery. the system will hover in-and-out of this state over time while on AC. this should generally be transparent to the user, so we should indicate it using the LEDs the same way we indicate PWR_STATE_CHARGE_NEAR_FULL. BUG=b:128709632 BRANCH=none TEST=verified LED stays white on atlas while battery is draining on AC. LED goes out when charger is removed Change-Id: I3af6783bcdbe399a444099fcee8ebab07451ff2c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570613 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mkbp: handle multiple writes of interruptJett Rink2019-04-181-76/+224
| | | | | | | | | | | | | | | | | | | We need to handle the case of multiple tasks trying to set the mkbp interrupt while the host command task is trying to clear it. The setting of the interrupt may also take a while and we need to ensure that we synchronize correct after a longer delay. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change TEST=pass CTS sensor run on eSPI-based system TEST=pass CTS sensor run on GPIO-based system Change-Id: I056b72c1210d7525c29a8555f97e6f09d773d12f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1560229 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* USB PD: Re-discover port partner when a contract was in placeDiana Z2019-04-182-1/+53
| | | | | | | | | | | | | | | | | | | | | | When the pd_task starts up with an explicit contract previously in place, re-check the partner's identity. This will happen automatically when we EC reset into RO since pd_chipset_startup sets the flag, but for a RO->RW jump the flag needs to be set again. Additionally, exit DP modes before sysjumping, in order to not confuse the port partner with a second enter mode when it had previously been in that mode. BUG=b:125552060 BRANCH=octopus TEST=on unlocked octopus board, plugged in powered HDMI dongle from hibernate state and confirmed display worked after RO->RW jump. Also turned off software sync and confirmed console "sysjump" worked. Change-Id: Idcde6f04deeb8f409a9b4d0a4b3fc924bdb644c7 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1506434 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_manager: Move source_port_bitmap definition where it's usedDaisuke Nojiri2019-04-181-5/+4
| | | | | | | | | | | | | | | | | | | This patch moves the definition of source_port_bitmap to the location where it's referenced to increase the readability. There is no functionality change. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I9dcdc3ec10c2f71b9f95c271f86ba31e436e697c Reviewed-on: https://chromium-review.googlesource.com/1566481 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd_protocol: Allow charging @ 500mA from Rp-USB.Aseda Aboagye2019-04-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | A USB Type-C ECN "Title: Default Current Clarification for non-USB Devices", allows a sink to draw 500mA based off of a Default USB Rp advertisement. This is especially important for devices which lack the hardware to detect legacy sources via BC 1.2. This commit will now allow those devices to charge at 5V/500mA. BUG=b:117805314,b:124138725 BRANCH=firmware-nocturne-10984.B,master TEST=Flash nocturne, plug in USB-A to USB-C cable, verify cable is detected as a charger and that we charge from it. Change-Id: I1f40cca7246c6d671c7775869da64cf30f649dc4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1431252 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> (cherry picked from commit 9509f9aa3322fb180f51064309875589c8b90973) Reviewed-on: https://chromium-review.googlesource.com/1565463 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Matthew Blecker <matthewb@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* kukui: remove flashpd/rwhashpd host command from ROTing Shen2019-04-171-1/+4
| | | | | | | | | | | | | | | | | | | | | Kukui is running out of RO space. In order to save more space, we found that these two functions takes ~500 bytes, so it's especially worth removing. RO size before and after: 122056 Apr 11 17:01 build/kukui/RO/ec.RO.flat 121544 Apr 11 18:14 build/kukui/RO/ec.RO.flat BUG=b:120588396 TEST=make buildall -j BRANCH=None Change-Id: I2e08d45093d5ef88516950e8289e559d4421d126 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1564490 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* USB PD: Suspend ports when resetting TCPCs during cold rebootDiana Z2019-04-151-1/+9
| | | | | | | | | | | | | | | | | | | Currently, when EC cold reboots run, they reset the board's TCPC chips, but do not communicate this fact to the PD tasks. This may lead to the PD tasks reading register values with are incorrect or not yet initialized. Before resetting the TCPCs, put each port into suspend to prevent this. BUG=b:129092057 BRANCH=octopus TEST=Ran several EC resets as well as EC cold reboots with source and sink partners, verified we successfully maintained connection with the port partner without hitting contract disagreements Change-Id: I6d509c4c6b22400b6250e2740e7927be92373802 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538751 Reviewed-by: Jett Rink <jettrink@chromium.org>
* button: fix compile error when CONFIG_LED_COMMON not definedTing Shen2019-04-111-0/+2
| | | | | | | | | | | | | | | | Compiler complains about debug_mode_blink_led defined but not used. Fix this. BUG=None TEST=make BRANCH=None Change-Id: I6f5431d0867bc4f37bc1e74d48f4b124305d4012 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1559100 Commit-Ready: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* pd: Apply Rd prior to sending PS_RDY in PRSWAP.Aseda Aboagye2019-04-091-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | According to the PD spec, in a Power Role swap, the initial source must change its termination from Rp to Rd prior to sending the PS_RDY control message. This commit fixes a bug where we were changing our termination *after* sending the PS_RDY control message. BUG=b:113207208, b:116340006 BRANCH=firmware-nocturne-10984.B,master TEST=Plug in charge thru hub with charger plugged into nocturne, verify PR swap succeeds and the CC lines don't float to vOpen. TEST=Plug in Pixel phone into nocturne, do a PR swap, verify that the CC lines don't float to vOpen. Change-Id: If041595baa77d2494c4caff3660151329bfd4926 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1381633 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 31dfe0b1a6b43b01bc89f45e6d3a4ac78b823959) Reviewed-on: https://chromium-review.googlesource.com/1388845 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chocodile_vpdmcu: Firmware for chocodile mcuSam Hurst2019-04-086-2/+2577
| | | | | | | | | | | | | | | | | | Implement Chocodile Charge-Through Vconn Powered firmware for mcu using new Type-C/PD State machine stack. BUG=b:115626873 BRANCH=none TEST=manual Charge-Through was tested on an Atlas running a DRP USB-C/PD state machine with CTUnattached.SNK and CTAttached.SNK states. Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: I847f1bcd2fc3ce41e66edd133a10c943d5e8c819 Reviewed-on: https://chromium-review.googlesource.com/1225250 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* cr50: use board_wipe_tpm to clear the tpmMary Ruthven2019-04-052-34/+5
| | | | | | | | | | | | | | | | | | | | | | | | | We were clearing the tpm in two different ways. There was one implementation in factory_mode.c and one in wp.c. This change merges the two, so there's only one board_wipe_tpm. While modifying the wipe tpm code from factory_mode.c I noticed the factory_enable_failed stuff is maybe a bit more complicated than necessary. I opened a bug for cleaning that up(b/129956462). It wont be addressed in this change. BUG=none BRANCH=none TEST=Run the processes that wipe the tpm open ccd. enable factory mode from vendor command. run rma open process Change-Id: Ia76df19f7d9e4f308f3f1a7175f130f1ef7249a2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535156 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: complete support of the new NVMEM structureVadim Bendebury2019-04-058-570/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch eliminates unnecessary legacy nvmem.c and nvmem_vars.c code and brings the code base to the state where the new NVMEM layout is fully functional. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 CQ-DEPEND=CL:1450278 TEST=the following tests pass: - test cases in ./test/nvmem.c - TCG suite (passes on par with the existing Cr50 code with the reduced code footprint TPM2 library) - Chrome OS device migrates from legacy to new implementation with user account maintained. - Chrome OS user account is maintained over AP and H1 reboots and deep sleep cycles. Change-Id: If4bc2dd125873a79dbe0e268eb32100a8b8b352d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496607 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: convert functions into staticNamyoon Woo2019-04-052-2/+2
| | | | | | | | | | | BUG=b:112778363 BRANCH=cr50 TEST=ran test_that suite:faft_cr50_prepvt on coral. Change-Id: I1b3c573ee5fcb40290541f231c78bf31650c13c4 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1410482 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cbi: Allow cbi command included optionallyDaisuke Nojiri2019-04-051-0/+3
| | | | | | | | | | | | | | | | | | | | Currently, console command 'cbi' is always included when cbi is enabled. This patch adds CONFIG_CMD_CBI so that a board can choose to include or exclude the command. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/129746223,b/127720872 BRANCH=none TEST=buildall Change-Id: I465d9b52af91d54a686022bf19a1c4e698d2a727 Reviewed-on: https://chromium-review.googlesource.com/1552359 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org>
* gpio: add config option for using gpio_get_flagsMary Ruthven2019-04-051-1/+1
| | | | | | | | | | | | | | | Separate gpio_get_flags from the CONFIG_CMD_GPIO_EXTENDED, so we can enable getting the gpio flags without enabling the ability to set them. BUG=none BRANCH=cr50 TEST=none Change-Id: Ib8e3a13fdcfe8ebec4523eb070b2425b5dc28278 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1542798 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kblight: Remove dependency on PWMDaisuke Nojiri2019-04-044-4/+6
| | | | | | | | | | | | | | | | | | | | | | Keyboard backlight can be controlled either by PWM or an external controller. This patch decouples keyboard backlight common code and PWM based backlight control. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=Nami TEST=Verify keyboard backlight can be adjusted on Ekko. Change-Id: I332b01a2a2b15bd37ce385b6c30591c90f078dfc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1549476 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> (cherry picked from commit e879713cee3212b4afffb3f0dd3c4dfbf8237c4a) Reviewed-on: https://chromium-review.googlesource.com/1549606 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: New NVMEM flash storage implementationVadim Bendebury2019-04-041-0/+2956
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is a proposed implementation of the new TPM NVMEM flash layer. There is a big comment block in common/new_nvmem.c describing the approach taken, changes to the API and outstanding issues. This implementation follows the design document attached to b:69907320. With all required changes to the rest of the code this new flash storage scheme consumes 7816(!) bytes of code storage. One of the more important aspects of this implementation is that the (key, value) pair objects are stored in the flash only, they are not duplicated in the SRAM cache. The advantage of this is that there could be more space dedicated to these objects. Soft limit is set to 1K as opposed to 272 bytes available with the legacy scheme. The major disadvantage is the need for the user not to forget to release the (key, value) pair retrieved from NVMEM, as it occupies space on the heap. BRANCH=cr50, cr50-mp BUG=b:69907320, b:129710256 TEST=with the rest of the patches applied the following tests pass: - test cases in ./test (completely reworked for the new scheme) - TCG suite (passes on par with the existing Cr50 code with the reduced code footprint TPM2 library) - Chrome OS device migrates from legacy to new implementation with user account maintained. - Chrome OS user account is maintained over AP and H1 reboots and deep sleep cycles. Change-Id: I6252649597c03abd4a08e2d55d61e384fe037ef7 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1450277 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* factory_mode: change how reset_required is savedMary Ruthven2019-04-031-1/+1
| | | | | | | | | | | | | | | | Logically OR reset_required with the saved reset_required state when enabling factory mode, so there is no way to cancel a reset once it's requested. BUG=none BRANCH=cr50 TEST=enable factory mode. Change-Id: I7a432989b83946570a914f27e806ec2dbc9e9791 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add command to override BATT_PRES_LMary Ruthven2019-04-031-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | We use BATT_PRES_L to determine if factory mode can be enabled. We need to be able to control this for cr50 testing. Add a command that can be used to override battery presence. This change also adds a ccd capability to control access to this command. If this capability is enabled, someone can easily use console commands and AP commands to enable factory mode, so it should be controlled separately from WP and GscFullConsole. BUG=b:126197850 BRANCH=cr50 TEST=override battery presence using bpforce. Make sure the state lasts through reboot, deep sleep, and power-on reset. When bp is forced disabled you can do ccd open without physical presence and you can enable factory mode. Change-Id: I026a537142b6780824192caa2a147c7bdac1545c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1505213 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
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