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* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-156-21/+26
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* TCPMv2: Process DPMs before discoveryDiana Z2021-01-141-26/+22
| | | | | | | | | | | | | | | | | | | | | | Some devices may reply to discovery differently if they're not yet being offered sufficient current. Process DPM requests before running discovery in order to get these devices into the best state for discovery probing. This also moves the cable soft reset DPM request up to the common DPM request function. Otherwise, it will be considered an unhandled request and dropped before attempting discovery. BRANCH=volteer BUG=b:177303467,b:177001425 TEST=verify we can reliably receive DiscoverSVIDs ACK from LaCie SSD Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I0917476c2aeb0cb9551edde3df14ddd1fd47fcab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627805 Tested-by: Utkarsh H Patel <utkarsh.h.patel@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* USB-PD: filter duplicated SVIDEric Yilun Lin2021-01-141-4/+24
| | | | | | | | | | | | | | | | | | | We have seen some peripherals may broadcast duplicated SVID, and this might cause the SM in a weird state in that the SVID disocvering traverses sequentially by pd_get_next_mode(), and this cause the SM discovering SVID modes over and over again. We filter out the duplicated SVID to prevent such scenario. BUG=b:177285652 TEST=Plug adapter ADLX65YCC3A, and ensure no repeated discover_mode for NAKed SVIDs. BRANCH=none Change-Id: I68811be039e214c5045fb71bb7025bcc6226a051 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2626795 Reviewed-by: Diana Z <dzigterman@chromium.org>
* board/genesis: Totally remove CONFIG_CHARGE_MANAGER andNeill Corlett2021-01-131-1/+1
| | | | | | | | | | | | | | CONFIG_USB_POWER_DELIVERY. Hardcode extpower_is_present() to 1 as the barrel jack is the only means of powering the board. BUG=b:173566595 TEST=Flashed to my Endeavour-C EVT1; reaches "Starting kernel" Change-Id: Ie456646bae2ca7ff5249d66bf0848fdd08caa6b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2624927 Tested-by: Neill Corlett <corlett@google.com> Commit-Queue: Neill Corlett <corlett@google.com> Reviewed-by: Matthew Ziegelbaum <ziegs@chromium.org>
* TCPMv2: Do not perform hard reset when battery is lowPatryk Duda2021-01-121-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds checking for enough battery level before sending hard reset in PE_SNK_Hard_Reset state. There are a lot of reasons causing Policy Engine to send hard reset. One of them is timeout in PE_SNK_Wait_For_Capabilities, which can cause brown out if battery doesn't have enough charge New flag PE_FLAGS_SNK_WAITING_BATT was added. This flag is set on PE_SNK_Hard_Reset entry, and can be cleared when battery reaches minimal charge (see pe_update_waiting_batt_flag()). Original fix implemented for TCPMv1 stack: https://chromium-review.googlesource.com/1565147 https://chromium-review.googlesource.com/1980406 BUG=b:160243307, b:161775827 BRANCH=none TEST=Get board with bad battery (eg. bobba). Flash ToT EC. Discharge battery to cutoff. Plug charger. Make sure that PD goes to PE_SRC_Disabled after PE_SNK_Wait_For_Capabilities tries to send hard reset (switches to PE_SNK_Hard_Reset). PD should remain in PE_SRC_Disabled state until battery reaches minimal charge. It might be necessary to limit PD_CAPS_COUNT (in my case to 10) in ServoV4 (used as charger) to actually trigger timeout. During test EC RO have to report that PD comm is disabled, in other words system must be locked. When battery charges quickly, it is allowed to do 'sysjump RW'. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I63ac93a093d921f41bea2af93de8325783056962 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600985 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Hand over Hard Reset send request to PE when availablePatryk Duda2021-01-121-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | When calling pd_send_hard_reset() PD_EVENT_SEND_HARD_RESET event is sent. This event is handled in tc_event_check() function, tc_hard_reset_request() is called and TC_FLAGS_HARD_RESET_REQUESTED is set. As a consequence Type-C layer performs Hard Reset without sending any information to port partner. In addition when PE is available, Type-C layer will set PE_FLAGS_PS_RESET_COMPLETE PE flag unexpectedly. This is fixed by passing Hard Reset send request to PE layer which will perform it correctly. Currently Hard Reset send using PD_EVENT_SEND_HARD_RESET is used only as reaction to overcurrent. BUG=b:160243307 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I71bd073a466942d86194cec1aa3787946b695924 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2618003 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Send Hard Reset from any state on DPM requestPatryk Duda2021-01-121-18/+22
| | | | | | | | | | | | | | | | | | | | | | | | | USB PD specification states that we can send Hard Reset on DPM request regardless of state we are currently in (see USB PD Specification 8.3.3.3.8). This patch implements changing state to PE_SNK_Hard_Reset or PE_SRC_Hard_Reset depending on current power role when requested by DPM. Currently, requests can come only from PD console. BUG=b:160243307 BRANCH=none TEST=Connect DUT to ServoV4. Configure ServoV4 as source using 'cc src' or 'cc srcdts'. Issue Hard Reset from DUT EC console using 'pd 0 hard'. Check if transition PE_SNK_Ready -> PE_SNK_Hard_Reset occurs. Configure ServoV4 as sink using 'cc pdsnk' or 'cc pdsnkdts'. Issue Hard Reset from DUT EC console using 'pd 0 hard'. Check if transition PE_SRC_Ready -> PE_SRC_Hard_Reset occurs. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I46a0446ff9dd417bab19fd13d71aa11e8aa83d04 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2618002 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv1: Replace charging allow listTing Shen2021-01-123-81/+31
| | | | | | | | | | | | | | | | This CL backports CL:2535217 to TCPMv1, and completely removes charging allow list. BRANCH=kukui BUG=b:175364716 TEST=on Burnet, verify DUT can charge from power bank. Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I89476c89fd4ab6d46acf880f7573b5deb8b2c0f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2603614 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* COIL: Remove non-inclusive words from common mockDossym Nurmukhanov2021-01-121-3/+3
| | | | | | | | | | | BUG=none BRANCH=none TEST=make runhosttests Signed-off-by: dossym@chromium.org Change-Id: I7338c137540ddf08886887d66ac92e7b7d57911c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622068 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* COIL: Remove non-inclusive words from i2c codeDossym Nurmukhanov2021-01-122-50/+50
| | | | | | | | | | | BUG=none BRANCH=none TEST=Build npcx9 and coachz boards Signed-off-by: dossym@chromium.org Change-Id: I7f2ccd80e595e0ee24ff56ecde8d810a1f8b98cb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622067 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* COIL: Remove non-inclusive words from Bluetooth codeDossym Nurmukhanov2021-01-121-2/+2
| | | | | | | | | | | BUG=none BRANCH=none TEST=build hadoken Signed-off-by: dossym@chromium.org Change-Id: I9a453bcdf14b3a6823bad23824aaee77a7013a81 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2622066 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx/system: LCT compensate for MTC in PSL_hibernateWealian Liao2021-01-121-0/+4
| | | | | | | | | | | | | | | | | | | | | NPCX chip uses the MTC module as the RTC counter. However, in PSL hibernate, MTC will stop counting. NPCX9 supports the LCT module which could count continuously when VCC1 power is off. The CL uses LCT to compensate for the MTC counter value after PSL hibernate wake-up. The LCT maximum counting value is 16 weeks. BRANCH=none BUG=b:165777478, b:171919875 TEST=pass "make buildall" TEST=Check the RTC value in the following scenario: 1. "hibernate" and wake up EC by PSL input. 2. "hibernate 30" and wake up EC after timeout. 3. "hibernate 30" and wake up EC by PSL input before timeout. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I39e370a437f40749acbd3a35a8b37ebec70f1bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506864 Reviewed-by: Keith Short <keithshort@chromium.org>
* COIL: Rename EC-EC comm defines to be more inclusiveDossym Nurmukhanov2021-01-121-17/+17
| | | | | | | | | | | | BUG=none BRANCH=none TEST=Build and run on a device Signed-off-by: dossym@chromium.org Change-Id: I48d1ec4be528ac3c39f81740016f11d7eca3c740 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2619070 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* TCPMv2: Defer initializing type-C supplier current limitWai-Hong Tam2021-01-111-16/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initializing all of the suppliers seeds the charge manger and a supplier is then selected (a corresponding charger input current is configured). Originally, both PD and type-C suppliers are unconditionally initialized in the restart_tc_sm() that seeds the charge manger. A lower current supplier (the default VBUS supplier) is selected first before the type-C current detection. A issue happens on the first boot from battery cutoff, the EC RO detects 5V 3A and boots AP. When sysjump to RW, the default VBUS supplier (5V 0.5A) is used first and limits the charger input current to some lower value. It makes AP out of power. This change defers the type-C supplier initialization to either Unattached.SNK (new) or Attached.SNK. In Unattached.SNK, we debounce the CC open status to make sure CC open and then initialize the type-C supplier. As some TCPC needs time to get the CC status valid. Before that, CC open is reported by default. It misleads the decision. We reuse the existing role toggle timer to debounce. And also align the transitions to DRPAutoToggle and LowPowerState to simplify the logic. BRANCH=Trogdor BUG=b:174105232, b:175663604 TEST=Verified the first boot from cutoff, AP still ON after sysjump to RW. TEST=Verified type-C detection, PD detection, and BC 1.2 detection still work correctly. Change-Id: Ia5d714a15d3f556463cf38e11130151e1f1477cb Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2619338 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* COIL: Rename non-inclusive wordingDossym Nurmukhanov2021-01-111-16/+17
| | | | | | | | | | | | | | Use controller/peripheral nomenclature. BUG=none BRANCH=none TEST=Build a device that uses i2c_bitbang (e.g. jacuzzi) Signed-off-by: dossym@chromium.org Change-Id: I597e1bf2f86ca93fe8b2230d603345033f43ed96 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2619071 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* crash: fix unsigned div-by-zero crashEric Yilun Lin2021-01-111-1/+1
| | | | | | | | | | | | | The bug was introduced in chromium:1834603 BUG=chromium:984041 TEST=ensure crash udivzero is triggered BRANCH=none Change-Id: I83d7465d1bbe41976c78c7d298abdafd3670e8cd Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2620725 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: switch to platform/ec printf format implementationJack Rosenthal2021-01-091-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Prior to this change, the cprints and cprintf shim implementations used Zephyr's printk to do the output formatting. Our EC code has some custom printf specifiers not supported by Zephyr's printk. We've already attempted to send some of our custom specifiers upstream, but upstream does not want them: https://github.com/zephyrproject-rtos/zephyr/pull/28882 The logical thing to do would be to bring in the vfnprintf function from our EC to the Zephyr build, and use that to do the output formatting instead. That's what this CL does. The binary cost of brining in this second printf implementation appears to be minimal (952 bytes on volteer). BUG=b:177065615 BRANCH=none TEST=on posix-ec and volteer, run gettime and observe output no longer contains %.6lld, but instead the correct system time Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I53cd4edf129223c12a2c5e7d0519623a8d07a328 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2618575
* tcpmv2: Use cable soft reset state during VCSKeith Short2021-01-091-82/+17
| | | | | | | | | | | | | BUG=b:152058087 BRANCH=volteer TEST=Connect to monitor as SRC, verify SOP' soft reset sent after VCONN swap and before SOP' DiscoveryIdentity. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If8b52ed033b1ee78d61958d6c9bf5d7ff01bc8dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601143 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* tcpmv2: always issue SOP' soft resetKeith Short2021-01-091-0/+114
| | | | | | | | | | | | | | | | | | | After entering a PD contract, always issue an SOP' soft reset before sending any discovery VDMs to the cable. BUG=b:172364575 BRANCH=volteer TEST=connect monitor with emarked cable, verify SOP' soft reset is sent when EC starts as SNK/DFP. TEST=Connect monitor with non-emark cable. Verify SOP' soft reset is sent once regardless of starting role. TEST=Connect USB4 dock, verify USB4 entry. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Id5026a2c8c9877b860e1356dd33763bad3e51841 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2596838 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* tcpmv2: correct MessageId handling during soft resetKeith Short2021-01-091-23/+30
| | | | | | | | | | | | | | | | | | | | Change the soft reset handling in the PRL to reset the MessageId counter only for the matching message type. From section 6.3.13 Soft Reset Message in the USB PD 3.0 v2.0 spec, Soft_Reset Message Shall be targeted at a specific entity depending on the type of SOP* Packet used. BUG=b:172364575 BRANCH=none TEST=make buildall TEST=Connect USB dock, verify MessageId sequences of SOP and SOP' are handled correctly. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I3d4b69e8d08e3691aeac024064a68599f76010a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613730 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Add custom protocol error handling for FRSEric Herrmann2021-01-081-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | For pe_report_error(), there are several cases which are handled differently than the default (soft reset), which are described in PD3.0 section 8.3.3.4.1.1. One of these is a protocol error during an FRS Send_Swap, which should be a transition to ErrorRecovery instead of Soft Reset (section 8.3.3.18.6.2). A normal PRS Send_Swap follows the default behavior. Add this exception to the default handling of protocol errors. Without this, the TCPM/TCPC will get into an incorrect state which isn't recoverable without a manual reset. BUG=b:171740860,b:148144711 TEST=make buildall TEST=On volteer, with FRS enabled, check that removing a device while primed for FRS results in a transition to ErrorRecovery instead of Soft Reset. BRANCH=None Change-Id: I350aa39d6f41e7a1d304389fd8bf2e7693cd912c Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606506 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Revert "zephyr: Update hooks shim to match ECOS"Jack Rosenthal2021-01-082-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e1224e693a33269866c1d8e1af44b325a7f69a72. Reason for revert: chumped CL is responsible for CQ failures Original change's description: > zephyr: Update hooks shim to match ECOS > > At present the hooks declaration in Zephyr doesn't use const but does > use static. This makes it incompatible with ECOS, even if it might be > more strictly correct. > > Update the hook to fix this so that we can build the missing USB code. > > BUG=b:175434113 > BRANCH=none > TEST=make BOARD=volteer > build zephyr on volteer > > Change-Id: Ib8decd11aa2adf85bb760965b0794c54854c41c7 > Signed-off-by: Simon Glass <sjg@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611895 > Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Bug: b:175434113 Change-Id: I25ef8436ae3a8fc839ce73c82dc04089ce9bac4e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2617116 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Yuval Peress <peress@chromium.org> Commit-Queue: Simon Glass <sjg@chromium.org> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Update hooks shim to match ECOSSimon Glass2021-01-072-4/+0
| | | | | | | | | | | | | | | | | | At present the hooks declaration in Zephyr doesn't use const but does use static. This makes it incompatible with ECOS, even if it might be more strictly correct. Update the hook to fix this so that we can build the missing USB code. BUG=b:175434113 BRANCH=none TEST=make BOARD=volteer build zephyr on volteer Change-Id: Ib8decd11aa2adf85bb760965b0794c54854c41c7 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611895 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ec_features: Use mask for AP mode entryAbe Levkoy2021-01-071-1/+1
| | | | | | | | | | | | | | | Convert EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY into a shifted bit before including it in features. BUG=b:168030639 TEST=Run ectool inventory; see "Host-controlled Type-C mode entry" BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Icdf713c02fb1ca0d54f4e98321b085bf0e3d4acc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2616131 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPMv2: Compliance Unit Test - TD.PD.SRC3.E7Denis Brockus2021-01-071-0/+74
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Iaa6888d2e0d861d64b2747856465789304dde414 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613724 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* UnitTest: Create battery mock for tcpmv2_complianceDenis Brockus2021-01-072-0/+212
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I1b06d512b3b869a300c981c4dd6bda54a236f342 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2614773 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Revert "TCPMv2: Decrease Low Power Mode debounce delay to 10 ms"Keith Short2021-01-071-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 5ff18dfd6ab67df2e62c6af9f20ed472808de707. Reason for revert: b:176986511 Volteer family devices need at least 75ms debounce to detect attachment of SNK devices. Original change's description: > TCPMv2: Decrease Low Power Mode debounce delay to 10 ms > > This patch decreases PD_LPM_DEBOUNCE to 10 ms. With current > 100 ms delay ANX7447 can't go to Low Power Mode due to silicon > bug (b:77544959). When DRP mode is enabled ANX7447 triggers alert > every 39.7 ms. Checking what caused an alert involves I2C > transaction which changes timeout after which TCPC goes to Low > Power Mode to get_time().val + PD_LPM_DEBOUNCE_US. As a result it > is not possible to put TCPC to LPM which is necessary to work > properly (b:149761477) > > Original value for PD_LPM_DEBOUNCE_US was 10 ms, introduced > in CL:1119255. This value is still used in TCPMv1. > For TCPMv2, PD_LPM_DEBOUNCE_US was changed to 100 ms in CL:2126078. > It is unclear why this value was changed. Review discussion and bug > b:149772936 don't mention why we needed to change that, so we change > it back to 10 ms for consistency with TCPMv1. > > Issue was found when running EC ToT with TCPMv2 enabled on bobba board. > > BUG=b:161775827, b:77544959, b:149761477 > BRANCH=none > TEST=Flash EC ToT on octopus board with ANX7447 (eg. bobba). > Make sure that DRP mode is enabled. Connect charger to port > with ANX7447 chip. Make sure that EC can connect with charger. > > Signed-off-by: Patryk Duda <pdk@semihalf.com> > Change-Id: Ia08818378a1fca424d392b4699f9c4adc460bfb5 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606235 > Reviewed-by: Edward Hill <ecgh@chromium.org> Bug: b:161775827 Bug: b:77544959 Bug: b:149761477 Change-Id: I882c077915b67b53acc73e2941ead33baabe9b5f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615118 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Update exiting Thunderbolt mode SOPAyushee Shah2021-01-071-1/+1
| | | | | | | | | | | | | | | | On receiving the ack for exiting thunderbolt mode SOP, call the tbt_exit_done() function instead of only clearing TBT_FLAG_RETRY_DONE flag. BUG=b:173459141 BRANCH=none TEST=Able to enter and exit AP driven Thunderbolt mode Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: Icc941beec027f808aa2eafd5190c977640b7599e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613727 Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-078-8/+8
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* usb_pd: correct PD control flag bit shiftingAyushee Shah2021-01-071-5/+9
| | | | | | | | | | | | | | | | PD control flag returned to host doesn't have correct bit shifting, this causes enumeration failure of TBT devices using MBR cable. Hence, corrected PD control flag bit shifting BUG=b:176604391 BRANCH=none TEST=Test with MBR cable and enumeration is successful. make buildall -j Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Change-Id: Ica3c71b00e435c5ba417717baf22fc6dc26f9a92 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613904 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* BB retimer: Set UFP mode of BB retimerAyushee2021-01-072-0/+23
| | | | | | | | | | | | | | | | | | | | | This CL enables getting the enter mode information received from DFP and sets the following BB retimer bits accordingly. Bit 2: RE_TIMER_DRIVER Bit 18: CABLE_TYPE Bit 19: VPRO_DOCK_DETECTED Bit 20: TBT_ACTIVE_LINK_TRAINING Bit 22: ACTIVE/PASSIVE Bits 27-25: TBT Cable speed Bits 29-28: TBT_GEN_SUPPORT BUG=b:157163664 BRANCH=None TEST=Tested with volteer as UFP, able to set the retimer bits Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I661aa4630b42fbaa136ff3855c4f70e3dee61546 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2382634 Reviewed-by: Keith Short <keithshort@chromium.org>
* Move tcpic.h header into include/driverSimon Glass2021-01-073-3/+3
| | | | | | | | | | | | | | | | | | This header cannot currently be accessed by Zephyr since it is in a driver directory, not an include directory. This header has quite a bit of public stuff in it, so it seems reasonable to consider everything public. Move the header file and update all users. BUG=b:175434113 BRANCH=none TEST=make buildall -j30 build volteer on zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ibba37f47a06783fafb5095f853f2a68d92b6df87 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607745
* TCPMv2: Update BIST commentsAbe Levkoy2021-01-061-17/+19
| | | | | | | | | | | | | Correctly cite PD 3.0 spec. BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I26de0d34e99291d5320051ff47f0fc7c5d84b4b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2545666 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Remove PE_BIST_RX stateAbe Levkoy2021-01-061-41/+0
| | | | | | | | | | | | | | Nothing uses this, and anyway, the EC doesn't have the means to evaluate the results of a BIST Carrier Mode test that it initiates. BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I8aa0d97c81422689de4ca165cb2c0c34c324f6a2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2602719 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Compliance Unit Test - allow rx with data to have timeoutDenis Brockus2021-01-061-2/+6
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Iafbb0dd23a72ef32a1b3100fdfdeaf57c58b51f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613249 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* TCPMv2: Compliance Unit Test - add display for EXT messagesDenis Brockus2021-01-061-30/+56
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I6d1f1ea59c07fa36d5817b9d3a8615ac633964d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613247 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zephyr: add a fake shared memory implementation for posix-ecJack Rosenthal2021-01-061-1/+10
| | | | | | | | | | | | | | | | | | | | | | CL:2575207 was not tested against posix-ec and caused build issues. posix-ec does not have the _image_ram_end symbol available. This adds a new configuration for a fake 1MB shared memory option, and enables it for posix architecture by default. Note that if this CL (or an alternative fix) cannot be landed in a timely fashion, CL:2575207 and any CLs which depend on it should be reverted so we can enable the CQ again and stop stepping on our own toes. BUG=b:176828988 BRANCH=none TEST=run zephyr-chrome firmware_builder.py Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1d828f480c6a5da0b162a124c8a5a62ae8afb444 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2611985 Reviewed-by: Yuval Peress <peress@chromium.org>
* TCPMv2: Decrease Low Power Mode debounce delay to 10 msPatryk Duda2021-01-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch decreases PD_LPM_DEBOUNCE to 10 ms. With current 100 ms delay ANX7447 can't go to Low Power Mode due to silicon bug (b:77544959). When DRP mode is enabled ANX7447 triggers alert every 39.7 ms. Checking what caused an alert involves I2C transaction which changes timeout after which TCPC goes to Low Power Mode to get_time().val + PD_LPM_DEBOUNCE_US. As a result it is not possible to put TCPC to LPM which is necessary to work properly (b:149761477) Original value for PD_LPM_DEBOUNCE_US was 10 ms, introduced in CL:1119255. This value is still used in TCPMv1. For TCPMv2, PD_LPM_DEBOUNCE_US was changed to 100 ms in CL:2126078. It is unclear why this value was changed. Review discussion and bug b:149772936 don't mention why we needed to change that, so we change it back to 10 ms for consistency with TCPMv1. Issue was found when running EC ToT with TCPMv2 enabled on bobba board. BUG=b:161775827, b:77544959, b:149761477 BRANCH=none TEST=Flash EC ToT on octopus board with ANX7447 (eg. bobba). Make sure that DRP mode is enabled. Connect charger to port with ANX7447 chip. Make sure that EC can connect with charger. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ia08818378a1fca424d392b4699f9c4adc460bfb5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606235 Reviewed-by: Edward Hill <ecgh@chromium.org>
* TCPMv2: Add information about port when printing flag and event namesPatryk Duda2021-01-041-8/+8
| | | | | | | | | | | | | | | | This CL modifies print_bits() function to provide port number while printing flag names. Without this it is not clear to which port flag change is applied. BUG=b:161775827 BRANCH=none TEST=Define DEBUG_PRINT_FLAG_AND_EVENT_NAMES, check if messages contain information about port. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I2124bdafa32651b5b87ba78cf367d5c39000b708 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606234 Reviewed-by: Edward Hill <ecgh@chromium.org>
* keyboard_mkbp: report switches result until init'dEric Yilun Lin2020-12-311-2/+18
| | | | | | | | | | | | | | | | | When sysjump, the switch results will be re-evluated, and if the AP is up, this might report the intermediate switch states and misalign the switches states between EC and AP. This CL delay reporting the switches until all the switches are inited. BUG=b:173962511 TEST=AP boot to OS, sysjump, and system stays at S0 BRANCH=none Change-Id: Ifce7654ae8f6eb651cf1f7402c8e9e34f1b713f6 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607206 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* TCPMv2: Compliance Unit Test - TD.PD.SRC.E2Denis Brockus2020-12-301-0/+23
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I0b498d56dd189e3360fd1498acbfb5314c9870d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2602844 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org>
* TCPMv2: Unit Test - reflect TCPCI registers initial valuesDenis Brockus2020-12-291-1/+103
| | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I262e99c7442acca0118250764017f942239ed493 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604561 Tested-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org>
* tpcmv2: Fix compile error for Zephyr buildsKeith Short2020-12-281-1/+12
| | | | | | | | | | | | | | | Fix Type-C max source mutex for compatibility with Zephyr environment. BUG=none BRANCH=none TEST=make buildall TEST=build zephyr-chrome for volteer Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ibae899b8c937e0ed673ce9661584091440d40c1f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605327 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Simon Glass <sjg@chromium.org>
* TCPMv2: Unit Test - remove unused out parameterDenis Brockus2020-12-281-9/+4
| | | | | | | | | | | | | | | | | | In an earlier cleanup, the need for returning the original transmit type value became no longer needed. So remove it. BUG=none BRANCH=none TEST=make builadll Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I8fe30d7a9a87325bda6c4da6b4a5070b2d3ee6c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604560 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* zephyr: Support multi-step I2C transactionsSimon Glass2020-12-241-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the Zephyr implementation of i2c_xfer_unlocked() assumes this is the only call for the whole transaction. However in some cases the function is called several times, e.g. to write a register number, read a length, then read that number of bytes). Add support for this, so i2c_read_string() works, for example. BUG=b:176189170 TEST=build and boot on volteer, with Nuvoton's I2C fix See that LION is shown as such, and not LIO > battery Status: 0x0080 INIT Param flags:00000003 Temp: 0x0bb7 = %.1d K (%.1d C) V: 0x31f6 = 12790 mV V-desired: 0x3390 = 13200 mV I: 0x00ac = 172 mA(CHG) I-desired: 0x0a19 = 2585 mA Charging: Allowed Charge: 92 % Manuf: LGC Device: AC17A8M Chem: LION Serial: 0xb754 V-design: 0x2d1e = 11550 mV Mode: 0x6001 Abs charge:87 % Remaining: 4648 mAh Cap-full: 5040 mAh (4939 mAh with 98 % compensation) Display: 96.9 % Design: 5360 mAh Time-full: 2h:47 Empty: 0h:0 Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I1fe08c0c919a98fa66510048d4c05ae6e10072d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600933 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* make: Move libcryptoc rules to third_party/rules.mkCraig Hesling2020-12-241-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | This moves the libcryptoc hooks from common/build.mk to third_party/rules.mk. Recall that Makefile.rules actually contains all of the "rules"/recipes for making objects. It alone contains all of the build output beautification commands and control. Makefile.rules is included as the last step in the master Makefile. This brings no firmware change, as verified with compare_build.sh. BRANCH=none BUG=none TEST=./util/compare_build.sh -b fp TEST=./util/compare_build.sh -b fp -p # This fails due to the differing position of # -lcryptoc, -lfpsensor, -lfpalgorithm, and/or -lfpbep. Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I8d8493536a0e56ac6a5a1a32827b99ae97723727 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092163 Reviewed-by: Yicheng Li <yichengli@chromium.org>
* TCPMv2: Update source-out configsDiana Z2020-12-244-22/+25
| | | | | | | | | | | | | | | | | | | | Now that the DPM will be handling source-out decisions for TCPMv2, remove references to its old configuration options from TCPMv2 boards in order to avoid any confusion as to what code is running now. Also remove the charge manager notifications of sink attach/detach since the policy is being centralized into the DPM. Note that the previous configuration options only ever allocated one 3.0 A port, and so the default number of 3.0 A ports has been set to 1. BRANCH=None BUG=b:168862110,b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie452e3da32b04226503539daa67b6b9f4a58aa58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597431 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv2: Update current limits in appropriate taskDiana Z2020-12-242-4/+13
| | | | | | | | | | | | | | | | | Since setting the current limit on a port often involves communicating with a port's PPC or charger, run this from the appropriate port task rather than allowing another port to run it. This interface can also be used later to increase or decrease the source Rp for non-PD partners. BRANCH=None BUG=b:168862110,b:141690755 TEST=on drawcia, plug in two hubs requiring 3.0 A and confirm that the first receives 3.0 A, and on its unplug the second is offered 3.0 A Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie8423f612d199f4389955e00a82e9ca588f2d836 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597430 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv2: DPM sourcing policy - 3.0 A PD sinksDiana Z2020-12-244-2/+154
| | | | | | | | | | | | | | | | | | | | | | | | | Move the sourcing policy from the charge_manager to the DPM for TCPMv2. The first step of this policy will be to allocate 3.0 A only if a peripheral reports requiring more than 1.5 A in their Sink Capabilities vSafe5V operational current. For this commit, leave in some charge_manager APIs for linking which will be re-named or removed later. BRANCH=None BUG=b:141690755,b:168862110 TEST=on drawcia verify: - non-PD sink only offered 1.5 A Rp - PD sink requiring 1.5 A or less Rp isn't offered 3.0 A - PD sink requiring 3.0 A is offered a new 3.0 A Source Capability after sink capability probing. Port continues to receive 3.0 A over both hard and soft resets. - When 2 3.0 A sinks are plugged in, only the first is offered 3.0 A. After the first is unplugged, the second receives a 3.0 A source capability message Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Iec48312df1125086db2919c1503c7ba31fe12bcc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597429 Reviewed-by: Keith Short <keithshort@chromium.org>
* zephyr: usb: Init mutexes in pd_set_vbus_discharge()Simon Glass2020-12-231-1/+8
| | | | | | | | | | | | | | Zephyr needs these to be inited before use. Add the code for this. It is harmless for ECOS but increases code size, so put it behind an #ifdef BUG=b:175434113 BRANCH=none TEST=build zephyr for volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I874c02e143b9d6987ab52036652897f384540def Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600226 Reviewed-by: Keith Short <keithshort@chromium.org>
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