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* zephyr: Update banner to match Chromium OSKeith Short2021-04-232-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the boot banner to match Chromium OS. This also modifies the version output to include "_zephyr" after the board name to clearly identify the image type. Boot banner: Booting Zephyr OS build zephyr-v2.5.0-31-g6fcd6373e58a --- UART initialized after reboot --- [Image: RO, volteer_zephyr_v2.0.8350-190d6f 2021-04-08 11:15:09 keithshort@mtbaldy] [Reset cause: reset-pin] uart:~$ version Chip: Nuvoton NPCX796FC 02 Board: 1 RO: volteer_zephyr_v2.0.8350-190d6f RW: volteer_zephyr_v2.0.8350-190d6f Build: volteer_zephyr_v2.0.8350-190d6f 2021-04-08 11:15:09 keithshort@mtbaldy BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia136c4e025aba95217f1d8c51de39255fef54f7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822208 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-233-3/+3
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* LED On/Off: Add state for off with insufficient powerDiana Z2021-04-231-1/+13
| | | | | | | | | | | | | | | | | Add a common state to communicate that we're off due to insufficient power. If not defined, allow this state to fall back to OFF since many systems with batteries will be using the battery LED to communicate this information. BRANCH=None BUG=b:185508707 TEST=on boten, confirm no regressions with fake low battery in S5 Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ie8b37785a43fdfdd6619fe72c8bd7e2be6776e43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832694 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* LED On/Off: Allow compiling without CONFIG_CHARGERDiana Z2021-04-221-0/+8
| | | | | | | | | | | | | | | | The header for charge_get_percent() will only define this function if CONFIG_CHARGER is present. Make a declaration for complilation to use, and then allow most of the led_get_state() function to be optimized out with IS_ENABLED(). BRANCH=None BUG=b:185508707 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I3d94f290ac5b9ec82b46b9c0a6fc668b2e8dd91c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832693 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* LED On/Off: Make battery LED optionalDiana Z2021-04-221-0/+12
| | | | | | | | | | | | | | | Currently, all boards using the LED On/Off module have battery LEDs. However, if we'd like to expand support to Chromeboxes then the battery LED must become optional. BRANCH=None BUG=b:185508707 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ieae098829ebe6c8b103f23d5abdbf70e7bcbdf2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832692 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* LED On/Off: Remove power LED configDiana Z2021-04-221-6/+10
| | | | | | | | | | | | | | | | | | | | | | Move the LED on/off module towards using a more flexible LED support approach. Define a weak power LED table and setter for boards to override when needed. Note that during run-time these functions will not get called since led_auto_control_is_enabled() will return false for nonexistent LEDs. This consumes an average of 165 additional bytes of flash space on boards which do not use a power LED. BRANCH=None BUG=b:185508707 TEST=make -j buildall, load on guybrush (battery LED only) and confirm no errors are seen. Load on Boten (both LEDs) and confirm behavior appears normal Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Iaa1e22a7f5d8be39eb8792ee13d358087d7f7482 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832691 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: PE: Clear PRS request following acceptfactory-13929.B-mainScott Collyer2021-04-211-0/+12
| | | | | | | | | | | | | | | | | | | | | This CL adds logic to clear any pending DPM_REQUEST_PR_SWAP once we accept a PRS request from the port partner. This prevents a possible back to back swap if we want to PRS, but the port partner sends the request before PRS swap request is generated. BUG=b:182441965 BRANCH=quiche TEST=tested quiche with kohaku where quiche attaches in sink role. This case causes quiche to want to power role swap and causes the port partner to request a power role swap. Verified that only 1 power role swap occurs. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I05ee27897d5900e71257d268acd3bd37c8abb787 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2799450 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* battery: Correct battery_get_disconnect_state() returnSimon Glass2021-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | This cannot return a value from a different enum. Doing so produces an error with clang: battery_fuel_gauge.c:228:10: warning: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum battery_disconnect_state' [-Wenum-conversion] Fix it by returning the existing error value. BUG=none BRANCH=none TEST=CQ Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I1f3826ef26b1255934ea96cd1541f60436546b57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2842204 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPC: Cleanup: Get Sink & SRC state from PD or PPCVijay Hiremath2021-04-211-0/+2
| | | | | | | | | | | | | | Added option to get the Sinking or Sourcing state from either PD or PPC. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ibb21ef69b5825ea5722ceacd5d7ef6f535aad17c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2838127 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Cleanup: Enable PPC from PD or Power MUXVijay Hiremath2021-04-201-1/+1
| | | | | | | | | | | | | | | Some PD chips have integrated SRC FET and control the SRC/SINK FET from GPIOs hence cleaned up the code to enable Power Path Control from either from PD or from Power MUX. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I77f96b681fd2e5fca35bce425e4bd5ec87d5ccfd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2828980 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* system: Wait 1s for EC to quiesce before hibernateAseda Aboagye2021-04-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The EC can enter hibernate via a keyboard shortcut alt+vol_up+H when in S0. However, the EC will never actually hibernate from S0; instead, it waits until the system is in S5/Pseudo G3 for 1hr (default setting). If the system is in S0 when hibernate is requested, it performs an unclean shutdown and then enters hibernate immediately. However, this can allow spurious interrupts to wake up the EC again. This commit simply adds a 1s delay after the unordely shutdown and before entering hibernate. BUG=b:185302895,b:185206379 BRANCH=dedede TEST=Build and flash DUT, boot to S0, press alt+vol_up+H, verify DUT turns off and stays off. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I98e094a64ae716811e44fe1858ad981403da7b39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829116 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* zephyr: i2c: Fix use of I2C_PORT_VIRTUAL_BATTERYYuval Peress2021-04-151-1/+2
| | | | | | | | | | | | | | | | | | In Zephyr builds, the I2C_PORT_* values are enums generated from devicetree (instead of #define values). This means that in Zephyr, it should suffice to just check VIRTUAL_BATTERY_ADDR_FLAGS. BRANCH=none BUG=b:185392974 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ifedaf45ec8bcfa33bb75c8381604ad565ca08d6a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826919 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: use interrupt based RX bufferingYuval Peress2021-04-151-13/+6
| | | | | | | | | | | | | | | | | | | | Poll-based RX was technically incorrect since Zephyr was setting up the UART to FIFO mode (instead of byte mode). This change replaces polling the RX UART with interrupt based callbacks. When calling uart_shell_stop(), the ISR will be replaced and will instead queue items to a ring buffer which can be read from uart_getc() (it can also be cleared via the uart_clear_input() function). BRANCH=none BUG=b:181352041 TEST=Build volteer, run, see expected 0xec07 from the GSC. Cq-Depend: chromium:2730870, chromium:2730869 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I5d2b61e914b56f678a259b373969522da87e8df3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2728824 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* TCPMv2: Generate Hard Reset eventAbe Levkoy2021-04-152-0/+7
| | | | | | | | | | | | | | | Inform the AP when the PRL completes a Hard Reset. BUG=b:183946291 TEST=Observe event during transition-to-default states TEST=With kernel patch, observe mode reentry after Hard Reset BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I4af576bd3a8fb57d820bd91d74817040214eaa5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2799924 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPMv2: Soft reset on Vconn_Swap sequence interruptionDiana Z2021-04-141-0/+12
| | | | | | | | | | | | | | | When a non-interruptible AMS is interrupted, the unexpected message should yield a soft reset on the SOP* of the incoming message. Before sending PS_RDY, check for this condition and soft reset if necessary. BRANCH=None BUG=b:182221344 TEST=on sasuke, confirm charger can successfully connect reliably Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I6612cb5d5d74cf99155cac99894a7746462a7b9e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823633 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Remove dual-role capability check from Attached.SNK entryDiana Z2021-04-132-19/+13
| | | | | | | | | | | | | | | | | | Currently, we'll check the partner dual role flag when entering Attached.SNK not from a power role swap. However, we have no way to know the partner dual role capabilities at that point. Set up connections as dedicated, and then allow the PE to update accordingly when source capabilities are received. BRANCH=None BUG=None TEST=on guybrush, confirm we automatically charge from a PD charger, non-PD charger, and do not automatically charge from another chromebook Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ia7cdf4259c35af32a303113befe0bd2fb26cf6d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2821365 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Update source PDO flags alwaysDiana Z2021-04-131-8/+12
| | | | | | | | | | | | | | | | | | | Always ensure we update our source PDO flags when storing partner source cap replies during PE_SNK_Evaluate_Capability. However, only propose a power role swap the first time we're storing source capabilities to prevent infinite PR swap loops between Chromebooks. BRANCH=volteer BUG=b:184971310 TEST=ensure connection with a DRP partner results in correct setting of dual role flags (dual-role for anything we don't want to automatically charge from, dedicated for anything we do want to automatically charge from). Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ida139af43fb384096b14e686cf5bd6bbfdf16aa9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2821602 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* usb_prl_sm: Fix spellingAbe Levkoy2021-04-131-1/+1
| | | | | | | | | | | | | wad -> was BUG=none TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I75647696c7150b03d681e190d803fd5de28523d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2812140 Reviewed-by: Diana Z <dzigterman@chromium.org>
* TCPMv2: Don't retry after failed alt mode entryAbe Levkoy2021-04-132-5/+12
| | | | | | | | | | | | | | | | If entering DP or TBT alt mode fails, leave the state machine in an inactive state. Allow the DPM to see that the mode entry process is done and stop trying to send more VDMs. BUG=b:184197145,b:179443762 TEST=make buildall TEST=Pass TDA.2.1.2.1 on Voxel with AP-driven mode entry TEST=Enter, exit, and reenter DP and TBT mode with host commands BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: If72b3410f9aa174c48c65a8ca908d79e2090fa62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2798525
* TCPMv2: Set SOP before requesting chunkAbe Levkoy2021-04-131-0/+1
| | | | | | | | | | | | | | | | When requesting the next chunk in the RCH state machine, set the SOP type for the request to the type of the just-received chunk response. Do not just use the SOP type of the last transmitted message. BUG=b:179443762 TEST=Pass TD.PD.SRC3.E32 with SOP' traffic immediately before chunk 0 BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ifb520bb7ee439ea895b11938395a943d5ca32edf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2812138 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ec: Filter non-FIXED PDOs in servo_v4{p1}Jeremy Bettis2021-04-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | Add a new config CONFIG_USB_PD_ONLY_FIXED_PDOS. If that config is enabled, ignore non-FIXED PDOs in both the console command `ada_srccaps` and also when selecting the preferred PDO for a voltage. Enable CONFIG_USB_PD_ONLY_FIXED_PDOS for servo_v4 and servo_v4p1, since they don't expose non-fixed PDO in their srccaps. Without this change, there is a risk that the "best" PDO for a given voltage will be non-FIXED and then that voltage just won't be supported at all. BRANCH=none BUG=b:178484932 TEST=added Change-Id: I0d1187ca372120c7fe21d627e1b82b59f6334add Signed-off-by: Jeremy Bettis <jbettis@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2809353 Tested-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* ec: Parse battery and augmented PDOs correctly.Jeremy Bettis2021-04-121-16/+24
| | | | | | | | | | | | | | | | Fixes pd_extract_pdo_power() to output the correct voltage and current for non-fixed PDOs. Add unit test. BRANCH=none BUG=b:178484932 TEST=added Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I6de55be3c753e01ef26424896c6fd41b8df8f94b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2805226 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* cbi: API for EC to update fw_config tagScott Collyer2021-04-101-0/+26
| | | | | | | | | | | | | | | | | | This CL adds an API to the CBI to allow the EC to update the FW_CONFIG tag field. This API is dependent on not having a the chipset task defined. BUG=b:164157329 BRANCH=quiche TEST=Verified on quiche that long button presses toggle bit 0 of the FW_CONFIG field. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I3a4360b32feac4a04fe53b518c122940f4b340f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2776227 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Sam Hurst <shurst@google.com> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* TCPMV2: Default PD Policy ManagementSam Hurst2021-04-093-18/+62
| | | | | | | | | | | | | | | | | | | A simple implementation to manage PD Policies on honeybun devices. This is meant as an interim solution until a more robust solution is implemented BUG=b:183026242 BRANCH=none TEST=make runtests Tested on Voxel by plugging in a dock Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: Ib8b38754e21b8497fe28855a7f80d2962a4ae7f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774128 Reviewed-by: Yuval Peress <peress@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* system: Remember AP watchdog resetYu-Ping Wu2021-04-091-0/+4
| | | | | | | | | | | | | | | | | | | | On MT8183, when EC detects a watchdog reset, EC needs to reboot itself in preparation for the next boot. This means that AP loses the reset cause (as AP system reset is toggled), and, therefore, we need to save the reset reason in the EC. This has been done in CL:1295890 for chip stm32. For the new MT8183 model 'cozmo', we need to do the same for chip it83xx. BUG=b:184225435 TEST=firmware_EventLog passed on Cozmo TEST=FW_NAME=cozmo emerge-jacuzzi chromeos-ec BRANCH=none Change-Id: I08d165b5dbd8e1d92fad66ef3873fc406ab6a0e0 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2814079 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* i2c_controller: zephyr: explicitly strip flags from addr_flagsFabio Baltieri2021-04-081-1/+6
| | | | | | | | | | | | | | | | | | | | | | The ECOS I2C APIs use addr_flag to pass the I2C address together with few flags. These are currently passed to the Zephyr API stripping only the PEC bit, and no other flags are used in Zephyr platforms at the moment, but if any flag would be present it would confuse the Zephyr I2C stack. This changes the Zephyr part of the driver to explicitly strip any possible flag from add_flag, and also add a warning to signal that we are discarding some information. BUG=none BRANCH=none TEST=build and flash on volteer TEST=cbi shell command Change-Id: I497fe33c52c78d783c86711928067a4aa0a321d7 Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2814624 Reviewed-by: Yuval Peress <peress@chromium.org>
* pd commands: support PD console command srccapsEric Yilun Lin2021-04-083-1/+26
| | | | | | | | | | | | | | | | | | | | | | | This allows servo querying DUT's srccap easier. BUG=b:140256624 TEST=on servo_v4 (TCPMv1) and Asurada (TCPMv2) tested that 1. plug adapter `pd 0 srccaps` show the PDOs 2. unplug adapter `pd 0 srccaps` show nothing sample output: > pd 1 srccaps 0: 5000mV/3000mA 1: 9000mV/2000mA 2: 12000mV/1500mA 3: 3300mV-5900mV/3000mA 4: 3300mV-11000mV/2000mA BRANCH=servo Change-Id: Iadf9f9d91359c96b188509a28b3dc42a7e7b2223 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2804008 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* usb_common: support parse Augmented PDOEric Yilun Lin2021-04-085-89/+103
| | | | | | | | | | | | | | | | | | Change the function signature to void pd_extract_pdo_power(uint32_t pdo, uint32_t *ma, uint32_t *max_mv, uint32_t *min_mv); Replace the original caller with an extra unused parameter, no functional changes. BUG=none TEST=`pd 0 srccaps` prints the correct PDO info BRANCH=asurada Change-Id: I9b508e1a13737fe3ed61e6086416cff0c8ffb9a9 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2810660 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* TCPMv1: clear SourceCap in disconnected stateEric Yilun Lin2021-04-082-4/+2
| | | | | | | | | | | | | Clear the SourceCaps to prevent misleading info. BUG=none TEST=`pd 0 srccaps` no output if adapter unplugged BRANCH=asurada Change-Id: Ibfefb3cc2e91c548fdf6579603dd5be20d68c08e Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2810659 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* hooks: Avoid torn accesses in the hook taskEvan Green2021-04-071-16/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hook task runs at the lowest priority, and both reads from and writes to a data structure that can be changed out from under it at any time. This is unsafe, and can cause missed hook events and double hook events. For example, the hook task reads __deferred_until[i], a 64-bit value, in two 32-bit reads. If the hook task is interrupted during this read, and the interruption changes the value, the hook task may read a totally bogus value. This is rare, as overflows across this 32-bit boundary don't happen often, but leads to unpredicable behavior when they do. The writes the hook task does are also problematic, since for instance the hook may have been rescheduled just after the slow old hook task entered its if clause deciding to run the hook, but before it clobbered __deferred_until[i] back to zero. Things get worse if the hook routine pointer ever changes, though I don't think we're currently doing that anywhere today. Instead, disable interrupts while the hook data structure is being manipulated as a makeshift lock around it. Remove the defer_new_call variable as well, since the new deadline is now computed atomically (and without the possibility of torn reads). BUG=b:178660461, b:179062230 BRANCH=None TEST=Run suspend 2500 on Boten, observe no spurious s0ix timeouts. Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Iff0d596014e1e79dd9691d363fdc8e54bfe2dff0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2805222 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* TCPMv2: Detach from debug devices in Unattached entryDiana Z2021-04-071-7/+10
| | | | | | | | | | | | | | | | | | | | | Call debug detach routine on the TCPC before setting our terminations in Unattached.SNK/SRC. This will cover more code paths than attempting to ensure we call the debug detach from every possible chipset transition, sysjump, etc. Note we should still debug detach in Attached exits when PR swapping. BRANCH=None BUG=b:183619502 TEST=on Galith, confirm that: - firmware_UserRequestRecovery passes reliably - board is able to boot with no battery and a charger attached in either port Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I6cef8ce57a569b0e15e1e10b77c830b1c7a55d75 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2792690 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "fpsensor: Support building firmware that works for both sensors"Tom Hughes2021-04-073-115/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ac08c9d1dbc9f587df3ee6b15d58c0203f7e356e. Reason for revert: Breaks public build Original change's description: > fpsensor: Support building firmware that works for both sensors > > This is a refactoring to allow building FPMCU firmware that works for > one FPC sensor and one ELAN sensor. > > 1. When both drivers implement our common functions, e.g. fp_sensor_init(), > rename them to fp_sensor_init_fpc() and fp_sensor_init_elan(). > 2. There are a few functions implemented not in FPC driver but in FPC > private library, e.g. fp_sensor_finger_status(). I kept this as-is for > FPC but renamed the one in ELAN driver to fp_sensor_finger_status_elan() > 3. If building for ELAN, need to hardcode elan=1 in hatch_fp/board.c > because the sensor type GPIO always says FPC. > > BRANCH=none > BUG=b:175158241 > TEST=make run-fpsensor; make run-fpsensor_status; > make run-fpsensor_crypto > TEST=make -j BOARD=dartmonkey > TEST=add CONFIG_FP_SENSOR_ELAN515 to board/hatch_fp/board.h; > make -j BOARD=bloonchipper > Firmware binary fully works on Dragonair (FPC) and Voema (ELAN) > TEST=run device tests with http://crrev/c/2750547 and > http://crrev/i/3654297 on Dragonclaw, all pass > > Change-Id: I789090dbdfe35ac6aefd6a629fa4c7bde89dc437 > Signed-off-by: Yicheng Li <yichengli@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727971 > Reviewed-by: Tom Hughes <tomhughes@chromium.org> > Commit-Queue: Tom Hughes <tomhughes@chromium.org> Bug: b:175158241, b:184616069 Change-Id: I2a02a6eefc316e7e13aa188f1ae16672dce2babd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2809521 Auto-Submit: Tom Hughes <tomhughes@chromium.org> Tested-by: Tom Hughes <tomhughes@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* PD_INT: Add ability to process non-TCPC alerts in PD_INTDiana Z2021-04-061-1/+9
| | | | | | | | | | | | | | | | Some boards may have other chips sharing the TCPC interrupt line, in which case their alerts may need to be handled at the same priority as the TCPC itself. Otherwise, it becomes difficult to respond quickly to TCPC interrupts. BRANCH=None BUG=b:182534117,b:183679237 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I905f20eeb0dd89c8516de31005d402a890906595 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2803460 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* PCHG: Support firmware updateDaisuke Nojiri2021-04-051-3/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds EC_CMD_PCHG_UPDATE, which allows the host to update firmware of ctn730 via I2C. An updater (e.g. ectool) is expected to issue EC_PCHG_UPDATE_CMD_OPEN, multiple EC_PCHG_UPDATE_CMD_WRITEs, then EC_PCHG_UPDATE_CLOSE. Each sub-command completion is notified to the host via EC_MKBP_EVENT_PCHG. An updater is supposed to wait for the previous sub-command to complete before proceeding to the next. Example: localhost ~ # ectool pchg 0 State: DOWNLOAD (6) FW Version: 0x104 localhost ~ # ectool pchg 0 update 0x207000 0x105 /path/to/image.bin Update file /path/to/image.bin (85632 bytes) is opened. Writing firmware (port=0 ver=0x105 addr=0x207000 bsize=128): ********************************************************************** FW update session closed (CRC32=0x7bd5c66f). localhost ~ # ectool pchg 0 reset Reset port 0 complete localhost ~ # ectool pchg 0 State: ENABLED (2) FW Version: 0x105 BUG=b:182600604, b:173235954 BRANCH=trogdor TEST=ectool pchg 0 update 0x201200 0x105 /tmp/user_ee_X0.1_V1.5.bin TEST=ectool pchg 0 reset Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I9c62f1714dd69428ab5870c443cb4eb77881a6c6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2757099
* fpsensor: Support building firmware that works for both sensorsYicheng Li2021-04-023-64/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a refactoring to allow building FPMCU firmware that works for one FPC sensor and one ELAN sensor. 1. When both drivers implement our common functions, e.g. fp_sensor_init(), rename them to fp_sensor_init_fpc() and fp_sensor_init_elan(). 2. There are a few functions implemented not in FPC driver but in FPC private library, e.g. fp_sensor_finger_status(). I kept this as-is for FPC but renamed the one in ELAN driver to fp_sensor_finger_status_elan() 3. If building for ELAN, need to hardcode elan=1 in hatch_fp/board.c because the sensor type GPIO always says FPC. BRANCH=none BUG=b:175158241 TEST=make run-fpsensor; make run-fpsensor_status; make run-fpsensor_crypto TEST=make -j BOARD=dartmonkey TEST=add CONFIG_FP_SENSOR_ELAN515 to board/hatch_fp/board.h; make -j BOARD=bloonchipper Firmware binary fully works on Dragonair (FPC) and Voema (ELAN) TEST=run device tests with http://crrev/c/2750547 and http://crrev/i/3654297 on Dragonclaw, all pass Change-Id: I789090dbdfe35ac6aefd6a629fa4c7bde89dc437 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727971 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* TCPMv2: Enter safe mode before entering TBT/USB4 mode for the cable.Madhusudanarao Amara2021-03-312-9/+15
| | | | | | | | | | | | | | | | | Before sending Enter Mode/Enter USB to the cable plug (SOP' and SOP'') the usb mux and retimer should be configured to safe mode BUG=b:183781477 BRANCH=None TEST=TBT/USB4 device enumerates fine on coldboot, warmboot and hotplug with MBR and passive cables. Change-Id: Ia8fe95d9183f7febdb118bca51ea9a137870832c Signed-off-by: Madhusudanarao Amara <madhusudanarao.amara@intel.corp-partner.google.com> Signed-off-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2786883 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* TCPMv2: PRL: Enahnce support for the tx message discard pathScott Collyer2021-03-311-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL modifies the tx message discard path in the PRL. The states that should have triggered tx message discard events, would only act on messages pending from PE, but not passed yet to the phy. This behavior was required to account for the serial nature of the different PRL state machines and inherent delay in sending/receiving messages to/from off chip TCPCs via the I2C bus. This CL adds a new WAIT value to the xmit_status enum so that a message being sent to the phy but not reponse yet can be known. In addition, xmit_status == DISCARDED is no longer treated automatically as a protocol error. BUG=b:181179550,b:173028144 BRANCH=None TEST=Running VDMU.E16 compliance test. Validated that the SVDM command sequence is properly interrupted in most all cases. This test only fails if collision events are present which is a happening on honybuns for 2 reasons: 1) GRL test waits too long to interrupt the VDM command (~1 msec) 2) honeybuns ucpd is faster since it doesn't have i2c delays. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2bec09b96d7f6ea6122fcb369246717950987ca8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2752251 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* TCPMv2: UFP-D: Make sure OPOS table is cleared in discoveryScott Collyer2021-03-311-0/+3
| | | | | | | | | | | | | | | | | | This CL adds a call to reset the OPOS value in the alt_dp_mode_opos table at the beginning of discovery. This required to pass the VDMU.E5 PD2.0 deterministic compliance test. BUG=b:175660576,b:180465870 BRANCH=None TEST=verifed that VDMU.E5 PD2.0 deterministic compliance test is passing when it's run in the full suite. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I330f35aca88a54c436c84b74618a586e4daaf07b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2777691 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* chgstv2: Check string validityreno.wang2021-03-301-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Battery gauge follow SMBus SPEC and SMBus SPEC define cumulative clock low extend time for both controller (master) and peripheral (slave). However, I2C doesn't. Regarding this issue, we observe EC sometimes pull I2C CLK low a while after EC start running. Actually, we are not sure the reason until now. If EC pull I2C CLK low too long, it may cause battery fw timeout because its cumulative clock extend time is over 25ms. When it happened, battery will release both its CLK and DATA and reset itself. So, EC will get 0xFF when EC keep reading data from battery. Battery static information will be unreliable and need to be updated. This change is improvement that EC should retry if battery string is unreliable. BUG=b:181639264 BRANCH=dedede TEST=make -j BOARD=boten, verify if EC retry to read battery static info. Signed-off-by: reno.wang <reno.wang@lcfc.corp-partner.google.com> Change-Id: I488fde8aae05414026e6993d7606fc02499fdf3b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2791084 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* fpsensor: Enable -WvlaTom Hughes2021-03-301-4/+17
| | | | | | | | | | | | | | | | Ideally this should be enabled for all the EC code, but that requires making more changes. For now enable it for the fingerprint sensor code to make sure we don't accidentally introduce variable length arrays. BRANCH=none BUG=b:172020413 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I80fe4acade2c84886142ef795e54be004d1663be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2792699 Commit-Queue: Yicheng Li <yichengli@chromium.org> Reviewed-by: Yicheng Li <yichengli@chromium.org>
* common: body_detection: re-enable body_detection in S0Ching-Kang Yen2021-03-291-3/+16
| | | | | | | | | | | | | | | | | | | | The powerd will enable the body_detection once after rebooting, but not after resuming. Because we disable the body_detection in S3, we should re-enable the body_detection in S0. BRANCH=trogdor BUG=b:123434029 TEST=powerd_dbus_suspend; ectool motionsense list_activities; see if body_detection is enabled. TEST=make buildall; Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Change-Id: Idb06888d9b4ec0eca994201f7fbd646f37c2c371 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2752573 Commit-Queue: Ching-Kang Yen <chingkang@chromium.org> Tested-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: body_detection: using bypass_fifo flagChing-Kang Yen2021-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Originally, the body_detection will set MOTIONSENSE_SENSOR_FLAG_WAKEUP when changing state, which disable suspension of device. Thus, there was a commit [crrev.com/c/2631887] that just simply unset the MOTIONSENSE_SENSOR_FLAG_WAKEUP, which make body_detection not work properly. So, this commit will resolve the problem by setting the BYPASS_FIFO flag. BRANCH=None BUG=b:123434029 BUG=b:176399952 TEST=powerd_dbus_suspend # See if the device wake up after suspend TEST=make buildall; Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Change-Id: Ia911f4b27c15891d4e04eedbd524d019e0f334f0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2780862 Commit-Queue: Ching-Kang Yen <chingkang@chromium.org> Tested-by: Ching-Kang Yen <chingkang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* Revert "common: body_detection: prevent AP from unexpected waking up"Ching-Kang Yen2021-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bca7737997eecb517dbbc94fd95d034f0f5cde56. Reason for revert: This commit is just a workaround, and causes another problem. The actual fix will be in the following commit. Original change's description: > common: body_detection: prevent AP from unexpected waking up > > Current body_detection will make AP resume after enter S3. Cause the AP > wake up in a short time after suspend. > This CL will prevent this from happening. > > BRANCH=None > BUG=b:176399952 > TEST=powerd_dbus_suspend # See if the device wake up after suspend > > Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> > Change-Id: Id208800a66e4e2d433a555210ece50af85c908ec > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2631887 > Reviewed-by: Wai-Hong Tam <waihong@google.com> BRANCH=None BUG=b:176399952 TEST=None Cq-Depend: chromium:2780862 Signed-off-by: Ching-Kang Yen <chingkang@chromium.org> Change-Id: I904ff718ff41336dca3c85c99a424a69483740f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721328 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: motion_sense: Prevent on/off body from waking up deviceGwendal Grignou2021-03-292-7/+25
| | | | | | | | | | | | | | | | | | | | Introduce a new flag: BYPASS_FIFO to raise an interrupt to the AP when an event is sent. It is not as strong as WAKEUP, as it does not wake up the AP. BYPASS_FIFO must be set when WAKEUP is set. It is applied to sync sensor as well as gesture/activity sensor. BUG=b:123434029 BRANCH=trogdor TEST=Compile Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Id5aba71e6d11ef31f7fa2c67ba2e07178d088b1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2780834 Reviewed-by: Ching-Kang Yen <chingkang@chromium.org> Tested-by: Ching-Kang Yen <chingkang@chromium.org> Commit-Queue: Ching-Kang Yen <chingkang@chromium.org>
* common/battery: Provide function to lower input voltagePatryk Duda2021-03-291-0/+82
| | | | | | | | | | | | | | This patch introduces generic version of function that sets voltage limit when chipset is off and battery is fully charged. BUG=b:182546058 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ib7606c8d1ab3fe1dc650a3abcef9ebc207335ab5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2773218 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TCPMv2: Call debug detach on toggle changesDiana Z2021-03-261-0/+7
| | | | | | | | | | | | | | | | | | | When our power state changes partway through a debug connection starting, we may end up transitioning straight from a source to a sink role without calling the debug detach routine. Ensure that dual role changes call the debug detach when forcing state changes between source and sink, where we were not previously Attached. BRANCH=None BUG=b:183619502 TEST=on galith, firmware_UserRequestRecovery can pass Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id2214487be9be4209dbd9bece94492bc4ac9c05e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2786068 Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Henry Sun <henrysun@google.com> Tested-by: Henry Sun <henrysun@google.com>
* switch: cleanup lid_is_open logicJack Rosenthal2021-03-251-6/+1
| | | | | | | | | | | | | | | Cleanup an ifdef here for systems without a lid switch, so that "lid looks open" is just a consequence of !IS_ENABLED(CONFIG_LID_SWITCH). BUG=none BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1bbc145a0ffb49a127cb5a4e3986ed0955381353 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2787588 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* PCHG: Notify host of new SOC and all other events in S0Daisuke Nojiri2021-03-251-4/+4
| | | | | | | | | | | | | | Currently, the EC notifies the host of a new SOC and errors. This change makes the EC additionally notify the host of all other events. BUG=b:182973695, b:173235954 BRANCH=trogdor TEST=Stylus battery indicator changes timely when stylus is attached. TEST=Suspend is entered quickly with a stylus attached. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Id74d809f9838fa36b25d710ed64b6f1ba236cad8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2785512
* ctn730: Print firmware versionDaisuke Nojiri2021-03-241-5/+7
| | | | | | | | | | | | | | | | | | This patch makes ctn730 driver print the firmware version. EC_CMD_PCHG is updated to version 1 and returns firmware version of a charger chip. Version 0 of EC_CMD_PCHG is deprecated. BUG=b:182600604, b:173235954, b:183151376 BRANCH=Trogdor TEST=Verify firmware version is printed on EC console. TEST=ectool pchg 0 (for version 1) TEST=cat /sys/class/power_supply/PCHG0/* (for version 0) "ERR kernel: [ 33.394847] cros-ec-pchg cros-ec-pchg.13.auto: Unable to get port.0 status (err:-524)" Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ib7bb9a7225fe914bc6c8d600d0f4766dbf75ace8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2757098
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