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* glados: limit max input current to 1.5A to avoid i2c errorsstabilize-7155.BAlec Berg2015-06-091-0/+4
| | | | | | | | | | | | | | | | | | | | | Add workaround to limit the max input current to 1.5A due to i2c communication problems at higher currents. Note that this max should be removed when possible. This introduces a new CONFIG option to define the maximum input current limit for a board, as opposed to the already existing default input current limit. BUG=none BRANCH=none TEST=load on glados, charge with zinger, make sure input current is set to 1.5A and no recurring i2c errors talking to battery and charger. Change-Id: Ib7070772e1bf5475e98a2dc946ae75bf08047b70 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/276169 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* pd: use pdcmd task to handle tcpc interruptAlec Berg2015-06-052-8/+18
| | | | | | | | | | | | | | | | | | | | Use the PDCMD task to handle PD MCU interrupts, and use it to trigger the tcpc_alert(). Note this fixes bug on Glados and Oak that could cause watchdog reset because tcpc_alert() which uses i2c to talk to tcpc was called from hooks task and can delay tickling watchdog. BUG=chrome-os-partner:40920 BRANCH=none TEST=load on glados and plug zinger into both ports many times. make sure we get a stable contract and no watchdog reset. Change-Id: I37625fae2ca0057d2ee8fa1eea6974f2d26d1b91 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275296 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* i2c/mec1322: Lock all I2C port before sysjump.Kevin K Wong2015-06-052-0/+14
| | | | | | | | | | | | | | | | | | | | | | | sysjump could happen anytime during an I2C transaction. After sysjump and EC reset, I2C pin will be programmed back as GPIO instead of alternate function, which will cause the I2C transacation to failed. MEC1322 I2C also depends on interrupt to handle the I2C transaction, however, sysjump will disable interrupt, which will cause watchdog timeout/reset since interupt for I2C transaction are disabled. BUG=none TEST=After "sysjump <RO/RW>", "i2cscan" is functional and no watchdog reset. BRANCH=none Change-Id: I181084822f0769173c724e48afb59d7099fa1566 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/273710 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* i2c: Retry i2c operation if fails on nack'd(EC_ERROR_BUSY).li feng2015-06-041-2/+10
| | | | | | | | | | | | | | | Retry count is defined by CONFIG_I2C_NACK_RETRY_COUNT. BUG=chrome-os-partner:37494 TEST=Tested on Cyan, observed retry happens on nack'd i2c. BRANCH=None Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I73ed15a52335de6c5a5b647660bfe431a8238716 Reviewed-on: https://chromium-review.googlesource.com/274689 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* Cr50: Add usb_blob handler frameworkBill Richardson2015-06-042-0/+114
| | | | | | | | | | | | | | | | | | | | | This adds a new task and endpoints to handle large opaque (to the USB) chunks of data. The expected use case is that the USB endpoint accepts bytes from the host and passes them blindly to the blob-handling task. At some point, the blob-handling task may wish to send bytes back to the host. What those bytes are and what they mean is determined at higher levels of abstraction. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall This CL doesn't enable the blob-handler; it just makes it available. The next CL will enable and test it. Change-Id: I6eba8e8010466e71efe9c5e06848b9f403df835f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275131 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* skylake: Use a simulated power button press to force-shutdown the APShawn Nematbakhsh2015-06-041-0/+9
| | | | | | | | | | | | | | | | Holding the power button is currently the best known way to bring the AP back to a state where it is shutdown and not powered. BUG=chrome-os-partner:40826, chrome-os-partner:40677 TEST=Run `apshutdown` on glados, verify that power state machine transitions to G3 after several seconds. Run `powerbtn`, verify that state machine transitions back to S0. BRANCH=None Change-Id: Ia799c5f199127f31bd24907b93946c6289d381f8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275060 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* motion: Add MOTIONSENSE_CMD_DATA: retrieve single sensor dataGwendal Grignou2015-06-031-1/+18
| | | | | | | | | | | | | | MOTIONSENSE_CMD_DATA return the value of a sinlge sensor. BRANCH=none BUG=chrome-os-partner:39900 TEST=On Smaug, using the new cros-ec-sensors driver, check sensors data using iio sysfs interface. Change-Id: I618ff050e0c7b4247ac56cfb0ca25e351270e1d6 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274824 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: implement TCPC RX Detect register to enable/disable TCPC RXAlec Berg2015-06-034-44/+74
| | | | | | | | | | | | | | | | | | | | | | | Implement the TCPC RX Detect register and use it for the TCPM to enable and disable PD communication. When no type-C connection, disable TCPC RX so that we don't send goodCRC when we are not ready. Once TCPM establishes a type-C connection, enable TCPC RX. BUG=none BRANCH=none TEST=tested on glados and on samus. On glados, without this change, sometimes when you plug in zinger, we get into a hard reset loop because TCPC is sending goodCRC to source cap while TCPM is still debouncing CC and is not ready. With this change, we reliably form PD contract. Also tested enabling and disabling PD comms from the TCPM console with "pd enable 0|1". Change-Id: I8c9e696f2597978436f6ceccfe06ffb021c95ea3 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274811 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* uart_buffering: extend CONSOLE_READ command for easy log concatenationstabilize-7134.BEric Caruso2015-06-021-8/+56
| | | | | | | | | | | | | | | | | | | | | | | | I'm planning to add functionality to the kernel which periodically dumps the EC console log and concatenates it so we can use it in bug reports and feedback. However, stitching together logs collected using the existing SNAPSHOT/READ commands is difficult. This adds a new version of READ which acts mostly the same but will only give you the difference between the two most recent snapshots when you pass the corresponding argument. BRANCH=ToT BUG=chromium:492721 TEST=On samus with kernel interface, cat /sys/kernel/debug/cros_ec/console_log and verify that the most recent bit of the log is printed, use spammy commands like 'accelinfo on' and make sure nothing breaks, check that 'ectool console' behavior has not changed Change-Id: Ib8216caa917715820c3e265400f0db2125e8808b Signed-off-by: Eric Caruso <ejcaruso@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273581 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* oak: Add PD communication to oakAlec Berg2015-05-301-0/+3
| | | | | | | | | | | | | | | | | | Add TCPM on EC side and TCPC on PD side to allow PD communication. Enable PD communication on port 0. BUG=none BRANCH=none TEST=load on oak. plug in hoho on port 0, and make sure we successfully negotiate a PD contract. (note: you have to manually enable 5V VBUS right now) Change-Id: I0ce7c016545bc56c5e10f66b49b73722187f12dc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271829 Reviewed-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Sheng-liang Song <ssl@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org>
* keyboard_mkbp: fix interrupt handling with MKBP_EVENTVincent Palatin2015-05-301-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_MKBP_EVENT is enabled, the current code is incorrect because we have a race condition when sending a new event (we force first the interrupt, then send the actual event content to the mkbp event framework which forces again the interrupt level). If the software still called EC_CMD_MKBP_STATE while CONFIG_MKBP_EVENT is enabled, this will kill the interrupt as soon as the FIFO is empty even though other events are pending in order to be backward compatible with firmware using the interrupt has a hint when polling the keyboard. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33194 TEST=make buildall fiddle with keyboard on Oak. Change-Id: Iafaf4174124934328c4a0172adeca651e5551f28 Reviewed-on: https://chromium-review.googlesource.com/274070 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: fix tcpc alert to handle multiple alert bits set at onceAlec Berg2015-05-291-3/+6
| | | | | | | | | | | | | | | | Fix tcpc_alert() so it can handle multiple alert bits. This is needed since the initial version of tcpc_alert() is read/clear and so we need to service all bits or else it will get lost. BUG=none BRANCH=none TEST=test on glados. see multiple alert bits and handle both of them. Change-Id: I4d2a19a5d5d6f85cad3d67a96217d65e6e65715c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274084 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: enable MBKP events for PD eventsVincent Palatin2015-05-281-1/+1
| | | | | | | | | | | | | | | | | | | enable the MKBP event feature to send host event and wire up the PD specific events. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33194 TEST=On Ryu P6, plug/unplug USB devices and add kernel trace to see the PD events happening. Change-Id: I21f47884a869987c917e56ed9b3f914815af51e4 Reviewed-on: https://chromium-review.googlesource.com/273620 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: fix type-C current limit detectionVincent Palatin2015-05-281-2/+2
| | | | | | | | | | | | | | | | | | | | There was a small typo in get_typec_current_limit() since the introduction of the new TCPCI constants, we need to find the current limit by using the voltage values measured on the sink side. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:40719 TEST=Connect Donette to Ryu and see the current limit set to 3.0A using the "charger" command. Change-Id: Icb4a5ea4997265dc1edeeb4d3cc69e416b864707 Reviewed-on: https://chromium-review.googlesource.com/273679 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Initialize the memory-mapped AC_PRESENT flagTed Kuo2015-05-281-0/+8
| | | | | | | | | | | | | | | | | | | The memory-mapped AC_PRESENT flag needs to be initialized for the batteryless projects. BUG=chrome-os-partner:40384 TEST=make -j buildall, make -j tests BRANCH=None Signed-off-by: Ted Kuo <tedkuo@ami.com.tw> Change-Id: Ia64ad6564f99b4aae060d29a572b4fe173da62d9 Reviewed-on: https://chromium-review.googlesource.com/273082 Tested-by: Ted Kuo <tedkuo@ami.com.tw> Reviewed-by: Mohammed Habibulla <moch@google.com> Commit-Queue: Ted Kuo <tedkuo@ami.com.tw> (cherry picked from commit 6cc0ece36d4190e2461f7e44767e0f77f47401b8) Reviewed-on: https://chromium-review.googlesource.com/273462 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: avoid re-sending discovery VDMs after power swapAlec Berg2015-05-271-7/+6
| | | | | | | | | | | | | | | | | | | Avoid re-sending discovery VDMs after power swap from source to sink. BUG=chrome-os-partner:40657 BRANCH=samus TEST=tested connecting samus to samus. tested power swapping back and forth and verify that we don't re-send discovery VDMs. Tested soft reset and verified that we don't re-send discovery VDMs. Tested hard reset and verified that we DO re-send discovery VDMs. Change-Id: Ib48c134f460eb776b7c6f5c1d86a5b56bb08ebcc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273420 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: never answer malformed VDMVincent Palatin2015-05-271-0/+2
| | | | | | | | | | | | | | | | | | | When we are receiving a VDM which seems malformed, don't try to send an answer, else we can ping-pong broken messages with the other side. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=plug Ryu P6 to plankton, no longer see endless "ERR:CMDT:1" error messages. Change-Id: If5b581c5c68996c60e37ac6d96638fd5df24356f Reviewed-on: https://chromium-review.googlesource.com/273525 Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* tcpm: return all non-zero errorsRong Chang2015-05-271-4/+4
| | | | | | | | | | | | | | TCPM functions calls I2C read/write, which returns positive error codes on stm32f0 based EC. BRANCH=none BUG=none TEST=none Change-Id: I8119074e7411e2fd88dd6ca696fc7b698d462623 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273506 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: fix duplicate PD receive event on combined TCPM/TCPCAlec Berg2015-05-271-0/+9
| | | | | | | | | | | | | | | | | | Fix duplicate PD RX event when using combined TCPM/TCPC. Problem is that PD_EVENT_RX is already set in the phy layer in pd_rx_event when CC edges are detected. Therefore, we shouldn't set it again when the TCPC detects that receiving has started. BUG=none BRANCH=none TEST=test on samus. without this change we occasionally get a PD error and hard reset under certain timing circumstances due to the repeated event. with this change, those errors go away. Change-Id: If1034a549b75740f327e16810e81c9aa28d71b00 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273418 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Make i2c_xfer a wrapper function to chip_i2c_xferShawn Nematbakhsh2015-05-271-0/+7
| | | | | | | | | | | | | | | | i2c_xfer was previously implemented at the chip-level, but now we want to add some global retry logic. Rename the chip-level i2c_xfer functions to chip_i2c_xfer and add a new global wrapper function i2c_xfer. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan, verify that values + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6 Reviewed-on: https://chromium-review.googlesource.com/272939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* oak: add initial support for oak board rev1Rong Chang2015-05-271-3/+1
| | | | | | | | | | | | | | | Add initial support for Oak rev1 board. This is just the EC and includes battery charging but does not include USB PD. BUG=none BRANCH=none TEST=load on oak board and get console Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Alec Berg <alecaberg@chromium.org> Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777 Reviewed-on: https://chromium-review.googlesource.com/261678
* pd: move non-phy layer config out of usb_pd_config.hAlec Berg2015-05-276-87/+87
| | | | | | | | | | | | | | | | | | | | | Move parts of usb_pd_config.h that are not part of the phy layer out of usb_pd_config.h and into board.h. This cleans up the division between the TCPC and TCPM as only the TCPC needs to use usb_pd_config.h. Also cleans up the use of the CC detection voltage thresholds by creating standard macros to use based on Rp strength for the board. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I946cceb38bea8233095b8a4b287102bb8a3a296d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270337 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Move i2c_read_string to common codeShawn Nematbakhsh2015-05-261-0/+30
| | | | | | | | | | | | | | | | | Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the lm4 i2c_read_string implementation to common code and delete all chip-specific versions. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan and Oak, verify that battery info + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa Reviewed-on: https://chromium-review.googlesource.com/272938 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Producer/Consumer: Refactor to use Queue policiesAnton Staaf2015-05-265-110/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the Producer and Consumer interfaces tracked the Consumer and Producer respectively at the other end of the queue that they interacted with. This was done to avoid modifying the queue implementation, but resulted in a rougher interface that required additional initialization steps and prevented alternative configurations; many producers and one consumer for example. This commit uses the new queue policies to track this information. The new direct policy behaves as the old producer and consumers did. Now the producers and consumers are just named references to the queue that they work on and a convenient location for a notification callback when the queue is updated in a way that is relevent to the producer or consumer. All users of Producer and Consumer have been updated including the stream adaptors which are in use by the echo test code and the mcdp28x0 driver. Use of the stream adaptors has also been simplified. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manual testing of Ryu (P5) and discovery board echo task Change-Id: I704be6378a31b4e20f5063295eff9943e4900409 Reviewed-on: https://chromium-review.googlesource.com/271792 Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* Queue: Add policies to queuesAnton Staaf2015-05-262-2/+22
| | | | | | | | | | | | | | | | | | | | Policies give a convenient place to hook into the queue operations and notify something that there is new space free in the queue or new units added. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I94b2aa94b8e8d07911191bc19a39fa827623b117 Reviewed-on: https://chromium-review.googlesource.com/271791 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* pd: add first version of TCPCI I2C interfaceAlec Berg2015-05-224-96/+392
| | | | | | | | | | | | | | | | Add first version of TCPCI (type-C port controller interface), which is an I2C protocol for interfacing with TCPCs. This is roughly tracking version 0.56 of the PD Interface spec. BUG=none BRANCH=none TEST=tested on oak. modified oak EC to be TCPM and oak PD to be TCPC and tested we can negotiate with hoho and zinger. Change-Id: I83644ca83f2d3ce69d5d8356beca20a7ab155a87 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270172
* pd: add config options for including TCPM and TCPC separatelyAlec Berg2015-05-223-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Add config options for various parts of USB PD stack: CONFIG_USB_POWER_DELIVERY: The use of this option has changed slightly. It now represents whether or not to include the USB PD protocol and policy layers of the software stack. CONFIG_USB_PD_TCPC: Compile in type-C port controller module which performs the phy layer of the PD stack. CONFIG_USB_PD_TCPM_STUB and CONFIG_USB_PD_TCPM_TCPCI: If CONFIG_USB_POWER_DELIVERY is defined, then one TCPM needs to be defined to declare which port management module to use to drive the TCPC. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I41aa65a478e36925745cd37a6707f242c0dfbf91 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270171 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: initial split of protocol code to create port controllerAlec Berg2015-05-224-735/+1185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial split of the USB PD protocol code to create the new port controller (TCPC) and port management (TCPM) blocks. The intention is that the TCPC code will eventually reside on a different MCU, along with the USB PD phy layer. The TCPM will stay with the protocol and policy layers and provide a standard interface to TCPC (over i2c). As a first step, this CL merely splits up the files and directly calls functions to reach across between TCPM and TCPC. BUG=none BRANCH=none TEST=tested on samus using zinger, hoho, another samus, donette, and a third party PD charger. Tested the following: - dual-role toggling - forming a connection as a source and as a sink - power negotiation at different voltages - charging - sourcing power to USB stick - soft reset - hard reset - power swap - data swap - bist mode 2 - zinger remote firmware updates Change-Id: I70bd68a003c81e075310913f10351b792f76d7e0 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-193-4/+6
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* driver: Add BMM150 behind BMI160 support.Gwendal Grignou2015-05-161-1/+1
| | | | | | | | | | | | | | | | Add support for Bosh Sensortec BMM160 compass. We access it through BMI150. BRANCH=none BUG=chrome-os-partner:39900 TEST=Test on a nucleo board and smaug. Change-Id: I5b959cab4f9341ba0fcd3ed9bad815fa92f80a37 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271525 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-154-31/+28
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* driver: Use common data structure to store default accel valuesGwendal Grignou2015-05-121-7/+8
| | | | | | | | | | | | | | | Move structure used by lms6ds0 to motion_sense.h, so that bosh driver can use the same mechanism. Use code to avoid reading chip range when reading data. BUG=none BRANCH=none TEST=Check Bosh driver is working as expected. Change-Id: Id8b5bb8735e479a122ef32ab9a400fba189d7488 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270453 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-127-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* ec: Add Inventory commandGwendal Grignou2015-05-071-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add command that list supported features by the firmware. Also let the firmware indicates if more features are expected in the RW version. This will help the cros_ec framework load the right driver(s) for exposing information via sysfs. BUG=chromium:428364 BRANCH=none TEST=Test on samus on both ec and pd: localhost ~ # ectool inventory EC supported features: 1 : Flash support 2 : Direct Fan power management support 3 : Keyboard backlight support 4 : Lightbar support 6 : Motion Sensors support 7 : Keyboard support 9 : BIOS Port 80h access support 10 : Thermal management support 11 : Switch backlight on/off support 12 : Switch wifi on/off support 13 : Host event support 14 : GPIO support 15 : I2C master support 16 : Charger support 17 : Simple Battery support 18 : Smart Battery support 21 : Control downstream MCU support localhost ~ # ectool --name cros_pd inventory EC supported features: 1 : Flash support 14 : GPIO support 15 : I2C master support 22 : USB Cros Power Delievery support Change-Id: Ib6eaac91fda86835e754c5316ecf81fbc27786e5 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/263463 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Sameer Nanda <snanda@chromium.org>
* pd: fix PDO selection for low voltage boardsstabilize-7039.BVincent Palatin2015-05-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the policy of the board is to select lowest voltage providing enough power, the current algorithm ignores the fact that the board input current limit might be lower than the charger maximum current for a particular voltage level leading to the possibility of selected a voltage with a lower available power. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=set a Ryu board with the following configuration : PD_PREFER_LOW_VOLTAGE PD_MAX_POWER_MW 24000 PD_MAX_CURRENT_MA 1000 PD_MAX_VOLTAGE_MV 20000 connect it a Zinger (offering 3A @ 20V, 3A @ 12V and 3A @ 5V), see it selecting 20V rather 12V before the patch. Change-Id: I8c0589bb5e5705c4d8a6035120d1cdfaacaa14df Reviewed-on: https://chromium-review.googlesource.com/269262 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: add explicit setting of D+/D- switch when setting type-C muxesAlec Berg2015-05-051-5/+18
| | | | | | | | | | | | | | | | | | | Add explicit setting of USB D+/D- switch when setting the type-C muxes. This fixes a bug in which we would open D+/D- switch when entering DP mode and lose USB2.0 connection. BUG=chrome-os-partner:39766 BRANCH=samus TEST=add printf to board_set_usb_switches() on samus and make sure we don't open the D+/D- switch when entering DP mode. Change-Id: I2b5bb2185298794ddb4cc457f3695ce6adabd9f8 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/268993 Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ryu: fork P4/P5 supportVincent Palatin2015-05-021-2/+2
| | | | | | | | | | | | | | | | | | | In preparation for Proto 6 board support which won't be backward compatible, fork the EC for Proto 4 and Proto 5 for people who need to support older boards. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:39202 TEST=make buildall Change-Id: I520bbf146cc1c1dc04e55283be57807ec19ebaa1 Reviewed-on: https://chromium-review.googlesource.com/266064 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cli: add ability to read/write memory of different bus widthVadim Bendebury2015-05-021-17/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds an optional extra parameter to the 'rw' command. When the first argument is .b or .s, the access size becomes 8 pr 16 bits respectively. BRANCH=none BUG=none TEST=on the EC console: > rw 0x10000 read 0x10000 = 0x00000000 > rw .b 0x10000 0x55 write 0x10000 = 0x55 > rw 0x10000 read 0x10000 = 0x00000055 > rw .b 0x10000 read 0x10000 = 0x55 > rw .s 0x10002 read 0x10002 = 0x0000 > rw .s 0x10002 0x1234 write 0x10002 = 0x1234 > rw 0x10000 read 0x10000 = 0x12340055 > rw .b 0x10000 read 0x10000 = 0x55 > rw .b 0x10001 read 0x10001 = 0x00 > rw .b 0x10002 read 0x10002 = 0x34 > rw .b 0x10003 read 0x10003 = 0x12 > rw .s 0x10000 read 0x10000 = 0x0055 > rw .s 0x10002 read 0x10002 = 0x1234 > rw . 0x10002 Parameter 1 invalid Usage: rw addr [.{b|s}] [value] > Change-Id: Iad1a4b3e297253ffdbf13afeede8ade9451eb11a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/268897 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charge_ramp: fix flaky charge_ramp testAlec Berg2015-05-021-6/+0
| | | | | | | | | | | | | | | | | | | | Fix flaky charge_ramp test. The test often delays CHARGE_DETECT_DELAY after a new charger has been plugged in. But, that is the same delay the charge_ramp module uses before starting to ramp. This creates a race condition where sometimes the test resumes before the ramp up starts and sometimes the test resumes after the ramp up starts. This change fixes the problem by modifying the test to delay by 100ms less than the charge_ramp module. BUG=chromium:483543 BRANCH=none TEST=run charge_ramp test 10 times w/o this CL and see failure 4 times. run test 20 times with this CL and observe 0 failures. Change-Id: I5f7a6a05f9293d3dd7db5517a9df7caec95c58ea Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/268798 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: rename motion sensor CONFIG_ optionsBill Richardson2015-05-012-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames some motion sensor options to start with more consistent prefixes. For gesture (tap) detection: CONFIG_GESTURE_DETECTION: CONFIG_SENSOR_BATTERY_TAP => CONFIG_GESTURE_SENSOR_BATTERY_TAP For detecting lid angle: CONFIG_LID_ANGLE: CONFIG_SENSOR_BASE => CONFIG_LID_ANGLE_SENSOR_BASE CONFIG_SENSOR_LID => CONFIG_LID_ANGLE_SENSOR_LID BUG=none BRANCH=none TEST=make buildall Change-Id: Ib8f645902a5585346e1d8d2cbf73d825c896a521 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/268777 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charge_manager: modify PD power HC to give more info on currentAlec Berg2015-05-012-18/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the EC_CMD_USB_PD_POWER_INFO host command to report the input current limit and the max current theoretically possible given the charger. The input current limit field is useful for logging purposes and the max current field is useful to give to powerd to determine if we have a low power charger connected. The max current is determined by checking if the charge supplier is allowed to ramp. If the charge supplier is allowed to ramp and has not completed ramping yet, then max current is the max current that we are allowed to ramp up to. Once the ramp has completed, then max current is the stable charging current. If the charge supplier is not allowed to ramp, then max current is simply the max current as registered with charge_manager. The point here is to keep the max as high as possible until we know for sure it is lower to avoid showing the user the low power notification until we know for sure. This CL also adds a new charger type, USB_CHG_TYPE_UNKNOWN. For a short period after a charger is plugged in, the supplier type may change and PD negotiation is still in process, and therefore we tell the host we have an unknown charger type. This allows powerd to show the charging icon, but delay determining if this is a low power charger until we know for sure. BUG=chrome-os-partner:38548 BRANCH=samus TEST=tested with zinger, a DCP, an SDP, and a proprietary charger. tested that low power notification never pops up with zinger, even if you purposely wedge charge circuit with "charger voltage 7000" on EC console. tested that the other chargers all pop up low power notification once the supplier changes from UNKNOWN to the real supplier. used "ectool --name=cros_pd usbpdpower" to check current values. Change-Id: If8a9a1799504cc2a13238f4e6ec917d25d972b22 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/265066 Reviewed-by: Sameer Nanda <snanda@chromium.org>
* pd: Allow for setting USB mux when swapping into DFP roleScott2015-05-011-7/+16
| | | | | | | | | | | | | | | | | | | | | - Added config option CONFIG_USBC_SS_MUX_DFP_ONLY - If this options is enabled, then the mux is set to TYPEC_USB_MUX only is data role is DFP. - If this option is not enabled, the mux is set for both UFP and DFP (i.e. RYU) BUG=chrome-os-partner:39059 TEST=Manual samus to plankton, switching between source and sink modes. Forced data role swap via ec console command. BRANCH=Samus Change-Id: Ibc2fb0ad42d0fe415d3338d38da94ad4b041513b Signed-off-by: Scott Collyer <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266916 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* plankton: HPD over USB PD.Todd Broch2015-05-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HPD needs to be transported over USB PD as both SBU lines are consumed for differential AUX signalling. This CL does the following: 1. Enables GPIO DPSRC_HPD as interrupt. 2. Sends debounced HPD across CC via the SVDM DP status message. 3. Adds polling for GPIO_DBG_20V_TO_DUT_L as it shares the same interrupt as DPSRC_HPD. 4. Configures DP redriver in presence of HPD high. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=none BUG=chrome-os-partner:33132,chrome-os-partner:33761 TEST=manual, 1. Connect samus -> plankton via type-C 2. Connect plankton -> DP monitor via displayport See initial SVDM discovery on samus console See EDID information See SVDM status message correct when plug/unplug DP cable from plankton 3. Press 'CHARGING_20V_TO_DUT_L' button and see below on plankton console. Button 8 = 0 Change-Id: Id95567a3bfa073ffa2c699335be8c5bf0327675f Reviewed-on: https://chromium-review.googlesource.com/229429 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org>
* samus_pd: Request different DP pin modes including multi-function.Todd Broch2015-04-301-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously samus_pd just picked pin mode E without regard to what the UFP was requesting. This change surveys the UFP's DP pin capabilities and then requests the appropriate pin config. Additionally if the UFP supports multi-function and has preferred it during the initial DP status message, samus will configure its type-c mux in 'dock' mode. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:38728 TEST=manual, 1. hoho + samus, pin mode = 'C' 2. dingdong + samus, pin mode = 'E'. 3. apple type-C HDMI multiport + samus, pin mode = 'D' and USB device enumerates as SuperSpeed. 4. plankton + samus w/ patch asserting alternate mode with multi-function preferred sets config to 'F' now and only drives DP out on 2 lanes w/ other two allowing USB key to be seen. Change-Id: Ie4764c33f108e8a88f0052b64ddb96cb92e5a78b Reviewed-on: https://chromium-review.googlesource.com/267796 Commit-Queue: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: cleanup PD receive error enumAlec Berg2015-04-291-5/+5
| | | | | | | | | | | | | | Cleanup PD receive error enum by including RX in name since we will have a different enum for TX errors. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I355092e0e73a022acb4a92736374cd2289d324bf Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/267670 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Added task-based Port80 POST code support.Kevin K Wong2015-04-271-0/+47
| | | | | | | | | | | | | | | | | | | | | | With mec1322's EMI set to decode IO 0x800, it does not have any other interfaces to support POST code via IO 0x80. This change is to enable Port80 POST code support via polling method. Limitation: - POST Code 0xFF will be ignored. - POST Code frequency is greater than 1 msec. BUG=chrome-os-partner:39386 TEST=Verified Port80 POST code is captured in EC console. Verified "port80 task" console command will disable/enable Port80 task. Verified "port80 poll" will get the last Port80 POST code. BRANCH=none Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/266783 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* samus: add device to dual-role charging white listAlec Berg2015-04-271-1/+1
| | | | | | | | | | | | | | Add Apple VGA charge-through adapter PID to dual-role charging white list so that we automatically charge through it. BUG=chrome-os-partner:38785 BRANCH=samus TEST=make -j buildall Change-Id: I5de757a9e97824a2b488a45497c73ab53cc1899c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/267300 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: continue dual-role toggling when detect Open/RaAlec Berg2015-04-251-14/+13
| | | | | | | | | | | | | | | | | | | | | | As a source, when we detect Open/Ra (active cable with no UFP) then do not transition to debounce CC line, instead continue dual-role toggling as if nothing is connected. BUG=chrome-os-partner:35652, chrome-os-partner:39486 BRANCH=samus TEST=test with samus and twinkie. on twinkie, simulate Open/Ra with: "tw res ra nc" and verify that we continue dual-role toggling. Then plug in zinger and verify we negotiate and start charging. Also, tested case where we initially detect Open/Rd and start debouncing, but then it turns into Open/Ra: echo "tw res rd nc" > /dev/ttyUSB0; sleep 0.05; echo "tw res ra nc" > /dev/ttyUSB0 In this case, samus transitions to SRC_DEBOUNCE briefly, then goes back to disconnected state and continues dual-role toggling. Change-Id: Idabac60b9e2f54639d7a6305d96e9984b0600519 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/267087 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: ignore cable resetAlec Berg2015-04-241-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Identify and ignore cable reset PD command BUG=chrome-os-partner:39464 BRANCH=samus TEST=connect two samus'. on one samus add code to send a cable reset like such: int send_cable_reset(int port) { int off; CPRINTF("C%d Send cable reset\n", port); /* 64-bit preamble */ off = pd_write_preamble(port); /* Hard-Reset: 3x RST-1 + 1x RST-2 */ off = pd_write_sym(port, off, BMC(PD_RST1)); off = pd_write_sym(port, off, BMC(PD_SYNC1)); off = pd_write_sym(port, off, BMC(PD_RST1)); off = pd_write_sym(port, off, BMC(PD_SYNC3)); /* Ensure that we have a final edge */ off = pd_write_last_edge(port, off); /* Transmit the packet */ if (pd_start_tx(port, pd[port].polarity, off) < 0) { pd[port].send_error = -5; return -5; } pd_tx_done(port, pd[port].polarity); /* Keep RX monitoring on */ pd_rx_enable_monitoring(port); return 0; } Without this CL, the receiving samus times out and ends up causing equivalent of hard reset. With this CL, we receive cable reset and drop it. Also used twinkie to measure goodCRC delay. No measureable change in delay on samus and zinger. Samus delay is ~70us and zinger delay is ~65us. Change-Id: Ic0e871c8cf96502b861f430e05ee145881fb55fa Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266981 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: lfw loader + RO/RW architectureDivya Jyothi2015-04-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mec1322 only has 96KB program memory, vs 256KB flash space on lm4.We no longer have enough program memory to load both RO and RW at boot. We'll want to implement a small loader program that will load either RO or RW from flash, and then jump to the loaded image. CONFIG_FW_INCLUDE_RO is enabled to include RO image into the build. pack.py script is altered to load the (lfw + R)O on boot. Software sync is not added.Distinguish between RO/RW is yet to be added. flash_ec is altered to support padding 0xFFs to 256k ec.bin to match the size of the SPI flash of the board. BUG=chromium:37510 BRANCH=None TEST=Make -j buildall,Verified ec.bin to be 256k. Verified RW image at offset 0h and (lfw + RO) at offset 2000h. On boot sysjump to lfw. lfw checks in shared SRAM (currently RO) and jumps to RO image. Change-Id: Ib9b114e2f24a615d5e5bd8b3803be621d1e5bd17 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265807 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
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