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* Kunimitsu: remove console commands for code sizeKyoung Kim2016-04-142-3/+4
| | | | | | | | | | | | | | | | | | | | | Remove following EC console commands to reduce code size: - battfake - apthrottle And none of commands above are used in 'auto test'. This is a squash of - https://chromium-review.googlesource.com/337657 - https://chromium-review.googlesource.com/338018 BUG=none BRANCH=firmware-glados-7820.B TEST=make -j buildall Change-Id: I11d2c5514f2714f0a46416feec2b2c47666fb462 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/338893 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Fix multiple reboot for battery cut-offDivya Sasidharan2016-04-132-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | In case of boot after battery is cut-off without this change the battery is assumed to be present even though it is not initialized and ready to provide power in try source enable function. With this assumption charger is disconnected momentarily which causes reboot. Also make sure that try source enable is updated after battery is ready by notifying hook call HOOK_BATTERY_SOC_CHANGE. BUG=chrome-os-partner:51753 BRANCH=firmware-glados-7820.B TEST=Enter battery cutoff command from EC console to enter into ship mode and plug-in AC, verified no reboots happen. Change-Id: I6f7656125717f85851f5ad4e37dfd953a52799c6 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/335913 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 10040ac6284efe88b74193bdbb0c05ec92b563b4) Reviewed-on: https://chromium-review.googlesource.com/336697 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* charger_state_v2: force static battery info update on battery changeKevin K Wong2016-04-131-0/+5
| | | | | | | | | | | | | | BUG=none BRANCH=none TEST=on system which has different static battery info based on battery present, when the present status has changed, verify the battery info is also changed. Change-Id: Id58c545e3315dc63c6dd6b59141b6302d767bfb7 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331655 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Add config to disable PD communication in locked ROShawn Nematbakhsh2016-04-111-1/+21
| | | | | | | | | | | | | | | | | | | | The scheme to disable PD communication in locked RO needs to be implemented on other platforms, so move it to common code, behind CONFIG_USB_PD_COMM_LOCKED. BUG=chrome-os-partner:52157 BRANCH=glados TEST=Manual on chell. Lock system and boot to recovery, then verify PD communication is functional. Enable CONFIG_USB_PD_COMM_LOCKED and verify PD communication isn't functional under the same test conditions. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I8d1f24c0b60cf1c54e329af003b7083ee55ffc40 Reviewed-on: https://chromium-review.googlesource.com/338064 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Support RW_B in sysjump command when applicablestabilize-8172.47.BBill Richardson2016-04-081-1/+19
| | | | | | | | | | | | | | | | | | | | If we #define CONFIG_RW_B, the firmware image can have two RW components. This CL expands the "sysinfo" command so that we can see which image we're running from when RW_B is also a possibility. BUG=chrome-os-partner:50701 BRANCH=none TEST=make buildall; test RW update on Cr50 Using test/tpm_test/tpmtest.py, update the RW firmware and reboot several times to switch between RW_A and RW_B. Note that the "sysjump" command reports the correct image each time. Change-Id: Iba3778579587f6df198728d3783cb848b4fd199d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337664 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: add support for creating multiple serial endpointsMary Ruthven2016-04-072-114/+0
| | | | | | | | | | | | | | | | | CR50 will need three serial endpoints for the streaming AP and EC UART and exporting its own console through USB. This change adds a macro to create endpoints that can be recognized by the usb_serial driver. BUG=chrome-os-partner:50702 BRANCH=none TEST=Verify "/dev/google/Cr50*/serial/Blob" prints capital letters when lower case letters are input. Change-Id: Iddf2c957a00dc3cd5448a6a00de2cf61ef5dd84c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336441 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* charge_manager: Report UNKNOWN USB charger for 2 seconds after changeShawn Nematbakhsh2016-04-031-7/+30
| | | | | | | | | | | | | | | | | | | After a charger is attached, we may set a charge limit based upon BC1.2 or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds for all negotiation to complete. Previously this behavior was implicit when using SW charge ramp. BUG=chrome-os-partner:51280 BRANCH=glados TEST=Manual on chell. Insert stock charger, verify that it is detected as TYPE_UNKNOWN until timeout. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028 Reviewed-on: https://chromium-review.googlesource.com/334312 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* console: Put additional console commands behind CONFIGsShawn Nematbakhsh2016-04-032-1/+4
| | | | | | | | | | | | | | | | Allow boards to save flash space by undef'ing CONFIGs which gate 'hcdebug' and 'md' console commands. BUG=chrome-os-partner:34489 BRANCH=None TEST=`make buildall -j` Change-Id: I583b98ff1e4d9d6a26958c6895fb0c0305dddceb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336813 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ectool: Support keyboard factory scanningDevn Lu2016-04-011-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | This is keyboard test mechanism request for "multiple key press test", we can thru the testing to scan out kso ksi pins shortting or keyboard has multiple key pressing, below was the testing steps: 1. Turn off internal keyboard scan function. 2. Set all scan & sense pins to input and internal push up. 3. Set start one pin to output low. 4. check other pins status if any sense low level. 5. repeat step 3~4 for all keyboard KSO/KSI pins. 6. Turn on internal keyboard scan function. BUG=chrome-os-partner:49235 BRANCH=ToT TEST=manual Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed. if no pins short together, it shows passed. Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/332322 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Include low-power exit triggers in reset causesBill Richardson2016-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Some of the reset causes are found in another register when resuming from a low-power state. We know we'll need to distinguish among them eventually, so we might as well decode them now. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 I forced the system into deep sleep and observed that the reset cause is accurately recorded on resume. Doing that requires a fair amount of hacks and manual effort, and can't happen by accident. Future CLs will make use of this. The current, normal behavior is completely unaffected. Change-Id: I5a7b19dee8bff1ff1703fbbcc84cff4e374cf872 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336314 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* spi_flash: print spi flash size in proper unitNaresh G Solanki2016-03-301-1/+1
| | | | | | | | | | | | | Spi flash size is calculated in the units of kB but is printed as MB. correcting it to kB unit. Change-Id: If71681fc868a5974b44d135055c01f9184c71602 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332732 Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Tested-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* Fan: enable fan after system resumeKeith Tzeng2016-03-301-1/+1
| | | | | | | | | | | | | | | | | | Fan will disable when S3 and S5 by pwm_fan_s3_s5, which call set_enabled(fan, 0) to disable it. But the pwn_fan_resume called fan_set_enabled() which not setting GPIO_FAN_PWR_DIF_L to 1, we should use set_enabled() instead. BUG=chrome-os-partner:50372 BRANCH=master TEST=check fan enable after system resume Signed-off-by: Keith Tzeng <Keith.Tzeng@quantatw.com> Change-Id: Id0bd4dd0afc7e02bcfa6e20401d6e9dfe8a81423 Reviewed-on: https://chromium-review.googlesource.com/335693 Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com> Tested-by: Keith Tzeng <keith.tzeng@quantatw.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* spi_flash: Reload watchdog before writing a flash pageShamile Khan2016-03-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When EC receives many flash write requests from host and PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the HOOK task may not get scheduled in time to pet the watchdog resulting in an EC reset. BUG=chrome-os-partner:51438 BRANCH=None TEST=Manual on lars, determine two EC versions that have enough differences so that replacing one image with the other will require all or most of the flash pages to be updated. Alternate between flashing the two images with flashrom using a script. Atleast 1000 iterations should pass. Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334457 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52) Reviewed-on: https://chromium-review.googlesource.com/334903 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* Cr50: cleanup: Clarify a few commentsBill Richardson2016-03-241-0/+7
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall; try on Cr50 No code changes, just comments. Change-Id: I3eccccb024b4a319920a8252cd7d5d3829bf21da Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/334820 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* usb_port_power_smart: Support variable port countchris wang2016-03-241-25/+32
| | | | | | | | | | | | | | | | | | | | Use CONFIG_USB_PORT_POWER_SMART_PORT_COUNT to support more usb ports (default 2). BUG=None BRANCH=firmware-strago-7287.B TEST=build&flash ec,verify on wizpig,usb function work Signed-off-by: Chris Wang <chriswang@ami.com.tw> Change-Id: I2460d4a5755ef457249d728169c27fc6d00625d2 Reviewed-on: https://chromium-review.googlesource.com/333232 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: lehai deng <denglehai@ithaier.com> Commit-Queue: Chris Wang <chriswang@ami.com.tw> Tested-by: Chris Wang <chriswang@ami.com.tw> (cherry picked from commit 1e7d3554f1bedbb839a0f4800286c9db0d27e4f1) Reviewed-on: https://chromium-review.googlesource.com/334510 Commit-Ready: Chris Wang <chriswang@ami.com.tw>
* Console: Fix channel enum valuesAnton Staaf2016-03-221-53/+9
| | | | | | | | | | | | | | | | | | | The channel enum and string name array were out of sync (when CONFIG_EXTENSION_COMMAND is defined). This was caused by the two lists being specified separately. I argue that this is a good reason to merge the lists into a separate X-Macro include file. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I81d143f550a0fe6ef0c64e3c8357ed18aee4bfdc Reviewed-on: https://chromium-review.googlesource.com/334381 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* smbus: Re-write smbus driverShawn Nematbakhsh2016-03-211-168/+108
| | | | | | | | | | | | | | | | | Re-write smbus driver to fix arbitrary length read and improve code organization. BUG=chromium:576911 BRANCH=None TEST=Manual on sentry. Verify that smbus communication with battery is functional. Change-Id: I63c4bc3df40755cd41b3d9956af0ab9d2145a253 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333787 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* crc8: Support crc calculation across non-contiguous dataShawn Nematbakhsh2016-03-181-2/+7
| | | | | | | | | | | | | | | | | Building a single buffer for crc calculation is often inefficient, so add a new function that calculates crc8 from an existing crc8. BUG=chromium:576911 BRANCH=None TEST=Manual on sentry with subsequent commit. Verify that smbus communication with battery is functional. Change-Id: I05ffedb81ffcf0c126acda5f6212b3147b1580a1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/333786 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Add error handling for pd_send_request_msg()Shawn Nematbakhsh2016-03-141-7/+14
| | | | | | | | | | | | | | | | | | | If we have already completed negotiation as a sink and pd_send_request_msg() fails, issue a soft reset so we don't remain indefinitely at our previously negotiated voltage. BUG=chrome-os-partner:50346 BRANCH=glados TEST=Manual on chell. Attach zinger to port 1, then attach zinger to port 2. Verify that port 1 negotiated to 20V. Detach port 1 and verify port 2 successfully negotiates to 20V and begins charging. Change-Id: I4f8ff9a1e3ef49858f6ae5c3ccb5b5d4d847e2d1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/332642 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mkbp_event: prevent unnecessary interrupts to APKoro Chen2016-03-101-2/+2
| | | | | | | | | | | | | | | | | | | | After commit 237406c5b12ed9934fc6eab7d24f30ba6e70fdce, there is chance that pd_power_supply_reset() will be called during S0->S3, and it interrupts AP and fails suspend if we are using MKBP_EVENT. This is because mkbp_send_event() does not check power state POWER_S0S3. Modify the condition to check events when AP is not in S0. BRANCH=none BUG=chrome-os-partner:50833 TEST=powerd_dbus_suspend always works without being resumed Change-Id: Id905a2cd4d2a0376bca163f40c68bcf4208d8bf5 Signed-off-by: Koro Chen <koro.chen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/331160 Commit-Ready: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Milton Chiang <milton.chiang@mediatek.com> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
* pd: Compilation fixes for upcoming board designsShawn Nematbakhsh2016-03-082-3/+8
| | | | | | | | | | | | | | | | | - Send host commands to TCPCs based upon CONFIG_HOSTCMD_PD, since boards with off-the-shelf TCPCs will also have a PDCMD task. - Don't log VBUS voltage if we have no VBUS ADC channel. BUG=chrome-os-partner:50819 BRANCH=None TEST=`make buildall -j` with subsequent kevin board commit. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I33347402ec31e1754ad8e9a62814d5c1f345737d Reviewed-on: https://chromium-review.googlesource.com/331343 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: move utility method reverse() to common/util.cnagendra modadugu2016-03-071-0/+15
| | | | | | | | | | | | | | | | | reverse() swaps the endian-ness of a buffer of specified length. This change moves the implementation to a common location. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=compilation succeeds Change-Id: If8c97f53cc199d63c1caebbd999e1c099814387e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/331333 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* spi_flash: Reload watchdog after erasing each 32K blockShawn Nematbakhsh2016-03-021-0/+5
| | | | | | | | | | | | | | | | | A single erase host command may erase an arbitrarily large region of storage, which may lead to our watchdog firing. BUG=chrome-os-partner:50587 BRANCH=glados TEST=Manual on glados, flash RW EC / PD FW while plugging + unplugging zinger. Verify that watchdog doesn't fire. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I90dc85306aec43326c11c794861f68c6e12686e4 Reviewed-on: https://chromium-review.googlesource.com/329987 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Move host and console commands to new fileAnton Staaf2016-03-023-201/+216
| | | | | | | | | | | | | | | | | | | These commands, like other users of GPIOs should be able to use the public GPIO API, and thus do not need to be coupled directly to the GPIO common code. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manually verified console commands on discovery board Change-Id: I6e38b9d103590d4f7c72813a33437067716a858c Reviewed-on: https://chromium-review.googlesource.com/329992 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* oak: enable lid angle updateRong Chang2016-03-021-0/+7
| | | | | | | | | | | | | | | | | This change enables lid angle update that turns off keyboard scan in tablet mode. BRANCH=none BUG=chrome-os-partner:49114 TEST=make BOARD=oak runtests make BOARD=oak -j && make BOARD=oak_pd -j load on oak and boot to vt2 console. flip lid to disable range, type keyboard and check. Signed-off-by: Rong Chang <rongchang@chromium.org> Change-Id: Ibd2f0d6ae33a95380c9fc52a7568166a04c119e9 Reviewed-on: https://chromium-review.googlesource.com/328884 Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* oak: avoid reading BC1.2 interrupt reg during handling vbus eventBen Lok2016-03-011-8/+8
| | | | | | | | | | | | | | | | | | | | PI3USB9281 may not assert the interrupt line if device is detached and reading the interrupt register simultaneously. And it is not necessary to check the interrupt status when vbus change event happens. To prevent losing the detach interrupt during vbus change event happens, only check the interrupt status only if receiving the USB_CHG_EVENT_INTR event. BUG=chrome-os-partner:48797 BRANCH=none TEST=Plug/Unplug PD charger 20 times, UI should not display "Low power charger" warning message each time during the PD charger is unplugged. Change-Id: I51fe68732ece882029f1503294c2122cfbb00c34 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/328897 Reviewed-by: Shawn N <shawnn@chromium.org>
* oak: Add kx022 lid accelerometer for rev5.Ben Lok2016-03-011-1/+0
| | | | | | | | | | | | | | | | | | | | | | refer to commit 574c8065710432f5a91fd8dd11d1fa28e2be1f3b, adds the lid accelerometer to the list of motion sensors on the rev5. Since commit bc404c94b4ab1e6a62e607fd7ef034aa31d6388e, math_util.c is no longer to include "math.h" header file. BUG=chrome-os-partner:50312 BRANCH=none TEST=Build Oak EC with driver enabled and verify that valid accelerometer data is read, and that range, resolution, and odr can all be modified. TEST=Verified that signs of accelerometer data conform to those shown in the doc. TEST=make buildall tests Change-Id: I8df1b2331a1fbea82015b97985541e2ebc393d10 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/319332 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* common: console: Change console_init() string.Aseda Aboagye2016-02-231-0/+4
| | | | | | | | | | | | | | | | | | | | | For enhanced EC images, change the string telling the user that the console is enabled. This is such that EC-3PO can distinguish between non-enhanced ECs and enhanced ECs during EC boot. BUG=chromium:588611 BRANCH=None TEST=Build for chell with CONFIG_EXPERIMENTAL_CONSOLE and verify that the new string is printed. TEST=Repeat above test but without the config option and verify that the old string is printed. TEST=make -j buildall tests Change-Id: Ic8ed0a028ecb701b999fa6c6a376704f375dbc62 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/329161 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Don't source VBUS when forcing sink rolestabilize-7956.BShawn Nematbakhsh2016-02-231-0/+2
| | | | | | | | | | | | | | | | | | | | | When forcing a sink role (eg. on transition from S3->S5), make sure we're not sourcing VBUS. Otherwise, if a power source is attached, we will fail to charge from it, due to the inability to sink and source VBUS simultaneously. BUG=chrome-os-partner:49544 chrome-os-partner:50343 TEST=Boot chell, attach USB-C peripheral, then power down chell. Remove USB-C peripheral, attach zinger, and verify PD negotiation + charging succeeds. BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5fb9b0eb26e61daa93a167d6a3e9aaf4e4eeed39 Reviewed-on: https://chromium-review.googlesource.com/327727 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Remove gpio_alt_funcs table from common headerAnton Staaf2016-02-221-1/+32
| | | | | | | | | | | | | | | | | | | | Now that the cr50 no longer uses this array to store its pinmux config we can move it out of the header file, removing it from the public interface for GPIO code. This allows us to start modifying this struct more easily. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I9b4ca8b678b102bb9b63ccffe23bf2dc87aeb44a Reviewed-on: https://chromium-review.googlesource.com/328824 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: clock: Use full-speed 48MHz processor clock during EC bootShawn Nematbakhsh2016-02-091-1/+1
| | | | | | | | | | | | | | | | | | | EC boot / hash computing can be a bottleneck for system boot time. Reduce this bottleneck by running our processor at 48 MHz through boot, until vboot hashing of RW completes. BUG=chrome-os-partner:49583 TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and 'cbmem' delta between 'vboot select&load kernel' and 'finished EC verification' is reduced to ~250 ms (which includes sysjump time). BRANCH=glados Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326792 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charger: Settings for charger current in no battery conditionVijay Hiremath2016-02-081-1/+6
| | | | | | | | | | | | | | | | | | | | | In case of no battery condition, current code sets the charger input current to the charger maximum input current. To avoid damage to the board, set the charger input current to the maximum current that the board can support. BUG=none BRANCH=none TEST=Manually tested on kunimitsu, removed the battery & then using EC console command 'charger', verified that the current value is set to 3000mA. Change-Id: I94c40228a6362822c841a6e0c226bea0d3398b73 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/325522 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* fmap: note fmap_name dependencyMary Ruthven2016-02-081-0/+1
| | | | | | | | | | | | | | | | fmap_decode now checks the fmap name to determine if the fmap it is decoding is the correct one. This change puts a comment in the ec fmap header to note the use. BUG=none BRANCH=none TEST=make buildall -j CQ-DEPEND=CL:322262 Change-Id: Icdd56eef5474b51cb178b6ba37c530c2357341b2 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326450 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* CR50: Add initialization code required by TPM2 compliance tests.nagendra modadugu2016-02-051-0/+4
| | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:50115 TEST=initial TPM2 tests pass Change-Id: Ie614f29e578fb177245c33e6d1a896534a8d6095 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/326180 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Fix sleep mask for multi-port lock.stabilize-smaug-7897.BMulin Chao2016-02-041-8/+18
| | | | | | | | | | | | | | | | | | | This change use a simple counter to to prevent ec enter sleep if there's any i2c port active. Once there's no i2c port active, we enable sleep bit of i2c in i2c_lock() func. Please note FW disables interrupt during changing counter to prevent preemptive conditions. Modified sources: 1. common/i2c.c: Fix sleep mask for multi-port lock. BUG=crbug.com/537759 TEST=make buildall -j; test on wheatley when CONFIG_LOW_POWER_S0 is deifned. BRANCH=none Change-Id: I17c226108fee0e5d656fa157808179898f9a8dbf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/325256 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Fix signed vs unsigned typingShawn Nematbakhsh2016-02-031-1/+1
| | | | | | | | | | | | | | | | | | - ec_response_thermal_get_threshold.value is unsigned, so it can not be less than zero. - make power_button_wait_for_release() take a signed int, to match its existing usage. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5748df3d9904d1e417adc38fee18f8cb3ce9750 Reviewed-on: https://chromium-review.googlesource.com/325840 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Enforce compilation without system headersStefan Reinauer2016-02-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces HOST_CPPFLAGS to be used for all objects being compiled with HOSTCC rather then the target compiler. Since glibc is not linked into the EC, no glibc include files should be included in the EC code base. Hence, create local definitions for clock_t and wchar_t that match what the glibc include would have done, and remove some unneeded includes. Due to very eager optimization, we have to give gcc a little notch to not kick out memset. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:43025 BUG=chrome-os-partner:49517 BRANCH=none TEST=compile tested Change-Id: Idf3a2881fa8352756b0927b09c6a97473358f239 Reviewed-on: https://chromium-review.googlesource.com/322435 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* charger/Kunimitsu: Fix for boot from cut-off batteryVijay Hiremath2016-02-022-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery in cut-off mode wakes when voltage is applied to the PACK and takes approximately 2 to 3 seconds to initialize before capable of providing the power. Hence made the battery present status to BP_NO in case of cut-off mode. Once the battery is ready new status is updated as BP_YES. When the battery status changes from BP_NO to BP_YES, charger input current is set to board specific charger input current which is not sufficient to boot the AP hence the system reboots. To avoid this issue, added code to write charger manager negotiated current to charger input current when the battery status changes from BP_NO to BP_YES. BRANCH=none BUG=chrome-os-partner:49224 TEST=Manually tested on Kunimitsu. Used console command 'cutoff' to put the battery in cut-off mode. Inserted the adopter to wake the system, system doesn't reboot & the battery charges. Change-Id: Ia5a1457506b4bef0b3dd27993e4b60ae64c8f746 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322430 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Reinitialize state variables on TCPC resetShawn Nematbakhsh2016-02-021-2/+5
| | | | | | | | | | | | | | | | | Resetting our state to default without also resetting the power role may lead to a state / role mismatch. BUG=chrome-os-partner:49563 TEST=Verify kunimitsu correctly detects charger at either polarity on sysjump. BRANCH=glados Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I239df9793773429e9b84a847e55d6753577fab32 Reviewed-on: https://chromium-review.googlesource.com/325385 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driverEwout van Bekkum2016-01-282-0/+939
| | | | | | | | | | | | | | | | | | | | | Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ec: Add temporary secure storage for the host during bootDuncan Laurie2016-01-253-0/+131
| | | | | | | | | | | | | | | | | | | This adds a temporary secure storage interface for the EC to be able to store small amounts of data from the host that is locked until the chipset resets. This is used by pre-memory verified boot on x86 systems where we need to know which RW slot to boot and what the hash is to ensure that we can resume from S3 safely. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315222 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* vboot_hash: Properly handle hash of zero-byte regionShawn Nematbakhsh2016-01-202-2/+17
| | | | | | | | | | | | | | | | | | | | If we're asked to compute a hash of an image on a region of storage, we may find that the region actually contains no image. In that case, we need to compute a hash of zero bytes. Properly handle this case from image size detection to hash computation to hash invalidation. BUG=chrome-os-partner:49529 TEST=Manual on chell. `dd conv=notrunc if=/dev/zero of=ec.bin bs=131072 count=1`, then write ec.bin and verify SW sync occurs, RW hash is computed correctly, and the system boots into dev mode. BRANCH=glados, strago Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5a023d13d2521f9c224615666950aea8fbc22bb Reviewed-on: https://chromium-review.googlesource.com/322750 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Simplify configurationAnton Staaf2016-01-202-22/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously there were only two uses of gpio_config_pins, one was gpio_config_module, which passed in GPIO_CONFIG_ALL_PORTS (the only place this is used), the other was the common I2C code when it needs to return the SDA and SCL lines to their alternate function after unwedging the bus. These uses are so different that it doesn't make much sense to keep a single API for them. This change adds a gpio_config_pin that is simpler to use as it just takes a gpio_signal enum to select the GPIO to configure and makes gpio_config_pins and GPIO_CONFIG_ALL_PORTS internal to gpio.c Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I92bfb0b520b0aa2165655b2ff5076e428c88631f Reviewed-on: https://chromium-review.googlesource.com/322437 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* I2C: Remove raw mode mutexAnton Staaf2016-01-191-12/+0
| | | | | | | | | | | | | | | | | The raw mode mutex is no longer needed as the return to I2C mode is now done per pin, and not for the entire I2C module. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ibe9b1acb8bf89cadb3f3a3ab4c70dc06969f48b0 Reviewed-on: https://chromium-review.googlesource.com/321458 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Add gpio_reset functionAnton Staaf2016-01-191-0/+8
| | | | | | | | | | | | | | | | | The gpio_reset function returns a GPIO to its initialy configured state. Using it removes a few more uses of gpio_list. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie24e8e8a96d0ff50f521a918e80ed2b379f8c1a9 Reviewed-on: https://chromium-review.googlesource.com/321951 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* vboot_hash: Save stack space when checking image sizestabilize-7834.66.Brelease-R49-7834.BShawn Nematbakhsh2016-01-151-1/+5
| | | | | | | | | | | | | | | | | Use a static buffer rather than 256 bytes of stack when scanning for the end of an image. BUG=chrome-os-partner:49396 TEST=Verify "ectool echash abort; ectool echash start 0xfffffffe 100" doesn't panic on glados. BRANCH=glados Change-Id: Ia864fe77134533bce079dab3b253142b14410ded Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322283 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* pd: Add common EC_HOST_EVENT_PD_MCU implementationShawn Nematbakhsh2016-01-072-6/+34
| | | | | | | | | | | | | | | | | | | | | For TCPMs with an off chip TCPC, PD MCU host event status can be handled in a common way. When a status flag is updated (ex. from charge_manager), notify the AP through the host event, and save the status flag for later retrieval. BUG=chrome-os-partner:49124 BRANCH=None TEST=Verify `cat /sys/class/power_supply/CROS_USB_PD_CHARGER1/online` on chell reflects the actual online status of the charger. Also verify UI charge icon tracks the online status correctly. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I63bc70205627474590e38ffd282faedaea3bcc66 Reviewed-on: https://chromium-review.googlesource.com/320796 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* charger: Change unlocked battery level ignore conditionsShawn Nematbakhsh2016-01-064-21/+25
| | | | | | | | | | | | | | | | | | | | | | | | x86 systems will auto-power-on when power is applied to the EC. When the battery level is critically low, power-on is prevented, except when the system is unlocked. So, when unlocked, some systems will auto-power-on regardless of battery level, overcurrent the charger / battery, and then repeat forever. Prevent this reboot loop by ignoring auto-power-up when the battery is critically low, regardless of system unlocked status. BUG=chrome-os-partner:48339 TEST=Verify power-up is prevented on no-battery chell w/ donette. Then, run 'powerbtn' on EC console and verify system powers on (and overcurrents). BRANCH=None Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319187 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* vboot_hash: check the current hash is for the right regionMary Ruthven2016-01-051-4/+19
| | | | | | | | | | | | | | | | | | | | | With the RO region being added to software sync, up to two hashes will be requested during boot. Currently if vboot_hash has a valid hash when the EC gets an EC_VBOOT_HASH_GET host command then it will return that hash. When the EC gets a request for the RO hash after it has calculated the RW hash it returns the RW hash in the response. This change will add a check that the EC not only has a valid hash, but that it is for the correct region. BRANCH=none BUG=none TEST=Try to get the RO and RW hashes from depthcharge and make sure they match the values gotten using ectool Change-Id: I2449c8d79b4a74f4865dd1234fb253bcdac66a31 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/318861 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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