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* led_policy_std: turn off power led when system shutdownstabilize-9460.60.Bstabilize-9460.40.Bstabilize-9460.4.Bstabilize-9460.23.Bjames_chao2017-04-131-0/+8
| | | | | | | | | | | | | | | | | | The led is control by HOOK_SECOND, but if dut press ALT+VOL_UP+H, enter hibernate mode when system in s0, there is no one second to turn off the power led, so the power led is still on when system enter hibernate. BUG=b:36328757 BRANCH=gru TEST=press ALT+VOL UP+H, the power led turn off and system enter hibernate mode. Change-Id: I72d18876aa5468131bae7ad42203982d123db8ba Signed-off-by: james_chao <james_chao@asus.com> Reviewed-on: https://chromium-review.googlesource.com/476850 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tcpm: anx74xx: Improvements to low power mode for S3/G3 chipset stateScott2017-04-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before entering standby mode, bit 7 (cable_det) or analog_ctrl_0 is cleared. This allows a new cable detect event to trigger the EC to put the ANX4329 into normal mode. However, in some cases such as when in S3/S5/G3 chipset power states a port will be in sink only mode and therefore won't attach when a sink only adapter is connected to the port. This results in the an indefinite toggle of standby<->normal mode transitions. This constant toggle floods the EC console and more importantly prevents the ANX4329 from remaining in standby mode and the power consumption remains at ~9.5 mW instead of ~1.2 mW when no adapter is connected. This CL adds logic around clearing the cable_det bit so that it's only cleared if both CC lines are open or if an Emark cable is attached. Emark cable is determined from the presence of Ra on one CC line and no Rd on the other CC line. The special consideration for an Emark cable is reqiured because when an Emark cable is connected, the USB PD auto toggle state may require some number of iterations until the attach event is recognized. In order to support handle cases where the drp mode is changed via either the EC console command or host command, added a call to tcpm_set_drp_toggle whenever the drp state is updated. Since the drp mode is updated upon chipset resume events, the chipset resume hook in board.c for anx74xx_cable_det_handler() became redundant and hence it was removed. BUG=b:35775019,b:35586188 BRANCH=reef TEST=Tested the following cases: - Sink, source adapters in chipset S0. Verified that adapters connected as expected. Also, used Emark cable to connect to both USB PD chargers (source) and Pixel phone (sink). - Run 'lidclose' on EC console then connect Type C -> A adatper [3490.370125 TCPC p0 reset!] [3490.389588 TCPC p0 Low Power Mode] It no longer toggles indefintely and after running 'lidopen' verified that port 0 is now in SRC_DISCOVERY. - In S3/G3 connected USB PD charger with regular and Emark typeC cable. Verified that port 0 is in SNK_READY state. - use 'pd dualrole sink' and test with Type C -> A adatper. Verified that tcpc wakes up, but goes into standby mode until entering 'pd dualrole on'. - When sink only adapter is connected in S3/G3, measure power level ~1.2 mW as opposed to ~10 mW in S0. - Repeated similar tests on port 1 (parade tcpc) to verify that adapters connected as expected. Change-Id: Ib8de666f72723934186fee7869f9dda01381c7a8 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/463991 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: S Wang <swang@analogix.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rwsig: Make it possible to run as a taskNicolas Boichat2017-04-112-18/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Optionally) split rwsig verification into a separate task. This allows us to initialize other components (e.g. USB) while the verification is in progress, speeding up the boot process to active USB in RO case. After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section if no action is taken by the AP (such as a forced request to jump to RW, or starting an update). Note: This comes with a ~36ms boot time regression, as other code gets to run before verification starts. BRANCH=none BUG=b:35587171 TEST=Flash, board boots to RW after 1s TEST=Change jump timeout to 5s, add 5s delay in check_signature, add console command to manually abort/continue rwsig verification. 'rwsig continue' works => Board jumps to RW after check_signature is completed (or immediately while waiting for timeout) 'rwsig abort' works => Board does not jump to RW. Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef Reviewed-on: https://chromium-review.googlesource.com/468709 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-115-4/+5
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rollback: Update and lock rollback block as part of rwsig verificationNicolas Boichat2017-04-112-8/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done at RO stage. If the rollback region is unprotected, update it to match the version in the RW image. If the rollback region is protected, we can't do that update, so we wait for RW to unlock that region (presumably after AP has verified that image is somewhat functional) before updating it. BRANCH=none BUG=b:35586219 TEST=flashwp true; reboot => hammer reboots twice flashinfo shows RO+rollback protected: Flags: wp_gpio_asserted ro_at_boot ro_now rollback_at_boot rollback_now Protected now: YYYYYYYY YYYYYYYY Y....... ........ TEST=Hack version.c to add "+1" to rollback_version, check that RO updates ROLLBACK info block on first boot. TEST=Use hack above, convert rwsig to separate task, add 5000 ms delay in rwsig just before rollback information is updated. Then: Quickly type: flashwp true; reboot; flashwp all; reboot => Wait for system to jump to RW rollbackinfo => minimum version 0 flashwp norb; reboot; wait for jump to RW rollbackinfo => minimum version 1 Change-Id: I78e502315c611c5edaf34b8d70a12fedd3e57bdf Reviewed-on: https://chromium-review.googlesource.com/452816 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: Added dts_mode on/off control for DUT port connectionScott2017-04-071-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added a new static variable disable_dts_mode. By default, DUT port will attempt to connect as a DTS source. However, if disable_dts_mode is set via a console command, the DUT port will connect as a regular source device. Charging behavior is identical between the two modes. In DTS mode, Rp is presented on both CC lines. When it's disabled Rp is presented only on CC1. Added tables to support the appropriate VNC and RD voltage thresholds. BUG=b:36908939 BRANCH=servo TEST=Tested with new console command 'dts on|off'. If new mode equals the current mode, no action is taken. If the mode is different, then verified that DUT port connects as DTS following 'dts on' and regular SRC following 'dts off'. Verifed this when the command is issued when connected to the DUT or disconnected. Validated that the H1 console is present for DTS mode and not present when DTS mode is disabled. Change-Id: Ie649709d6b2bbe947708d05eac42fde61d2677a8 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/468447 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Fixups in emulated sysrq codeNicolas Boichat2017-04-062-2/+2
| | | | | | | | | | | | | | | | Follow-up to CL:456520, addressing a few more comments. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I692afa7c911882f00d92b8e6d83889c52821e171 Reviewed-on: https://chromium-review.googlesource.com/468506 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: prefer CD pin assignments over EF for USBC->USBC case.Todd Broch2017-04-061-5/+8
| | | | | | | | | | | | | BRANCH=samus,glados,oak,gru,reef BUG=chromium:694597 TEST=manual, connect samus to USB-C monitor via cable and see it select pin assigmnent 'C' Change-Id: Iddad5b654715bd30ba081c62f8fb53e07816498c Reviewed-on: https://chromium-review.googlesource.com/465379 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-068-2/+256
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add support for emulated sysrqNicolas Boichat2017-03-312-0/+35
| | | | | | | | | | | | | | | | | | | | On keyboard-less design, we will implement a special debug mode, based on button sequences, to transmit sysrq events to the AP. This implements the new MKBP event to send sysrq, and a console command to test it. Later CL will implement debug mode itself. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I71d3f77497baf8cc7fac65cd040ce20513b507bc Reviewed-on: https://chromium-review.googlesource.com/456520 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chg_ramp: Don't change ICL until vals are init'd.Aseda Aboagye2017-03-301-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When the charge ramp task starts, it starts up in the DISCONNECTED state. From this state, it's possible to set the input current limit to 0 mA. However, upon task start, we shouldn't take any action until we have valid values from a new charge supplier or a supplier leaving. This commit changes the charge ramp task to not touch the input current limit until the charge ramp state changes or the desired input current changes at least once. BUG=b:36468002 BRANCH=gru,master TEST=Flash kevin EC RW or build AP FW that contains the fix that will by sync'd by EC SW sync. Make sure WP is asserted to prevent PD communications in RO. Unplug battery. Plug in AC, verify that system can boot up to UI on AC alone. TEST=make -j buildall Change-Id: I351917bce7902c49d1bb842a0cc83dd161d75b6f Reviewed-on: https://chromium-review.googlesource.com/461382 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/463927 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* servo_v4: Set desired data role for DUT port to UFPScott2017-03-261-0/+2
| | | | | | | | | | | | | | | | | | The default for servo_v4 DUT port is to be SRC to charge the DUT, but a UFP data role so that the DUT's usb mux gets connected. BUG=b:35586526 BRANCH=servo TEST=Connect to Electro and verify that servo_v4 data role is that of UFP and that electro is getting an IP address from the enet port on servo_v4. Change-Id: I8f2e4242777bf879598852004096f683d68c091c Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/452725 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: pd: Updated CC_NC and CC_RA macrosScott2017-03-261-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previous boards that implemented tcpc layer on chip didn't support variable Rp values. However, servo_v4 can present any of the 3 possible Rp values and therefore the voltage thresholds that are used to determine a no-connect or Ra attach status need a way to be set based on the Rp value that's current attached to a given CC line. - Added port and cc line selection to both the CC_NC and CC_RA macros and now check if they are already defined before being defined in usb_pd_tcpc.c. - Defined each of these macros in board.h to use a function that's able to select the threshold based on the current Rp configuration. BUG=b:35586526 BRANCH=servo TEST=Tested with servo_v4 against Electro and verified that it connects when a charger is and is not connected to CHG port which exercises the differnt Rp combinations that servo_v4 presents. Change-Id: I1a31e430c0f290486f0fa8a50bdafdddf20d23ca Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/451962 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* flash: ensure proper pstate alignmentVincent Palatin2017-03-241-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The pstate structure is written using the low-level flash_physical_write() function. As a consequence, it is supposed to meet the CONFIG_FLASH_WRITE_SIZE alignment constraint. Add a build-time assertion to avoid silent failures. Slightly decrease the maximum size of the serial number string, so the structure has a natural 32-byte alignment which is compatible with a large number of platforms (including STM32L4 which requires 64-bit alignment). Of course, this change is not fully backward-compatible. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:571477 b:35648258 TEST=on STM32L442, build and run 'flashrom --wp-enable' without failure. Change-Id: Ia8f82790a61a6c7d2cf9bfeb95bfdaf7b8c52d11 Reviewed-on: https://chromium-review.googlesource.com/458201 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cr50: add vendor command to restore corrupted headerVadim Bendebury2017-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upcoming move of the Cr50 firmware update to the background requires postponing the activation of the newly uploaded Cr50 image to a later point in time, when the AP is ready to switch to start using the new Cr50 image. The suggested way of achieving it is as follows: when downloading the new image, the current Cr50 code modifies the header's 'image_size' field, setting its top bit to 1. This both makes the size invalid and guarantees that the new image would not verify on the following Cr50 restarts. When the AP is ready to switch to running the new Cr50 image, it will send a vendor command, which would trigger the currently running Cr50 image to restore the other image's size field. This vendor command would also communicate the timeout for the Cr50 to wait before rebooting, if there has been at least one header (ro or rw) restored. Rebooting the Cr50 would trigger rebooting the AP, resulting in the entire system running the updated firmware. Response sent to the AP will indicate if there has been a header restored and the reboot is indeed upcoming, this would allow the AP to quiesce the state of the device to handle the reboot gracefully. BRANCH=cr50 BUG=b:35580805 TEST=with the rest of the patches applied observed the system properly after the new header version was restored. Change-Id: Ia1edee67b6aa8f458810d5dc2931477cfaab1566 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/457676 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* console: ensure "Console is enabled" string is intactphilipchen2017-03-201-0/+2
| | | | | | | | | | | | | BUG=chromium:687228 BRANCH=none TEST=boot 10 times on kevin, and see the complete string "Console is enabled..." Change-Id: I9bb7358eb0a3d8172b5584329b9837cf62def635 Reviewed-on: https://chromium-review.googlesource.com/457421 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* motion_lid: no angle correction when lid closephilipchen2017-03-171-2/+5
| | | | | | | | | | | | | | | | | | | | BUG=b:36107214 BRANCH=gru TEST=manually on kevin: (1) make DUT in tablet mode (2) swiftly close the lid (3) check ec log and confirm DUT can read small angle and turn into clamshell mode when lid is closed. TEST=make runtests Change-Id: I7ebf10d38a8b300960ebf46be717d48522c6fd0b Reviewed-on: https://chromium-review.googlesource.com/455458 Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 75ba9147c392367037c21e79899f463c32c1f92f) Reviewed-on: https://chromium-review.googlesource.com/457137 Commit-Ready: Philip Chen <philipchen@chromium.org>
* tcpm: Call usb_mux board_init on exit from low power modeDaisuke Nojiri2017-03-161-1/+8
| | | | | | | | | | | | | | | | | PS8751 does not restore all register contents when resuming from low power mode. This change makes tcpm call board_init when it stops auto-toggling so that register contents can be restored. BUG=b:35585399 BRACH=none TEST=On Snappy, the board_init funciton is called every time a device is plugged in and register contents are restored. Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/454139 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb: Cleanup headersNicolas Boichat2017-03-161-0/+2
| | | | | | | | | | | | | | | | | | | Let's split the usb headers in 3 different parts, instead of having usb_descriptor.h pull in usb_hw.h and usb_api.h. - usb_api.h: EC functions related to usb (e.g. connect/disconnect) - usb_descriptor.h: common USB names and structures - usb_hw.h: Functions required for interactive with EC's USB HW BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e Reviewed-on: https://chromium-review.googlesource.com/454861 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Use stored size in image_data for determining image_usedShawn Nematbakhsh2017-03-161-62/+23
| | | | | | | | | | | | | | | | | | Image used size is now part of the image_data struct present in all images at a fixed offset, so use it rather than scanning from the end of the image. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns the same value as the old implementation, for both RO and RW images. BRANCH=None Change-Id: I35f0aa87f5ab1371dbd8b132f22b9d0044358223 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450859 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* version: Store image size data in version structShawn Nematbakhsh2017-03-164-24/+26
| | | | | | | | | | | | | | | | | | | | | Store our image size (known at build time) in our version struct (now renamed to image_data). This will allow us to more efficiently determine the size of an image in a follow-up CL. Note that compatibility is broken for old ROs that do not include this CL. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that stored image size matches output of system_get_image_used() for both RO and RW images. BRANCH=None Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450858 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Changes to USB PD state machine for SRC DTS modeScott2017-03-131-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to make pass through charging safe, there must be a mechanism to signal the CHG port manager that Vbus is available and in a steady state. When a typec only charger is used for the CHG port, then it's steady state is SRC_DISCOVERY. Need a way to differentiate the TypeC only charger from a USB PD charger that's also going through SNK_DISCOVERY. In addition, to allow a DTS device to support PD messaging, can't stay in SRC_ACCESSORY state. This CL makes a modification to the USB PD state machine so that if a debug accessory is detected and CONFIG_USB_PD_DTS is defined, then the state machine will advance to SRC_STARTUP and prepare for messages similar to when a UFP attach is detected. BUG=b:35586526 BRANCH=servo TEST=Manual Built for both Plankton and Reef, verified that Reef connects as both SNK and SRC. Change-Id: I9aea0341cd9b6e6773023f0923a9a18a86fc4627 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448987 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: add feature bit for fingerprint supportVincent Palatin2017-03-131-0/+3
| | | | | | | | | | | | | | | | Add a new 'feature' bit to allow the host to auto-detect a FP MCU. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=manual, on Eve, look at the features bit on the kernel interface. Change-Id: If21320bb29d58f0a6dfadba03d8892e4183e5430 Reviewed-on: https://chromium-review.googlesource.com/452341 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Ensure print_build_string() prints short strings properly.Carl Hamilton2017-03-081-1/+1
| | | | | | | | | | | | | | | | | Pass "full_build_string" to ccprintf() as expected. I believe that this code only worked previosly due to blind luck; the compiler allocated "full_build_string" on the stack in such a way that it was available at the end of the call frame for ccprintf(). BUG=none BRANCH=none TEST=make -j buildall Change-Id: Ib307547a4c4d6300ccf018b33aee4db7a4f364f8 Reviewed-on: https://chromium-review.googlesource.com/451084 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* pdcontrol: Suspend port individuallyDaisuke Nojiri2017-03-071-62/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pdcontrol suspend command will be used to prevent tcpm from putting the chip into sleep while firmware update is taking place. Currently the command suspends or resumes port 0. This patch makes the command apply to ports individually. pd enable console command now takes a port number: pd <port> enable/disable. This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED. When it's defined, PD communication is disabled at startup. Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to disable PD communication at startup. Therefore, this patch defines CONFIG_USB_PD_COMM_DISABLED in its board.h. BUG=b:35586859 BRANCH=none TEST=From AP console: localhost # /tmp/ectool pdcontrol suspend 1 [600.188013 TCPC p1 suspended!] > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020 localhost # /tmp/ectool pdcontrol resume 1 [678.516613 TCPC p1 resumed!] > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 From ec console: > pd 1 disable Port C1 disable > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 > pd 1 enable Port C1 enabled > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447968 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add option to adjust compiler optimization on RSAVincent Palatin2017-03-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Using -O3 optimization level rather than -Os results in a large speed-up for a minor code size increase for the RSA code with our current GCC toolchain. Add the CONFIG_RSA_OPTIMIZED option to do it on platforms which are not too size-constrained. On cortex-M4 based STM32L432, I'm measuring a 37 to 40% speed increase (depending on CPU frequency) for a 200 bytes code size delta. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manual: benchmark RSA2048 with F4 exponent on STM32L432: -Os -O3 @16Mhz 185163 us --> 111942 us @80Mhz 39286 us --> 24582 us Change-Id: I8c2e4b757f037f4f645fb73ba0faaaa471b24896 Reviewed-on: https://chromium-review.googlesource.com/445218 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* charger: Add state for discharge + fullDaisuke Nojiri2017-03-031-1/+6
| | | | | | | | | | | | | | | | | | When battery is fully charged, Reef starts discharging to protect battery and starts charging again when charge level goes down around 95%. To prevent the battery LED from showing blue with the charger plugged in, this patch adds a new state for discharge + nearly full. Reef shows a color indicating battery is full if an external charger is present. BUG=b:35775017 BRANCH=none TEST=Fully charge Electro. Plug in OEM charger. LED lights blue. Change-Id: I4c7c62f2c51c1d39188d1b271331984e89d5d7a3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448961 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* switch: Initialize switch state earlier during HOOK_INITShawn Nematbakhsh2017-03-022-1/+6
| | | | | | | | | | | | | | | | | | | | The host may ask for our switch state at any time, so do initialization immediately after lid + power button are initialized. BUG=chrome-os-partner:63073 BRANCH=gru TEST=On kevin, verify system boots when EC reset is triggered with lid open. Verify lid close and power button press still succeed to power-down from dev screen. Change-Id: I8e37c02ef4f4d2d7c06beb383cdbda8eea67bc5c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444322 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 106d33cd3a8e4f3356950a3b2b92ea587977b4e7) Reviewed-on: https://chromium-review.googlesource.com/445276 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* pd: Add tcpc_select_rp_value to stub tcpm driverScott2017-03-021-0/+10
| | | | | | | | | | | | | | | | | | | | | | The function tcpm_select_rp_value() is used to set a given Rp value. This function was not supported for boards that use the config option CONFIG_USB_PD_TCPC. This CL adds a weak board_ function which can be overloaded for boards that have the requirement to set Rp to different values. BUG=chrome-os-partner:61878 BRANCH=servo TEST=run 'make buildall'. On plankton added a console command to trigger a call to tcpm_select_rp_value(0, 0), verified that it returned 2 (EC_ERROR_NOT_IMPLEMENTED). Then added board_select_rp_value() to plankton's board.c and verified that it returned 0. Change-Id: I1cd6f0ed51717736d30575c58025bd9a1c5d6fc4 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446685 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Store console lock state in NvMem vars.Aseda Aboagye2017-02-272-1/+79
| | | | | | | | | | | | | | | | | | | | | | This commit enables the use of the nvmem vars module. The console lock state is migrated from using the long life scratch register, to nvmem vars instead which will persist across power on reboots. BUG=b:35586145 BRANCH=None TEST=Flash a dev image. Lock the console. Remove all power from the system. Power on system and verify that console is still locked. Unlock the console, remove power from the system, power on the system, verify that the console is now unlocked. TEST=Repeat the above test, but using the nvtestvar console command instead. Change-Id: I03a2098bb0017cfca59889457a332eafb0e95db6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/445804 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* hostcmd: Remove EC_CMD_VBNV_CONTEXT handler for most boardsShawn Nematbakhsh2017-02-251-7/+3
| | | | | | | | | | | | | | | | | Most boards do not keep VBNV storage on the EC, so leave out the host command handler by default. BUG=chromium:693210 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia202ec7d73d1804d8430fe7516cc783afd86e89a Reviewed-on: https://chromium-review.googlesource.com/446716 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* flash: Add ROLLBACK flash region, that can be protected separatelyNicolas Boichat2017-02-251-6/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ROLLBACK region will be used to store rollback information, and can be protected independently of RW (it can only be protected when RO is protected, though). This is only supported on stm32f0 currently. BRANCH=none BUG=chrome-os-partner:61671 TEST=on hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW+RB protected flashwp noall; reboot => only RO protected flashwp rw; reboot => only RO+RW protected flashwp rb; reboot => RO+RW+RB protected flashwp norb; reboot => RO+RW protected flashwp all; reboot => RO+RW+RB protected flashwp norw; reboot => RO+RB protected TEST=on reef, rb/norb commands not available Change-Id: I45ffc66d91cf3699ecff025e5114c59a73dc8274 Reviewed-on: https://chromium-review.googlesource.com/430519 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-241-4/+9
| | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash: Add EC_FLASH_PROTECT_RW_[AT_BOOT|NOW] flagsstabilize-9313.BNicolas Boichat2017-02-231-15/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea of this flag is to be able to protect/unprotect only the RW portion of the flash. In the (usual) case where ALL=RO+RW, with no other region, this makes no difference compared to the existing EC_FLASH_PROTECT_ALL_* flag, and this flag may not be supported. This is necessary for futher work, where a ROLLBACK region is added, so that RW/ROLLBACK can be protected/unprotected individually. Only support for stm32f0 is added, as this is the target for hammer. BRANCH=none BUG=chrome-os-partner:61671 TEST=build and flash hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW protected flashwp noall; reboot => only RO protected flashwp rw/norw not available TEST=enable CONFIG_FLASH_PROTECT_RW build and flash hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW protected flashwp noall; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=build and flash reef (npcx) flashinfo => RO+RW not protected flashwp true => RO protected flashwp all; flashinfo => all_now displayed reboot => RO protected flashwp rw/norw not available Change-Id: Ica6f499cf2e8a9345b08ef52c915655a983ffe3c Reviewed-on: https://chromium-review.googlesource.com/442265 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/flash.c: Remove redundant codeNicolas Boichat2017-02-231-10/+8
| | | | | | | | | | | | | | | | | | | | | Saves a little bit of flash size: Compared 167 of 167 files. 77 files changed. Total size change: -3240 bytes. Average size change: -42 bytes. BRANCH=none BUG=chrome-os-partner:61671 TEST=make buildall -j TEST=hammer: 'flashwp true' works as expected TEST=hammer+CONFIG_FLASH_PSTATE_BANK: 'flashwp true' still works TEST=reef: 'flashwp now' sets all_now flag in flashinfo Change-Id: Ic2fe8f0c67520afea276369fdf8c59e75e95208e Reviewed-on: https://chromium-review.googlesource.com/444488 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* curve25519: strip-down, build and testVincent Palatin2017-02-232-4087/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keep only the most compact version of the curve25519 code and remove the remaining unused code for easier compilation. Do the minimal changes to make it compile in the EC code base, there should be no real functional changes. Re-use the wording from BoringSSL include/openssl/curve25519.h for the header. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62991 TEST=run x25519 on host (ie 'make run-x25519') and the STM32L4 target: make BOARD=eve_fp PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=eve_fp --image=build/eve_fp/x25519.bin execute 'runtest' in the console. Change-Id: I13dbe453eff39b461effb1b3ffa549afc1749fef Reviewed-on: https://chromium-review.googlesource.com/444187 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Adam Langley <agl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* util: add constant-time memcmpVincent Palatin2017-02-231-0/+19
| | | | | | | | | | | | | | | | | Import from vboot_reference the constant-time memcmp implementation for safer usage in cryptography code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62991 TEST=run curve25519 test Change-Id: I9c4c61e15912c978e13b6cc002af879c8ae8f630 Reviewed-on: https://chromium-review.googlesource.com/446098 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* import curve25519 code from BoringSSLVincent Palatin2017-02-231-0/+4937
| | | | | | | | | | | | | | | | | | | | | | | | | | Import the implementation of the curve25519 public key cryptography from BoringSSL. It's the unmodified crypto/curve25519/curve25519.c file from the repository at sha c034e2d3ce16df5f89134515bc113eb4f3a28e0e. (current HEAD of chromium-stable branch) It will be used as a primitive to implement a Diffie-Hellman exchange. The test code in test/x25519.c is also imported unmodified from BoringSSL crypto/curve25519/x25519_test.cc. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62991 TEST=with follow-up CLs, run curve25519 test vectors on host, MEC1322 and STM32 targets. Change-Id: Ie497f78249f505e32d8e025b0537e82bf4476298 Reviewed-on: https://chromium-review.googlesource.com/444186 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Make sure TPM wipe only clears TPM data.Aseda Aboagye2017-02-232-12/+19
| | | | | | | | | | | | | | | | | | | | Previously, wiping the TPM would wipe all of NvMem, however, it really should only clear the TPM's NvMem space. This commit adds a function to clear a given NvMem user's space and makes the TPM only clear its space. BUG=chrome-os-partner:61597 BRANCH=None TEST=Add code for using nvmem vars, create a test variable, add a user to snappy, unlock the console, verify that the user is no longer present on the system and the test nvmem var still exists. TEST=make -j buildall Change-Id: Ic98baa5166a1ef9ae76e910b1b9ab100300e947f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/445803 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nvmem: do not prefer old partition over new one.Vadim Bendebury2017-02-221-16/+15
| | | | | | | | | | | | | | | | | | | | | | | | The code deciding which partition to choose properly determines which one is newer, but invariably populates the cache with the second one, when both partitions are valid. This is obviously wrong, on top of that there is no need to check both partitions' validity, if the newer one checks out. BRANCH=none BUG=chrome-os-partner:60555, chrome-os-partner:61972 BUG=chrome-os-partner:61716, chrome-os-partner:61234 BUG=chrome-os-partner:61167, chrome-os-partner:60555 TEST=successfully ran $ ssh 192.168.1.102 suspend_stress_test --suspend_min 10 \ --suspend_max 10 --wake_max 10 --wake_min 10 for more than 300 cycles (it still is going) Change-Id: I02d9bb062b9edbbb9787a95ba760872e09ff2761 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/445356 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Benson Leung <bleung@chromium.org>
* mkbp: Support devices having buttons but no keyboardPhilip Chen2017-02-211-1/+4
| | | | | | | | | | | | | | | | | | | If we turn on CONFIG_KEYBOARD_PROTOCOL_MKBP on devices without keyscan task, we'll see a few compile errors due to dependencies on keyscan. This is the fix. BUG=chrome-os-partner:62987 BRANCH=none TEST=make buildall -j Change-Id: Ib0dd1570f0e1a2de084cf1c5f75b8e3ad1cb301a Reviewed-on: https://chromium-review.googlesource.com/443745 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444946 Commit-Ready: Philip Chen <philipchen@chromium.org>
* g: extension: Add a whitelist for vendor commands.Aseda Aboagye2017-02-182-9/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB FW upgrade endpoint should really only accept vendor commands required to perform the firmware update. This commit adds a whitelist that is checked whenever a vendor command is received over this endpoint. The allowed commands over USB are the following: - EXTENSION_POST_RESET - VENDOR_CC_IMMEDIATE_RESET (only for dev images) There is also functionality to have a whitelist for vendor commands that come over the TPM interface. BUG=chrome-os-partner:62815 BRANCH=None TEST=Flash Cr50 with image containing this change. Verify that an upgrade over USB to newer image works. TEST=Try using usb_updater to send a vendor command that's not in the whitelist. Verify that the vendor command is dropped. Change-Id: I71f8ba090a1cc6c9e7c30ce0dd3c25259e8f292f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/443447 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Decrement retry counter on manual reboots.Aseda Aboagye2017-02-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, manually triggered reboots cause the retry counter to be incremented. However, if the system is responsive enough to process the reboot commands from either the console or TPM vendor command, we can assume that the image is "ok". This commit changes the Cr50 behaviour to decrement the retry counter when a reboot is issued on the console or the TPM vendor command is received. BUG=chrome-os-partner:62687 BRANCH=None TEST=Flash cr50. Flash an older image in the other slot. Enter the reboot command on the console over 10 times and verify that retry counter never exceeds RW_BOOT_MAX_RETRY_COUNT and older image is never executed. CQ-DEPEND=CL:444264 Change-Id: Ic35bdc63c4141834584a00a7ecceab2abe8dfc21 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/443330 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Move chip/g-specific system() prototypes to system_chip.hShawn Nematbakhsh2017-02-181-0/+1
| | | | | | | | | | | | | BUG=chromium:693148 BRANCH=None TEST=`make buildall -j` Change-Id: I7a758e6b5a04721d0422cfe8b767d85abddb1ad2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444264 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/flash.c: Rename flashwp parameter from [no]rw to [no]allNicolas Boichat2017-02-171-3/+3
| | | | | | | | | | | | | | | | | | | | | Saying that 'flashwp rw' was protecting RW region was not really accurate: it was actually protecting the whole flash (which, well, is actually equivalent as the RW can't be protected without the RO). Let's fix that in anticipation for adding a new flag that will _really_ set the RW protection (and only that). BRANCH=none BUG=chrome-os-partner:61671 TEST=make buildall -j Change-Id: Ic1c585622330b4976e71150f3a71b74a031a7694 Reviewed-on: https://chromium-review.googlesource.com/442264 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* rwsig: Add support for rwsig image typesNicolas Boichat2017-02-174-11/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usbpd1 futility image type is deprecated and should not be used for new designs. This adds proper support for rwsig image type. Key and signatures are added at linker stage step (futility cannot directly create such signed images). Thanks to VB21 header, rwsig.c can now tell how many bytes of the RW image need to be cryptographically verified, and ensure that the rest is blank (0xff). BRANCH=none BUG=chromium:690773 TEST=make BOARD=hammer; flash, RW image is verified correctly. TEST=make runtests -j TEST=For the rest of the tests: Change config option to CONFIG_RWSIG_TYPE_RWSIG TEST=make BOARD=hammer; flash, hammer still verifies correctly. TEST=cp build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig; futility sign --type rwsig --prikey build/hammer/key.vbprik2 \ build/hammer/ec.RW.bin diff build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig => Same file TEST=Add CONFIG_CMD_FLASH, flashwrite 0x1e000, reboot, EC does not verify anymore. TEST=dump_fmap build/hammer/ec.bin shows KEY_RO and SIG_RW at correct locations. Change-Id: I50ec828284c2d1eca67fa8cbddaf6f3b06606c82 Reviewed-on: https://chromium-review.googlesource.com/441546 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* motion: Add opt3001 as a motion sensorGwendal Grignou2017-02-161-5/+11
| | | | | | | | | | | | | | | | | | Use the motion sensor to manage ALS as well. The current interface (via memmap) is preserved, but we can also access the sensor via cros ec sensor stack and send the ALS information to ARC++. BUG=chrome-os-partner:59423 BRANCH=reef CQ-DEPEND=CL:424217 TEST=Check the sensor is working via ACPI sensor and cros ec sensor. Check ARC++ sees the sensors. Change-Id: Iaf608370454ad582691b72b471ea87b511863a78 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424323 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* builtin: Expands string.h / stdint.hNadim Taha2017-02-171-0/+56
| | | | | | | | | | | | | | Declares UINT8_MAX, INT8_MAX and defines strnlen(), strncpy(), strncmp() & memchr(). Needed by a module I'm integrating into cr51. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I894b0297216df1b945b36fc77cd3bc5c4ef8aa2b Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/436786 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pdchipinfo: Add option to force renewalDaisuke Nojiri2017-02-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This change adds an option to pdchipinfo command to force ec to get the version from the chip instead of the cache (if it's available). This option will be used after firmware update, which makes the cache value stale. BUG=chrome-os-partner:62383 BRANCH=none TEST=Run ectool as follows: localhost ~ # /tmp/ectool pdchipinfo 0 on vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # /tmp/ectool pdchipinfo 1 on EC result 2 (ERROR) Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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