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* servo: Adds logging of panic info to USB consolev2.4.0Brian J. Nemec2020-02-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a console command to log the panic info data to the UART console. This change modifies it so after printing data to UART, it will also pass it to the USB console so the data can be easily logged by servod. BUG=chromium:1018008 BRANCH=servo TEST=Manual testing on Sweetberry, ServoV4, and ServoMicro 1) Unplug device to clean panic info, plug device in to USB 2) Request 'panicinfo' from the console interface 3) Response 'No saved panic data available.' 4) Trigger crash using commands like 'sysjump 0x100' or 'crash assert' 5) Reconnect console 6) Request 'panicinfo'. Fault registers are returned over USB console and UART console. The values match the correct addresses which is easily verified in the sysjump case. Change-Id: I5b0bb102296f5fcc967519bb3a59af49644e6f4b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880579 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> (cherry picked from commit 27220c0776a906201d5c49a244b56508643c03b0) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044708 Reviewed-by: Brian Nemec <bnemec@google.com> Commit-Queue: Brian Nemec <bnemec@google.com> Tested-by: Brian Nemec <bnemec@google.com>
* common: Add sensor stillness detectorYuval Peress2019-12-182-0/+111
| | | | | | | | | | | | | | This change adds a stillness detector for 3d sensors. This will be needed to filter sensor readings when calibrating later. BUG=b:138303429,chromium:1023858 BRANCH=None TEST=buildall with new unit tests Change-Id: I919ae7533fd42b0394de66aa0585e58343a662cc Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833157 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common: Format firmware_image linker scriptCraig Hesling2019-12-171-42/+47
| | | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: Ia86d7ed16ad3d12c26688b23e79ffb6f4bba9531 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1970812 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_pd: Sending Thunderbolts-compatible host notificationAyushee2019-12-172-0/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | Sending the following information to the host in cros_ec_usb_pd_control command to configure thunderbolt compat mode: 1. TBT flag - Contains information about: a. Retimer (Present/Absent) b. Thunderbolt-compatible adapter (Type-C/ Legacy TBT adapter) c. Thunderbolt-compatible type (Optical/Non-optical) d. Active link training (Uni/bi-directional communication) 2. Cable speed (USB3.1 Gen1 Cable / 10 Gbps / 10 Gbps and 20 Gbps) 3. Cable rounded support (3rd Gen Non-Rounded TBT/ 3rd & 4th Gen Rounded and Non-Rounded TBT) BUG=b:140644242 BRANCH=None TEST=Verfied on the tglrvp-u CPU console using "ectool usbpd" command, able to get the information Change-Id: I38cf0b488945d78564c96eedab50a6e2900dfb80 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926381 Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Burnside bridge retimer: Add Thunderbolt-compatible mode bitsAyushee2019-12-171-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel burnside bridge retimer supports the ability to train the link and operate in both Thunderbolt 1/2(10Gbps) and Thunderbolt 3 (20Gbps) link speeds. Adding the following fields in the configuration register of the retimer to support Thunderbolt-compatible mode: 1. Active cable - Active/passive cable 2. Thunderbolt connection - Thunderbolt configured or not 3. Thunderbolt type - Type-C Type-C or Type-C legacy thunderbolt adapter 4. Thunderbolt Cable type - Optical or Electrical 5. Active link training - Unidirectional or bidirectional link training 6. Thunderbolt cable speed - 10Gbps/20Gbps active/passive cable 7. Thunderbolt Generation - 3rd generation or 4th generation thunderbolt cable BUG=b:140645327 BRANCH=None TEST=Manually verified on Tglrvp-U, able to configure the registers Change-Id: I4ac351702df156c5bddf4ead141f59000a6d6af5 Signed-off-by: Ayushee <ayushee.shah@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926380 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPMv1: Add support for Thunderbolt-compatible modeAyushee2019-12-173-10/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thunderbolt is a hardware interface that allows connection of external peripherals to a computer. This code enables thunderbolt 3 over Type-C interface. Thunderbolt provides concurrent support for PCIe transactions and DisplayPort and the thunderbolt controller provides isochronous communication on a single network style interface, allowing a Host computer to communicate at high bandwidth with multiple data/display devices through a single physical connection. The USB Type-C specification allows for Alternate Modes to be supported on the connector and cables. This CL adds a Discovery flow to determine if an Thunderbolt Alternate Mode is supported and a mechanism for switching in thunderbolt mode. TBT USB PD flow: -------------------Explicit contact--------------------- Discover Identity(SOP) ---- Modal operation supported? | ---------- ACK -----|---- NACK --- Disable TBT | Discover Identity(SOP') --- Check and store response (CL:1707851 and CL:1553898) | Is cable super speed? -------- Yes -------|----- No ---- Disable TBT | Discover SVID (SOP) -------- SVID == 0x8087? | ------------- Yes -----|------ No ---- Disable TBT | Discover SVID (SOP') -------- SVID == 0x8087? | ----------- yes------- | - No - Limit TBT to passive Gen 2 | Discover Mode (SOP) ------ Store device response ---------------| | Discover Mode (SOP') ----- Store cable response | Enter Safe mode | Active cable? --------- Yes -----|-------- No --------- | | Enter TBT mode (SOP' SOP" SOP) Enter TBT mode SOP (Note: This is not implemented in this CL) BUG=b:140643923 BRANCH=none TEST=Tested on Tglrvp-u able to enter into Thunderbolt-compatible mode & Non Thunderbolt-compatible devices are detected as per their spec. Change-Id: I65ed86e9f32d36fe8e30c3285f516b9871f3e119 Signed-off-by: Ayushee <ayushee.shah@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926379 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* cbi: add FW_CONFIG CBI fieldJett Rink2019-12-161-0/+13
| | | | | | | | | | | | | | | | | | This field will be used to describe which "features" or path the firmware code should enable or disable. Firmware code should look at the firmware configuration value to make code decision for un-discoverable hardware connections or layouts that differ within the same firmware binary. Firmware should no longer use SKU_ID/VARIANT_ID to make decisions, only this new FW_CONFIG field. BRANCH=none BUG=b:145519081 TEST=Created cbi image with FW_CONFIG field Change-Id: I1db8e7638a15343173ea5061e9038a7d53bda090 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1945821 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: add support for i2c bit-bangingTing Shen2019-12-163-7/+394
| | | | | | | | | | | | | | | | | | | | | | | | Krane/Jacuzzi need a 100KHz SMBus port for battery, in addition to the existing two i2c ports. This CL adds a bit-bang driver that supports i2c/smbus bit-banging through a set of pre-defined gpio pins. BUG=b:138161741,b:138415463 TEST=On a reworked jacuzzi (battery i2c connected to other gpios), 1) `battery` shows reasonable output (this verifies i2c_readN, i2c_read_string) 2) `i2cscan` works for port 3 (bitbang port) 3) `cutoff` (verifies i2c_writeN) 4) `i2ctest` stress test BRANCH=master Change-Id: I78020e5c51707c3d9f0fd54f2c299e2f29cabe2f Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1765110 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* TCPMv2: Add jittery holdoff timer before sending initial messages in ↵Sam Hurst2019-12-141-124/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PE_SNK/SRC_RDY In order to prevent collisions for PD 2.0 mode, we added a jittery holdoff timer which would pseudorandomly wait a time period before initiating messages of our own from the SNK/SRC ready states BUG=chromium:1022218 BRANCH=none TEST=make -j buildall manual tests: Connected Apple 2019 AV Multiport dock with Apple 2019 61W PSU Connected Kensington SD2000P dock Observed no packet processing collisions between port partners Using total phase, verified that as a source, a PD2.0 message was not sent before a 400+ ms delay while in the SRC_READY state. And as a sink, a PD2.0 message was not sent before 200+ ms delay while in the SNK_READY state. Apple 2019 A2119 HBR3 HDMI dongle Nektek 90w USB-C charger This collides with 0xf * 12ms Connect and observe for SRC_CAP interrupting VDM probes. Change-Id: I338b891baae754c2eaac106e33bc48bc12865d27 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907558 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bma255: Fix build dependency for BMA255 accelerometerKeith Short2019-12-131-1/+1
| | | | | | | | | | | | | | | The accel_bma2x2.c driver requires math_util.c, but was using the wrong config option to setup the dependency. BUG=none BRANCH=none TEST=make buildall Change-Id: I049ea9f621181593acfdb7eb506242ed8d530599 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1965646 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_pd: Rename "Externally powered" to "Unconstrained Power"Benson Leung2019-12-125-28/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was changed in PD 2.0 years ago (via ECN authored by our own David Schneider), but our codebase still refers to BIT 27 of the Fixed PDO as "Externally powered" instead of "Unconstrained Power". This will search and replace all instances of "Externally powered" when it refers to BIT 27, as well as function names, other internal representations of that property, strings, and comments. seds: s/PD_FLAGS_PARTNER_EXTPOWER/PD_FLAGS_PARTNER_UNCONSTR/g s/partner_extpower/partner_unconstrained/g s/externally powered/unconstrained/g Some others too. Signed-off-by: Benson Leung <bleung@chromium.org> BUG=chromium:1030990 TEST=Codebase builds clean. No functional change, except for the property shows up in ectool as "Unconstrained power" now. Change-Id: I5ececa03f29eb31057be3d0ad5311117093bc6da Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956147 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Benson Leung <bleung@google.com> Tested-by: Benson Leung <bleung@google.com>
* keyboard_scan: detect inconsistent state in read_matrixTing Shen2019-12-121-17/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current read_matrix() function didn't handle keyboard state change during the scanning loop. For example, consider keys J(c6r4), L(c9r4), H(c6r1) and F9(c9r1), and the following sequence: - User presses and holds J - Key scan task reads col 6, got state[6] = 0x10 (J) - User presses H+J+L, ghost key F9 is also "pressed" at this point. - Key scan task reads col 9, got state[9] = 0x12 (L+F9) - state[6] and state[9] has only one common bit, so it passes has_ghosting check. - EC thinks J+L+F9 clicked. Implemented a simple heuristic to detect this case, and update state[] array to something likely to be the state after the key press. With this change, we will no longer distinguish J -> H+J+L and J->F9+J+L. The latter used to be accepted but it'll be rejected by this change. BUG=b:145405136 TEST=hold J and L, press H repeatedly, make sure F9 never triggered. BRANCH=kukui,hatch TEST=make run-kb_scan (uncomment kb_scan in test/build.mk). TEST=The average wait_time is reduced about 100 usec on Nami: 1746 msec (old) v.s. 1636 msec (new). Change-Id: Ia20d5a283639d291530e5983254f6163f5c3537f Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1955105 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* tcpci: change connect to auto discharge disconnectDenis Brockus2019-12-121-0/+12
| | | | | | | | | | | | | | | | | | | It was originally thought the connect/disconnect would be a good generic way to set/clear auto_discharge_disconnect but it was not working reliably. Although the points that we are calling to perform this enable/disable are close to the connect/disconnect, there is more fine tuning required to make this work. BUG=b:144126745,chromium:951683 BRANCH=none TEST=attach/disconnect charger with and without AP running TEST=attach/disconnect device with AP running Change-Id: Ib1418771aec6d0a52895972e4db6881b072c0c3d Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1960514 Reviewed-by: Edward Hill <ecgh@chromium.org>
* Charge state v2: Only shutdown on cold dischargeDiana Z2019-12-111-4/+14
| | | | | | | | | | | | | | | | | | Currently, the discharge minimum temperature is always checked when determining if the system should shut down, even if the system is not discharging. This change allows the system to run below the discharging minimum temperature as long as AC is present. BRANCH=octopus BUG=b:145494158 TEST=loaded onto octopus unit, faked low battery temperature and verified the system did shut down when discharging and did not with AC Change-Id: I4f6549b04dc1e7b55e410d3ae4f67dc6126f9c7c Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958853 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_pd: Get current DP pin modeVijay Hiremath2019-12-113-13/+14
| | | | | | | | | | | | | | As part of the new changes in CL:1949052 getting DP pin mode status is removed hence adding back old CL:1646534 on TOT. BUG=b:146006717 BRANCH=none TEST=Manually tested on TGLRVP, able to see DP working Change-Id: I09cee179ad64c1b7753ec87ce83a1d5dc54770cd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961150 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rollback: Conditionally include cryptocCraig Hesling2019-12-111-0/+2
| | | | | | | | | | | | | | | | | | This include is not needed and not available when CONFIG_ROLLBACK_SECRET_SIZE is not defined. BRANCH=none BUG=none TEST=make buildall -j TEST=# undefine CONFIG_ROLLBACK_SECRET_SIZE in nocturne_fp board.h make BOARD=nocturne_fp # This will not compile without this fix # With this fix, no compilation errors are output Change-Id: I651f4e254189f34228f1aa2f2a2ff21808ab5d5c Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1952291 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usb_pd_policy: Make a lot of objects commonAseda Aboagye2019-12-101-1/+447
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a board specific usb_pd_policy.c file that contains a lot of code for handling DisplayPort Alternate mode, Google Firmware Update Alternate mode, as well as some PD policy functions such as deciding to Accept or Reject a data role swap or a power role swap. Several boards simply copy/paste this code from project to project as a lot of this functionality is not actually board specific. This commit tries to refactor this by pulling the functions that are not mainly board specific into common code. The functions are made overridable such that boards that truly do require a different implementation may do so. Additionally, this consolidation changes the policy behaviour for some boards, but they should be for the better. Some examples include that data swaps are always allowed if we are a UFP (no system image requirement), power swaps are allowed to become a sink if we are no longer dual role (e.g. - in suspend), and DisplayPort Alternate Mode is not entered if the AP is off. In order to facilitate this refactor, a couple CONFIG_* options were introduced: - CONFIG_USB_PD_DP_HPD_GPIO /* HPD is sent to the GPU from the EC via a GPIO */ - CONFIG_USB_PD_CUSTOM_VDO /* * Define this if a board needs custom SNK and/or SRC PDOs. * * The default SRC PDO is a fixed 5V/1.5A with PDO_FIXED_FLAGS indicating * Dual-Role power, USB Communication Capable, and Dual-Role data. * * The default SNK PDOs are: * - Fixed 5V/500mA with the same PDO_FIXED_FLAGS * - Variable (non-battery) min 4.75V, max PD_MAX_VOLTAGE_MV, * operational current PD_MAX_CURRENT_MA, * - Battery min 4.75V, max PD_MAX_VOLTAGE_MV, operational power * PD_OPERATING_POWER_MW */ BUG=chromium:1021724,b:141458448 BRANCH=<as many as we can that are still supported> TEST=`make -j buildall` TEST=Flash a kohaku, verify that DP Alt Mode still works with a variety of DP peripherals TEST=Repeat above with a nocturne TEST=Repeat above with an atlas Change-Id: I18fd7e22dc77fe1dc6c21c38cd7f1bc53cae86cb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949052 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Don't send SrcCap as a SNKSam Hurst2019-12-102-5/+2
| | | | | | | | | | | | | | | | | When a port partner TrySrc's the DUT, stop sending SrcCap message retries immediately. BUG=chromium:1020760 BRANCH=none TEST=make -j buildall manual tests: using total phase, I verified that SrcCap message retries are not sent when the DUT get's TrySrc'ed. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: Ia71d863e151221d5ad7c291b7a76d64c0caa8b99 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1924783 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* tcpci: Move HOOK_USB_PD_CONNECT earlier to fix VBUS sourceEdward Hill2019-12-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | Revert the change made by crrev.com/c/1940777 to where hook_notify(HOOK_USB_PD_CONNECT) is called in PD_STATE_SRC_DISCONNECTED_DEBOUNCE and PD_STATE_SNK_DISCONNECTED_DEBOUNCE. For the source case, it needs to be before pd_set_power_supply_ready(), because tcpci_tcpc_connect_state_change() needs to set TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT before ppc_vbus_source_enable() sends TCPC_REG_COMMAND_SRC_CTRL_HIGH to the NCT3807 TCPC. BUG=b:145095935 BRANCH=none TEST=VBUS source enabled when sink device plugged into USB-C1 Change-Id: I9dc98b2deb5e8dde0cd2ae9267d7952967551e02 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958572 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* TCPMv2: Fixed PR swap request from charge managerSam Hurst2019-12-102-3/+8
| | | | | | | | | | | | | | | | | | | The PR swap request from the charge manager was locking up the TC state machine. The pd_request_power_swap function was changed so that it sends the request to the policy engine instead of initiating it directly. BUG=chromium:1027247 BRANCH=none TEST=make -j buildall Tested with apple dongle "A2119 2019 HBR3" known to reproduce this problem. Change-Id: Ic59036056434ed525a839cd781cff93e3b5bfc53 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928795 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Define board_override_features_flags APIs as overridablednojiri2019-12-101-8/+12
| | | | | | | | | | | | | | | | | | | | | | Currently board_override_features_flags0/1 are enabled by CONFIG_EC_FEATURE_BOARD_OVERRIDE. This patch defines the callbacks as overridable. It will allow us to remove CONFIG_EC_FEATURE_BOARD_OVERRIDE and the redundancy it incurs. Signed-off-by: dnojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I0c2870b746879b272ada35b9615b611627a9f426 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1951810 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: add generic read/modify/write operationsDenis Brockus2019-12-101-0/+86
| | | | | | | | | | | | | | | | i2c_update is used to set or clear a mask i2c_field_update is used to clear out a field before the set BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7f8f93f4894fb9635092931a93961d328eacfeb9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956437 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* TCPMv2: Fixed the pointer problem with decoding SRC_CAP PDOSam Hurst2019-12-091-1/+1
| | | | | | | | | | | | | | | | | | A pointer to the PDO was getting incorrectly incremented, causing an unknown value to be sent to the pe_update_pdo_flags function. BUG=chromium:1027252 BRANCH=none TEST=make -j buildall Plugged in an apple dock and verified that the PDO was being correctly decoded. Change-Id: I06f11aad0043f63ef43f75beccf48241f739ae46 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928794 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TCPMv2: Handle unexpected msgs received during Port DiscoverySam Hurst2019-12-091-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During a port discovery, unexpected messages such as SRC_CAPs and Not_Supported are handled by the Src.Attached or Snk.Attached state and the port discovery process is terminated. BUG=chromium:1027252 BRANCH=none TEST=make -j buildall Manual Test: Used an Anker charger to verify that Not Supported messages are handle correctly during a Port Discovery. Total Phase output: Source:DFP, Source_Cap Sink:UFP, GoodCRC Sink:UFP, Request Source:DFP, GoodCRC Source:DFP, Accept Sink:UFP, GoodCRC Source:DFP, PS_RDY Sink:UFP, GoodCRC Sink:UFP, VDM:DiscIdentity Source:DFP, GoodCRC Source:DFP, Not_Supported Sink:UFP, GoodCRC Change-Id: I48db149c0c59affe6aad49b8b1bcfb6dc3656142 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928793 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: narrow the condition for custom TPM command codesNamyoon Woo2019-12-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | CR50 used to detects the custom TPM command code if the vendor specific bit field is set. This patch enfornces this condition by comparing the command code to 0x20000000 value. It is planned to support extended TPM commands, which are not yet standard, and those commands shall have 0x20000000|x as their command code. This patch will pass those commands to tpm2 library directly by calling ExecuteCommand(). BUG=b:140527213 BRANCH=cr50 TEST=ran gsctools with -m, -o, -i options. Cq-Depend: chromium:1892419 Change-Id: I43ce52bee96f6b6def8e4bf3a14f092b3235740a Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891523 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* fusb302: implement vbus measurement using tcpcTing Shen2019-12-091-0/+2
| | | | | | | | | | | | | | | | Jacuzzi measure vbus using fusb302, add a config option CONFIG_USB_PD_VBUS_MEASURE_TCPC and related implementation. BUG=b:145376409 TEST=`ectool usbpdpower` BRANCH=none Change-Id: I84019a75338121f777a344a4b92710e2117a6bda Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1947507 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* usb_pd: request preferred voltage PDOYilun Lin2019-12-093-7/+207
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_USB_PD_PREFER_MV to support PD will request preferred voltage. One should define pd_pref_config, including preferd voltage, e.g. 5000, and PD_PREFER_BOOST or PD_PREFER_BUCK based on the board charging efficiency. Also, system PLT power is needed for evaluating board's desired power. The option will try to find a most fit PDO: 1. Pick the PDO which fulfills the system desired power. If a preferred voltage PDO doesn't provide enough power, it will be skipped. 2. If none of the PDO meets the preferred voltage, it will pick the closest voltage PDO based on prefer boost or prefer bulk. 3. The system desired power will be constantly updated when system in constant voltage stage (battery percent > 70%). This is done by monitoring the battery charging current. 4. If the system desired power changes, it will re-evaluate the PDO and send request if has a better fit. TEST=Set prefer_mv to 5000 and ensure PD voltage could pick 9V/12V when desired voltage > 15W (5V/3A) and pick 5V when desired voltage <= 15W BUG=b:141170279 b:141903096 b:144073892 BRANCH=kukui Change-Id: I94646cb1c74c10cf8db889f19c3df6339844042c Signed-off-by: Yilun Lin <yllin@chromium.org> Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1871499
* TCPMv2: Operating as a SNK, clear the End AMS flagSam Hurst2019-12-071-3/+17
| | | | | | | | | | | | | | | | | | While operating as a sink, the End AMS flag is cleared at the end of the Atomic Message Sequence. BUG=b:145812132 BRANCH=none TEST=make -j buildall manual tests: Using a kohaku and a Kensington dock, I verified that the END_AMS flag is cleard and PD communication does not stop. Change-Id: Ia8b40ab42916dc5b2a690a6fb7f519015912a6fa Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954256 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Don't use SinkTXOK/NG in middle of partner-initiated PD3.0 AMSSam Hurst2019-12-071-25/+35
| | | | | | | | | | | | | | | | | | Don't send ACCEPT message (to PR_SWAP AMS initiated by partner) after lowering Rp to SnkTXNG. BUG=chromium:1023064 BRANCH=none TEST=make -j buildall manual tests: Connected several docks with charger and verified PR_SWAP. Also works with the CM dock that triggered this bug. Change-Id: Iab5474174cf8313c24bae8a7869565005504af25 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912161 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Don't turn off VCONN during a PR_SWAPSam Hurst2019-12-061-1/+1
| | | | | | | | | | | | | | | | | A flag that tracks PR_SWAP was being prematurely cleared, causing VCONN to turn off. BUG=chromium:1031304 BRANCH=none TEST=make -j buildall manual tests: Using a kohaku and a Kensington dock, I verified that VCONN does not turn off during a PR_SWAP Change-Id: I2947bd50f299684d58f4cbdcd9c649f395c3d7d2 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954311 Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: use different task pause for each portDenis Brockus2019-12-061-4/+6
| | | | | | | | | | | | | | | Switching over to using an array with an entry per port so each port is individually paused and awaken. BUG=none BRANCH=none TEST=charger attach unattach repeated time should work Change-Id: I570f93876d2ea60a5a0707f2096969ceb269b31f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954307 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: remove entering_mode host commandJoel Kitching2019-12-061-20/+0
| | | | | | | | | | | | | | | | | After this host command is called, the value is stored in g_vboot_mode and never accessed again. BUG=b:124141368, chromium:1014379 TEST=make buildall -j BRANCH=none Change-Id: I7923658139d15394c1c3c07baca7168e34c111e9 Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:1830239, chromium:1864533 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1865050 Tested-by: Joel Kitching <kitching@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Joel Kitching <kitching@chromium.org>
* ppc: Use hard reset to recover from CC overvoltageEdward Hill2019-12-061-0/+5
| | | | | | | | | | | | | | | When sn5s330 PPC detects CC overvoltage, recover via hard reset and don't enable PP2 sink FET directly. Also clean up the interrupt unmasking in sn5s330_init(). BUG=b:144892533 BRANCH=grunt TEST=Do ESD test to trigger CC1/CC2 OVP, device recovers to sink Change-Id: I662bf164b55508be4d5cc1b3ad639c9613bd1935 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949264 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usbc: Move PPC overcurrent functions to usb_common.cEdward Hill2019-12-064-108/+67
| | | | | | | | | | | | | Share single copy of PPC overcurrent functions between TCPMv1 and TCPMv2. BUG=none BRANCH=none TEST=build Change-Id: I70e25e8580f6bbfebe6269552cd186f3bb981ede Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954305 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/host: Avoid concurrent recipes of libcryptoc.aYicheng Li2019-12-051-0/+1
| | | | | | | | | | | | | | | | | | | | CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50. CONFIG_LIBCRYPTOC does similar things for other boards that configures it, including host. This resulted in cr50_fuzz having concurrent recipes for libcryptoc, as it has both configs. This change separates CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc. Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC. BRANCH=none BUG=b:144811298 TEST=make -j buildall > /dev/null Observed no more "warning: overriding recipe for target 'build/host/cr50_fuzz/cryptoc/libcryptoc.a' " Change-Id: I2186cbead773629456da254df5f82b96e9646fc2 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* tcpci: POWER_CTRL auto discharge disconnect initDenis Brockus2019-12-051-9/+9
| | | | | | | | | | | | | | | | | Change TCPCI to use HOOK_USB_PD_CONNECT/DISCONNECT to set/clear TCPC_REG_POWER_CTRL_AUTO_DISCHARGE_DISCONNECT according to the TCPCI spec. Change the definition of HOOK_USB_PD_CONNECT to occur after CC and VBus are stable. BUG=b:144126745,chromium:951683 BRANCH=none TEST=Charger attach/pull with AP not running Change-Id: I625efbba80f190322e3e92de6318b710b3ce7ade Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1940777
* usb_pd: Enable Try.Src when dedicated charge port presentAyushee2019-12-021-0/+9
| | | | | | | | | | | | | | | | | | When a dedicated charge port is connected, it can source power. Hence, allow PD for trying as source. BUG=b:144824310 BRANCH=None TEST=Tested on TGL-Y able to see try.src logs with DC jack present without the battery connected Change-Id: I46e419c7e08ab4cf1e43c8b65e9cc4fdadc73825 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926712 Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* i2c: don't output trace line for 0 length dataDenis Brockus2019-12-021-0/+3
| | | | | | | | | | | | | | | | | Write I2C operations always displayed a line indicating a read of port:addr with nothing following. Just don't output any lines that have no data to display. BUG=none BRANCH=none TEST=i2ctrace should not display lines with no data Change-Id: I1ba4bf3e627c47e62c68a592473431fcc195420a Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1940776 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Fix smart erase.Barry Twycross2019-11-271-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Smart erase is used by the haven private-CR51 firmware, I don't know if other projects use it. Smart erase attempts to speed up erase by checking if the block to be erased is all ff's, and only erasing it if there is content (not ff's). The bug is that after erasing a block, the code does not wait for completion of the erase before reading ahead to see if the next block is already erased (all ff's). This is contrary to the spec where the only valid operation is a check of the status after issuing the erase. On some eeproms, with some timings, this causes the smart erase to give a flase positive erased block detection. Ie, the eeprom reads back al ff's while it's busy doing the erase. The upshot is that only the first non erased block is erased, and the rest of the eeprom is left untouched. The code before smart erase looked like: do wait for not busy erase block until all erased wait for not busy Smart erase was added by inserting the check for erased at the top of the loop. If instead, it's moved down below the wait for not busy, everything works fine. (Or, the wait for not busy is moved back to top of the loop.) This is the fix used here. TEST= Run without and with patch on a Starcard. Without patch not all of the targeted flash is erased. With patch, all of the targeted flash is erased. BUG=b:144868388 BRANCH=barryt/smart Signed-off-by: barryt@google.com Change-Id: I679ad4d21c3c353252646394f5631abc42782ded Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931466 Reviewed-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Barry Twycross <barryt@google.com> Commit-Queue: Barry Twycross <barryt@google.com> Tested-by: Barry Twycross <barryt@google.com> Auto-Submit: Barry Twycross <barryt@google.com>
* host_command: clear any leftover dataJett Rink2019-11-261-0/+14
| | | | | | | | | | | | | | | We want to ensure that the entire buffer we may be sending back to the host from the EC does not contain any data from previous host command responses. Clear the data in common code so all chips do not have to implement this functionality. BRANCH=none BUG=b:144878983,chromium:1026994 TEST=new unit test shows cleared data Change-Id: I93ad4d36923ba1bf171f740e94830640d3fde3b0 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930931
* usbc: make BB virtual mux retimer compatible with non-virtualDenis Brockus2019-11-251-2/+0
| | | | | | | | | | | | | | | | Changed the driver interface for BB virtual mux retimer to stop using global functions and use the usb_retimers array instead. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I56befaca1720eb2f4e0599a983629b4df45dc76b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928121 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* Reland "smart_battery: add smbus error checking support"Ting Shen2019-11-251-36/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of daccb3adea9394116d7ab2c807e4a360cb5a93a1 Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: http://crrev.com/c/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> BUG=b:138415463 TEST=in addition to the TESTs above, verified this CL boots on hatch(npcx chips), and reef_it8320(it83xx chips). BRANCH=master Change-Id: I67975eee677cfd6e383742d48103662372cac061 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913940 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* battery : differentiate overtemperature conditionYongBeum.Ha2019-11-251-2/+13
| | | | | | | | | | | | | | | | Battery charging is stopped over 55'C during charging and started below 45'C. BUG=b:140596424 BRANCH=hatch TEST=make -j BOARD=kohaku && ./util/flash_ec --board=kohaku check charging status & led on chamber Change-Id: Ib4a8ba5236d107397db904ca7075f0d0f29dd724 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928539 Tested-by: YongBeum Ha <ybha@samsung.com> Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* TCPMv2: Keep message transmission and reception synchronizedSam Hurst2019-11-242-52/+114
| | | | | | | | | | | | | | | | | | | | | If a message is expected after a transmit, hold off on checking for that until the sender response timer is set. BUG=chromium:1022715 BRANCH=none TEST=make -j buildall manual tests: Connect StarTech CDP2DP USB-C to DP dongle Observe REQUEST send less than 1ms after SRC_CAP Look for ACCEPT message sent by PE and PD Change-Id: I1d155ead698ac39172c604cc3f656631565855d5 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907807 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: PD: Separately track each SOP and SOP' and SOP''Sam Hurst2019-11-243-89/+168
| | | | | | | | | | | | | | | | | | Tracked PD header spec. version for each port partner type. BUG=chromium:1023025 BRANCH=none TEST=make -j buildall Manual Testing: Connected PD2.0 source charger and made sure we talked PD2.0 Connected PD3.0 source charger and made sure we talked PD3.0 Connected apple 2019 PD2.0 dock with charger and made sure we downgraded from PD3.0 to PD2.0 Change-Id: I3b49d9630acf6c19101ac71334445890c78c4077 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1907430 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: ServoV4 is not recognized appropriatelySam Hurst2019-11-222-95/+340
| | | | | | | | | | | | | | | | | | Configure the port as a SNK with PD in DebugAccessory.SNK state BUG=chromium:1020752 BRANCH=none TEST=make -j buildall Manual Test: 1: Connect Servo v4 with NeckTek charger pluged in DUT power port The DUT negotiates to 20V, and starts charging. Change-Id: Id44d566024b5016965f996435d11befdc1c53e98 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1906993 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: fix storm tracker overflow issueJett Rink2019-11-221-6/+9
| | | | | | | | | | | | | | | | | | | If there is no USB-C interrupt activity for 2^31 microseconds, then there are more than ALERT_STORM_MAX_COUNT events within 2^31 microsecond (instead of ALERT_STORM_INTERVAL), then the interrupt storm would incorrectly detect a storm and disable the port due to incorrect math regarding 32-bit overflow. BRANCH=octopus and all branches with original storm detection (CL:1650484) BUG=b:144369187 TEST=unit test in CL Change-Id: I90b888ac092f81d151538d6018771fb32f8e9c39 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925668 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* battery : Define CONFIG_BATTERY_DEAD_UNTIL_VALUEYongBeum Ha2019-11-221-0/+4
| | | | | | | | | | | | | | | | It takes 850ms~950ms to get valid RSOC after battery wake-up. Sometimes battery FG returns garbage data(1%) as RSOC and 0 value of desired current / voltage. Add CONFIG_BATTERY_DEAD_UNTIL_VALUE to continue charging. BUG=b:138413964 BRANCH=None TEST=build & flash, check battery charging with dead battery Change-Id: I0cbe30aa973499b0c27faf9b6da03a0344ad1065 Signed-off-by: YongBeum Ha <ybha@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918985 Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv2: Enable TCPC low power when port is looking for a connectionSam Hurst2019-11-214-253/+473
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port is in a state where it is looking for a connection, to save power, we should put the TCPC in its low power mode and enable auto toggling. Low power mode can happen when DRP auto toggling, acting as a SNK only, or acting as a SRC only. BUG=chromium:1022217 BRANCH=none TEST=make -j buildall manual tests: 1: (S0) Nothing plugged in, port is drp and low power mode 2: (S5/S3/S0ix) Port is SNK only, and low power with nothing plugged in 3: (S3/S0ix) If TypeC sink was previously plugged in, port remains powered 4: (S5/S3/S0ix) TypeC source is recognized 5: (S3->S0) TypeC sink plugged in, port is powered when S0 is reached Low power exit test: Using this command from the AP console: ectool i2cread 8 2 0x16 0x0d Transfer failed with status=0x1 # This means the TCPC was asleep. On the EC console: 2019-11-21 09:50:24 [315.235538 TCPC p1 init ready] 2019-11-21 09:50:24 [315.236048 TCPC p1 Exit Low Power Mode] 2019-11-21 09:50:24 [315.242837 TCPC p1 init ready] 2019-11-21 09:50:24 [315.243229 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.246471 C1: Unattached.SNK] 2019-11-21 09:50:24 [315.252504 C1: DRPAutoToggle] 2019-11-21 09:50:24 [315.362878 C1: LowPowerMode] 2019-11-21 09:50:24 [315.363314 TCPC p1 Enter Low Power Mode] Change-Id: I7e853d05e0ece1f6b3031f17a18fcbf0d9a15a51 Signed-off-by: Sam Hurst <shurst@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904974 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv1: Improve jitter based collision avoidanceAseda Aboagye2019-11-211-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | For the holdoff timer, we were using the system timestamp as a source of adding jitter. However, it seems that there are certain cases that can cause a periodic collision with the jitter only varying by ~1-2ms. This leads to many repeated collisions until the jitter slides just out of the collision window. This commit changes the jitter calculation to use more of the bits that are changing to reduce the number of collisions. BUG=b:144676183, chromium:925618 BRANCH=hatch,atlas,nocturne,grunt,octopus,rammus,kukui TEST=Flash kohaku, plug some peripherals known for collisions, verify that if a collision is encountered, it's only encountered once (no cycles). TEST=Add debugging prints for the jitter, verify that the jitter is varied and appears non-deterministic. Change-Id: I6c27880551dd35b78993f7130d1ce4eb81aa10ef Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922751 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
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