| Commit message (Collapse) | Author | Age | Files | Lines |
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This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a.
Reason for revert: responsible for CQ failures (crbug.com/1202406)
BUG=chromium:1202406
BRANCH=none
TEST=CQ
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Original change's description:
> config: rename CONFIG_FLASH to CONFIG_FLASH_CROS
>
> The config name collides with the same config name in zephyr.
>
> Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to
> CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig
> side.
>
> BUG=b:180980668
> TEST=make buildall
> BRANCH=none
>
> Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640
> Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622
> Tested-by: Eric Yilun Lin <yllin@google.com>
> Reviewed-by: Keith Short <keithshort@chromium.org>
> Commit-Queue: Keith Short <keithshort@chromium.org>
Bug: b:180980668
Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274
Auto-Submit: Jack Rosenthal <jrosenth@chromium.org>
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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The config name collides with the same config name in zephyr.
Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to
CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig
side.
BUG=b:180980668
TEST=make buildall
BRANCH=none
Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry
to the G3 power state.
BRANCH=None
BUG=b:166787955,b:167996216,chromium:1045209
TEST=make -j buildall, runs on waddledee with no linking errors
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used
throughout. The issue is that the units don't match. In
Zephyr the value is in KiB instead of bytes. This refactor
simply renames CONFIG_FLASH_SIZE in platform/ec to include
the unit (via _BYTES).
BRANCH=none
BUG=b:174873770
TEST=make buildall
be generated by the build instead of per board
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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1. In npcx7, the PSL (hibernation) wakeup source only can come from
physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer)
module is introduced to support wakeup from a configurable timeout.
2. support PSL wakeup from the VCC1_RST pin. This function is disabled
by default and enabled (and locked) in the firmware in the npcx9 A1
chip. In the npcx9 A2 chip, this function is enabled (and locked)
by booter.
3. Support pulse mode and open drain (if pulse mode is enabled) for
PSL_OUT pin.
4. support one PSL general-purpose output pin which is powered by VSBY.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds.
make sure the reset cause in the console is "power-on hibernate
rtc-alarm"
TEST="hibernate"; check EC wakes up from hibernate after pressing
VCC1_RST button on the internal test board.
Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1
power; check EC can wake up from hibernate with any input event.
Test=configure the level of PSL_GPO before hibernation; check the level
is kept after entering hibernation.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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This fixes a regression introduced by chromiun:2325768 that broke
software sync and forced recovery mode due to an incorrect EC image
size value when CONFIG_CHIP_DATA_IN_INIT_ROM is used.
also, __image_size was set twice in the linker script with the latter
taking precedence when CONFIG_CHIP_INIT_ROM_REGION is enabled. Made
the 1st occurrence conditional to avoid confusion.
BUG=none
BRANCH=none
TEST=EC console "hash" command now reports the correct image size and
we no longer end up in recovery due to software sync.
Change-Id: Ic0fb405f6918bdfa467be5919eed91eb17ef7c2a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428566
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Reorganize the RO and RW images so the .data section remains in flash
and is not copied into code RAM by the bootloader. This frees effective
flash space for more code in the .text and .rodata sections.
The EC initialization is changed to copy the .data section directly from
flash into data RAM so the runtime access of objects linked into .data
are unchanged.
This is controlled with a new config option
CONFIG_CHIP_DATA_IN_INIT_ROM. This option is automatically enabled when
the board enables the ROM resident section with
CONFIG_CHIP_INIT_ROM_REGION and the EC chip supports memory mapped
access to flash (CONFIG_MAPPED_STORAGE).
On Volteer this change saves 1656 bytes of RW flash space.
BUG=none
BRANCH=none
TEST=make buildall
TEST=Run "ectool motionsense lid_angle" on Volteer.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I2eff814ad240dfb46bfba400b83d78d1f69a8310
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325768
Reviewed-by: caveh jalali <caveh@chromium.org>
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CL:2334389 broke the make debug output for the kukui_scp and
flapjack_scp boards. The actual EC image was not affected.
This change also cleans up the #ifdef usage to consolidate assignment of
the output sections into one place.
BUG=b:164696005
BRANCH=none
TEST=make buildall
TEST=Run "util/compare_board.sh -b cortex-m"
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: If69cb492e2aa5f1181e27be24ee66f63cc74ff62
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359492
Reviewed-by: caveh jalali <caveh@chromium.org>
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EC images are copied in full from flash to RAM. When the code RAM size
is smaller than 1/2 the flash size, the EC image size is limited to the
code RAM size, leaving unused flash space.
Create a new linker section .init_rom used to store data objects that
are single use in the previously unused flash area. Data objects can be
used at runtime by copying into RAM using the flash_read() function.
This change is tied to the NPCX flash layout, with asserts to ensure
builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by
the chip.
CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until
the predecessor CL:2325764 is available in CPFE images.
BUG=b:160330682
BRANCH=none
TEST=make buildall
TEST=With debug code, use the _init_rom macro and validate the data can
be read using flash_read().
TEST=Using hex editor, verify .init_rom section located at 192K boundary
and unused bytes are filled with 0xFF.
TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m)
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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Change the linker symbol used to track available flash from __image_size
to __flash_used. __image_size is now only used on the struct image_data
header.
BUG=b:160330682
BRANCH=none
TEST=make buildall
TEST=Run compare_build.sh against the following boards:
cortex-m: volteer (npcx chipset)
cortex-m0: honeybuns (stm32f0 chipset)
minute-ia: not changed
nds32: waddledee (it83xx)
riscv-rv32i: asurada (i8xxx2)
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I94f5b4827cc0da1055520685cfeb1fafc0119e1c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334389
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Add linker defined labels for the configured flash sizes. This is only
used for image analysis.
BUG=none
BRANCH=none
TEST=make buildall
TEST=To see the labels run
"nm -n build/<board>/RW/ec.RW.elf | grep __config"
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ib4db8478b19a8d93776c68fa24ee31fb21a50a24
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325765
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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These hooks are only enabled through a new CONFIG.
The resume init hook will be used to initialize the SPI driver,
which goes to sleep on suspend. Require to initialize
it first such that it can receive a host resume event, that
notifies the normal resume hook.
The suspend complete hook is paired with the resume init hook,
which reverts the initialization of the SPI driver.
BRANCH=None
BUG=b:148149387
TEST=make buildall -j
TEST=Build successfully on both default off and defining this CONFIG.
Change-Id: I615e2bf92c75f83a7b0ab3eded61a1ef241dbdcf
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321875
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A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are
called from the chipset task, while the system has already shut down
and all the suspend rails are already off.
It will be used for executing pending EC reboot at the chipset shutdown.
The EC reboot should be executed when the chipset is completely off.
BRANCH=None
BUG=b:156981868
TEST=Built all boards.
Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BUG=b:149350081
BRANCH=none
TEST=build all, and emerged ec related packages for host and octopus.
$ make buildall -j
$ cros_workon --host list
chromeos-base/chromeos-cr50-dev
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools
$ sudo emerge chromeos-cr50-dev -j
$ sudo emerge chromeos-ec -j
$ sudo emerge chromeos-ec-headers -j
$ sudo emerge ec-devutils -j
$ sudo emerge ec-utils -j
$ sudo emerge ec-utils-test -j
$ sudo emerge hdctools -j
$ cros_workon-octopus list
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools
$ sudo emerge-octopus chromeos-ec -j
$ sudo emerge-octopus chromeos-ec-headers -j
$ sudo emerge-octopus ec-devutils -j
$ sudo emerge-octopus ec-utils -j
$ sudo emerge-octopus ec-utils-test -j
$ sudo emerge-octopus hdctools -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: If751b26b0635b0021c077338e96eaa8e8dcf17a5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080631
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This is just a cleanup of the linker scripts for cortex-m chips.
This brings no functional change.
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: If9fa43157e8955fed7c7426b910c6af957794b0b
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930392
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Enable CONFIG_PRESERVE_LOGS to gather more information
when SCP is crashed.
TEST=1. crash scp
2. restart scp
3. restart timberslide to ensure the logs are fetched
4. see that untransmitted logs are fetched into /var/log/cros_scp.log
BUG=b:140220117
BRANCH=none
Change-Id: I12635afa6c92fd8fa9cc889ce75999f855f18db0
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833943
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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I had a hard time reading this section, so figured I may as well
rewrite it to use IS_ENABLED while I was here.
Gave CONFIG_{RO,RW}_HEAD_ROOM a default value of zero here, which
makes the math work out for boards without it anyway.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I87dc2d73838c350088916b57aa51d5f368c5592f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727570
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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This option was only used with kunimitsu, which was removed from the
EC codebase a long time ago. The EC code won't even compile with this
option enabled anymore.
Remove it!
BUG=chromium:989301
BRANCH=none
TEST=buildall
Change-Id: I8ede226ec1e7b300ded6bb1769d82e142db1b0aa
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727569
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL fixes DRAM section loaded at the wrong location, and
also relayouts the DRAM section to have a smaller flat binary.
Current DRAM region layout is as below:
.dram.data LMA | LOAD
.dram.data VMA |
.dram.bss | NOLOAD
.dram.rodata | LOAD
.dram.text | LOAD
This will create a flat binary file as following layout:
.dram.data
.dram.bss
.dram.rodata
.dram.text
and loader will load .flat.dram to .dram.data LMA's starting section.
This leads to .dram.bss, .dram.rodata and .dram.text been loaded at
the wrong location, where .dram.data VMA resides.
This CL fixes the issue by reorganize the sections into:
.dram.text | LOAD
.dram.rodata | LOAD
.dram.data LMA | LOAD
.dram.data VMA |
.dram.bss | NOLOAD
and thus we have a flat binary as:
.dram.text
.dram.rodata
.dram.data
so that:
1. everything will be placed at the correct address.
2. have a smaller flat binary.
The CL also removes .dram.keep.* section, which is not used so far.
BUG=b:134079593
BRANCH=master
TEST=With crrev.com/c/1646691, check the output of object header:
1. SIZEOF(.dram.text + .dram.rodata + .dram.data) = SIZEOF(.image.RW.dram)
0x68 0x18 0x14 0x94
2. ADDR(.dram.data LMA) + SIZEOF(.dram.data) = ADDR(.dram.data VMA)
0x10000080 0x14 0x10000094
arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf
Idx Name Size VMA LMA File off Algn
5 .dram.text 00000068 10000000 10000000 00030000 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
6 .dram.rodata 00000018 10000068 10000068 00030068 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .dram.data 00000014 10000094 10000080 00030094 2**0
CONTENTS, ALLOC, LOAD, DATA
8 .dram.bss 00000004 100000a8 100000a8 000300a8 2**0
ALLOC
arm-none-eabi-objdump -h build/kukui_scp/ec.obj
Idx Name Size VMA LMA File off Algn
2 .image.RW.dram 00000094 50000000 50000000 00020000 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
TEST=With crrev.com/c/1646691, see the console has correct output:
dram_bss_val = 0
dram_data_val[0]= 1
dram_data_val[1]= 2
dram_data_val[2]= 3
dram_data_val[3]= 4
dram_data_val[4]= 5
dram_data_val[5]= 6
dram_data_val[6]= 7
dram_data_val[7]= 8
dram_data_val[8]= 9
dram_data_val[9]= 10
dram_data_val[10]= 11
dram_data_val[11]= 12
dram_data_val[12]= 13
dram_data_val[13]= 14
dram_data_val[14]= 15
dram_data_val[15]= 16
dram_data_val[16]= 17
dram_rodata_val[0]= 55
dram_rodata_val[1]= 56
dram_rodata_val[2]= 57
dram_rodata_val[3]= 58
dram_rodata_val[4]= 59
dram_rodata_val[5]= 60
Change-Id: Ic6836c6ad553d0ceae4d55df92caa1896fee905d
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646690
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Auto-Submit: Yilun Lin <yllin@chromium.org>
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.dram.bss section is like .bss section that all the contents should
be initialized to zero.
TEST=build a image with .dram.bss section, and verify it only has
ALLOC attribute.
$ arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf
7 .dram.bss 00000acb 3009aaa8 3009aaa8 0010aaa8 2**2
ALLOC
BUG=b:134079593, b:122058243
BRANCH=master
Change-Id: I853b2977465b83458f566c5dd953458147d4e10e
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646689
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
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This patch adds a hook for USB PD connect event.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/127228934
BRANCH=none
TEST=buildall. Verify a hook is called on BC12 charger connection.
Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3
Reviewed-on: https://chromium-review.googlesource.com/1597794
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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ld won't complain .data LMA overlapping if using a computed LMA
address. This CL workaround this by assigning a load memory region.
Related discussion:
https://github.com/rust-embedded/cortex-m-rt/issues/86
TEST=make buildall -j
TEST=cherry-pick https://crrev.com/c/1592972
make BOARD=kukui_scp -j
and see it ld reports failure for LMA overlapping:
build/kukui_scp/RW/ec.RW.elf section `.data' will not fit in region `IROM'
region `IROM' overflowed by 3784 bytes
TEST=w/o this CL; make buildall -j; cp -r build build.old
w/ this CL; comment out EC version rules
#.PHONY: $(out)/ec_version.h
make buildall -j
compares the .flat files by:
for f in $(ls build/*/*/ec.*.flat | sed -e 's|build/||');
do
echo "###### diff ${f}"
diff <(xxd build/${f}) <(xxd build.old/${f})
done
and see that all the .flat are the same, except that
some boards(aquila, arcadia, cr5*, granite,
haven_dev, hg_*, hotelgolf, hslt_*, indus, proto2, red,
starcard, tk-x001) using g-chip have different content at
addr 0x0~0x360 (related to regen key?), and this change
is not likely to touch that address.
BUG=b:131641213
BRANCH=None
Change-Id: I54c697669ef3836c93027bce90f507c33283c6f3
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1588297
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Currently, kukui_scp's memory layout interleaves with RO and RW
sections. This complicates the MPU region configuration, and it
even unconfigurable.
This CL propose to simplify the layout and configuration by introducing
an IROM region, and re-layout the memory.
New layout would be:
---------------------------- 0x0
RO| .stepping_stone
| .text .rodata .data LMA
---------------------------- 0x100000
RW| .bss .data stack
| ipi shared buffer
---------------------------- 0x7C0000
BRANCH=None
BUG=b:123269246
TEST=1. w/o this CL: make buildall -j; mv build build.old
2. w/ this CL: make buildall -j;
3. compare smap by: ls build/*/*/ec.*.smap | \
sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
and sees that only kukui_scp's smap changed.
Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530263
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Overlapping LMA section with other VMA section will fail lld.
This CL makes the linker script to be compatible with both ld and lld.
BRANCH=None
BUG=b:128269393
TEST=On m/master; make buildall -j; mv build build.old
After this CL:
make buildall -j
ls build/*/*/ec.*.smap | sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
=> no difference except that __data_lma_start's attribute changes
from D to R.
e.g., 0011a4a0 D __data_lma_start becomse
0011a4a0 R __data_lma_start
TEST=diff build/kukui_scp/RW/ec.RW.flat build.old/kukui_scp/RW/ec.RW.flat
are the same, except the version strings.
TEST=CC=clang make BOARD=kukui_scp and see that __bss_start and
__data_lma_start not overlapping in kukui_scp/RW/ec.RW.smap
TEST=CC=clang make BOARD=nocturne_fp -j and build pass.
Change-Id: I4a6ece8d2279124e2797e0dc71b228a470f029d9
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1514436
Commit-Ready: Tom Hughes <tomhughes@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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We manually copy other .data from the original section on boot, and
clear DRAM .bss.
This way, a single object file (or archive) can be moved fully to
DRAM.
BRANCH=none
BUG=b:122058243
TEST=With next CL, dram_test works
Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1445652
Reviewed-by: Jett Rink <jettrink@chromium.org>
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With tpm2 makefile now re-naming .bss section in the produced objects,
there is need to try grouping files by module name, especially since
this does not even work when linking object modules directly instead
of the library.
BRANCH=cr50, cr50-mp
BUG=b:65253310
TEST=make BOARD=cr50 -j produces an image with the same _bss_libtpm2
section.
Change-Id: I38f8ec3efa0364a0ad58781b7822a0eb52b636bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1457602
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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If .text, .rodata and .bss section are all puts in the same memory
space, e.g. RAM (.data section's LMA is usually located right
after .rodata section, and right before .bss section.).
.data section's LMA might be overlapped with .bss section so that
it would get cleared to zero on program startup.
TEST=Remove ". = ALIGN(512);" in .bss section in linker script,
and check build/kukui_scp/RW/ec.RW.smap, and we have
__data_lma_start = 0x74b4
__bss_start = 0x74f8
__data_start = 0x8ae0
__data_end = 0x8b20
__data_end - __data_start = 64
__bss_start - __data_lma_start = 68 # .data is able to fit in.
check .data section LMA won't be overlapped with .bss section VMA.
BUG=b:122084384
BRANCH=None
Change-Id: Ic6ae7ad7c6a080ce7aa6375c4f0e01ac9474cdc7
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1404640
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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The name of __ro_end is confusing. The variable is
actually used as a label tagging that it is the starting
address of .data LMA. Renames to __data_lma_start to
be more decriptive.
BRANCH=None
TEST=make buildall -j
BUG=b:122084384
Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1433160
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This allows to store specific code/data in a .dram region. This
is used by mt_scp to run code off DRAM, as we plan to have more
code than what can fit in SRAM.
BRANCH=none
BUG=b:122058243
TEST=make BOARD=kukui_scp -j
objdump -x build/kukui_scp/ec.obj
=> Some code is loaded in DRAM
TEST=Load kukui_scp, icachetest works
Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1391542
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We would like to keep a symbol in a chip memory region from GC in link
time. However __attribute__((used)) cannot fulfill the requirement in such
situation. This CL adds a "name.keep" section to prevent all the symbols
in this section in a chip memory region from GC. Also, we would like to
support a non-NOLOAD section, which can load default value on runtime.
BUG=b:120825336
TEST=make buildall -j
BRANCH=none
Change-Id: I76cf445f6b4c0b61c20182a1aaf5a44f962049ae
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1373949
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Linker script verifies flash size and layout when generating firmware
binary. This configuration macro removes FLASH section and asserts.
BRANCH=none
BUG=b:114326670
TEST=make buildall -j
Change-Id: I3c9ce6f930260d780839e52b45055f88cc22f85f
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1208771
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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If we keep it assembly-only, the link time optimizer gets confused and
eliminates seemingly unused functions, to then replace references to
them with the "no handler" defaults in a later step.
Similar approach as with vecttable: Implement the table in C so LTO
knows the entire story.
BUG=b:65441143
BRANCH=none
TEST=usb_ep_{rx,tx,reset} and usb_iface_request look more reasonable in
disassembly on cr50.
Change-Id: I72103af742164c29aac38e9929d1a83d8c154b53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1177711
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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In our design once enter BIST test data mode, Hw don't
interrupt Fw due to any Rx received packet. But when port
partner re-connect in this mode, it will cause that our
pd port doesn't respond packet which port partner transmits.
When port partner disconnects, so we need to reset our pd
port protocol layer and PHY to leave BIST test data mode and
let Hw can interrupt Fw. With this modify it can pass
GRL-USB-PD compliance TDA2.1.2.2 test item.
BUG=b:112602596
BRANCH=none
TEST=GRL-USB-PD compliance test.
Change-Id: I30526b5d796e3eabc9af2f524071c98bb0ef5abf
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1170718
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Some boards are pretty tight on RAM space. Print out remain RAM bytes
for each board along with the tightest 3 boards during buildall.
BRANCH=none
BUG=none
TEST=buildall now outputs the tightest boards on RAM.
Change-Id: I819e554400e88937bb937f2ca51daf737588a9a5
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194342
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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Add a hook to act when a detachable device is connected/disconnected
from a base.
BUG=b:73133611
BRANCH=nocturne
TEST=Test with evtest that an event is sent to the AP.
Change-Id: I21103fff88f19a197124095ee229eebb178dcf3d
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1180538
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Different versions of the linker behave differently when mixing object
built with lto enabled (desirable for code size reduction) and disabled
(assembler code), especially when they refer to each other symbols:
The file evaluation order of the linker becomes important as it
eliminates dead code at various points in time, and LTO code referring
to non-LTO code or vice versa, is not visible at early runs.
Sadly, just changing the order on the command line isn't sufficient:
What works for gcc8 breaks gcc6 (and may behave different in even more
ways on gcc4 or other versions).
Therefore, implement the vector table in C, so it's compiled in LTO
mode, just like the code it refers to.
BUG=b:65441143
BRANCH=none
TEST=with this change coral EC is functional when built with the gcc 8.1
based coreboot toolchain.
Change-Id: I9b75f6558f0357e18000ff1161096c8f9c94a8ac
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1120333
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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We add a configuration option to set the minimum shared memory
size (CONFIG_SHAREDMEM_MINIMUM_SIZE), so that the link will fail
if there is not enough IRAM left.
Also, we add 2 macros around shared_mem_acquire, that check, at
build time, that the shared memory size is sufficient for the
allocation:
- SHARED_MEM_ACQUIRE_CHECK should be used instead of
shared_mem_acquire, when size is known in advance.
- SHARED_MEM_CHECK_SIZE should be used when only a maximum size
is known.
This does not account for "jump tags" that boards often add on
jump from RO to RW. Luckily, RW usually does not do verification,
and does not need as much shared memory.
BRANCH=none
BUG=chromium:739771
TEST=make buildall -j, no error
Change-Id: Ic4c72938affe65fe8f8bc17ee5111c1798fc536f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1002713
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Remove the former special case for USB RAM
Add additional RAM regions for STM32H7.
For USB RAM, add an explicit alignment directive to ensure we always meet
the 8-byte boundary hardware constraint for the BTABLE.
This was already true because we put the .usb_ram.btable section first.
I keep this property by alpha-sorting the sections but makes it more
explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection,
99_lastsection.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
TEST=build all targets with and without the patch and verify that all
smap files are identical.
Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175
Reviewed-on: https://chromium-review.googlesource.com/946369
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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When a chip has special/non-contiguous SRAM physical memory region,
rather than extending the generic linker file ad nauseam, define a
mechanism to declare a chip specific list of those regions.
To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS
configuration and have a memory_regions.inc with the list of regions.
The special-purpose preprocessed chip/<chip_name>/memory_regions.inc
file has one region declaration per line using the following macro:
REGION(name, attributes, start_address, size)
Each region will get a proper MEMORY entry and a section in the linker
file.
the __SECTION(region_name) helper is provided as a convenience to
declare variable in a specific region.
Note: those 'special' regions are NOT cleared at startup contrary to
.bss.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn, along with the following CLs, run the firmware with
large arrays in special AHB memory regions.
Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c
Reviewed-on: https://chromium-review.googlesource.com/946368
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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In particular, this will allow touchpad driver and keyboard matrix
scanning to be powered off/disabled when the USB interface is
disabled without setting the remote wake feature
(USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be
ignored anyway.
BRANCH=none
BUG=b:72683995
TEST=With next CLs, touchpad and keyboard matrix scanning are disabled
when lid is closed.
Change-Id: I3750bfaf8c31cde075adf9da4fef39753b8981c5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/897067
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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The compiler marks data put into the TPM2_common.bss section as
PROGBITS, which the linker does not like. Changing the section name
prevents the marking and keeps linker happy.
BRANCH=cr50
BUG=chromium:799385
TEST=verified that local_state is still in where it belongs:
$ egrep '(local_state|__bss_libtpm2)' build/cr50/RW/ec.RW.smap
00010400 B __bss_libtpm2_start
00015d0c b local_state
00015d18 B __bss_libtpm2_end
Change-Id: I48f7d2cb08c7ccb2ef3b3159eaf4d66e2b8720b4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/852793
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Modules in board/cr50/tpm2 are part of the TPM task, and their .bss
segment needs to be wiped out along with other TPM modules' when TPM
is reset.
The only module from this directory which has static variables is
NVMem.c. This patch groups the variables into a structure, and makes
sure that the structure is stored in the part of .bss which is zeroed
when TPM is reset.
BRANCH=none
BUG=none
TEST=verified that TPM wipeout happening during RMA reset is
successful.
Change-Id: I5f80dc5e4f5f7cdce2d1a1ed59e0fbac354c5bf6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/733814
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1.
All boards which use chip/g either use both CONFIG_USB_SERIALNO and
CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on
CONFIG_USB_SERIALNO.
This is in preparation for making common/case_closed_debug refer only
to the usb_pd_protocol version (with mode=disabled/partial/enabled),
and cr50 will have its own version (with only enabled/disabled, and
tied more closely to CCD config).
No functionality changes.
BUG=none
BRANCH=cr50
TEST=make buildall -j; boot cr50 and see change hook called
Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648067
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This adds the CCD configuration module, and the console commands to
control it. It is not wired up to any of the CCD capabilities; that's
coming in the next CL.
Briefly:
* CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to
print it.
* CCD can be Locked, Unlocked (some capabilities), or Opened
(all capabilities), using the ccdlock / ccdunlock / ccdopen commands.
* CCD config can be restricted by setting a password via ccdpass.
* Individual config capabilities can be set via ccdset. Some of those will
be used to gate access to things like write protect and UARTs. Others
affect the requirements for ccdunlock / ccdopen (for example, is physical
presenc required).
* The entire config can be reset via ccdreset. If only unlocked, config
that is restricted to Opened is not reset.
* If CR50_DEV=1, ccdoops will force-reset and open the config.
See go/cr50-ccd-wp for more information.
BUG=b:62537474
BRANCH=none
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccdlock # lock, because CR50_DEV=1 builds start unlocked
ccdinfo # locked, flags=0, all capabilities default
ccdpass # access denied (we're locked)
ccdreset # access denied
ccdset flashap always # access denied
ccdunlock
ccdinfo # unlocked
ccdpass foo
ccdinfo # flags=2 (password set when unlocked)
ccdset flashap always # access denied
ccdset uartectx unlesslocked
ccdinfo # yes, uartectx permission changed
ccdlock
ccdunlock # fails without password
ccdunlock bar # wrong password
ccdunlock foo # busy
(wait 3 sec)
ccdunlock foo
ccdreset
ccdinfo # no password, flags 0, capabilities all default
ccdopen # requires physical presence; tap power or use 'pp'
ccdset uartectx unlesslocked
ccdset batterybypasspp ifopened
ccdpass baz
ccdinfo # password set, flag 0, ccdset changes worked
ccdunlock
ccdreset
ccdinfo # uartectx back to ifopened, password still set
ccdopen baz # still requires physical presence
ccdset opennolongpp always
ccdlock
ccdopen baz # no pp required
ccdset unlocknoshortpp unlesslocked
ccdlock
ccdopen baz # short pp sequence required (3 taps)
ccdlock
ccdunlock baz # short pp sequence required
ccdopen baz # pp not required
ccdset unlocknoshortpp always
ccdlock
testlab open # access denied
testlab enable # access denied
ccdunlock baz
testlab open # access denied
testlab enable # access denied
ccdopen baz
testlab enable # requires short pp
ccdinfo # flags 1
ccdreset
ccdinfo # no password, flags=1, caps all default
ccdlock
testlab open
ccdinfo # opened
testlab disable # requires short pp; let it time out
ccdinfo # still opened, flags=1
ccdlock
ccdoops # backdoor in CR50_DEV images to force-reset CCD
ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccdreset rma
ccdinfo # flags = 0x400000, everything but Cr50FullConsole always
ccdreset # back to flags=0, all default
Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9
Reviewed-on: https://chromium-review.googlesource.com/569439
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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We're going to add more rwsig-related functions, and adding them
to rsa.h seems increasingly incorrect.
BRANCH=none
BUG=b:35587171
TEST=make buildall -j
Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2
Reviewed-on: https://chromium-review.googlesource.com/468708
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Change-Id: I35f0aa87f5ab1371dbd8b132f22b9d0044358223
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450859
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450858
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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All boards have been transitioned to charge_state_v2.c
So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and
CONFIG_CHARGER_TIMEOUT_HOURS can be removed
BUG=chrome-os-partner:36272
TEST=make -j buildall
BRANCH=none
Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a
Reviewed-on: https://chromium-review.googlesource.com/435467
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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