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* Revert "Merge remote-tracking branch cros/main into ↵factory-brya-14909.124.B-mainYH Lin2022-12-051-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | factory-brya-14909.124.B-main" This reverts commit 184d13e77614be3be5374d3fef9d1edf66ec8687. Reason for revert: broken build due to ec-utils. Original change's description: > Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main > > Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file > baseboard/brya/relevant-paths.txt factory-brya-14909.124.B-main > > Relevant changes: > > git log --oneline 19d4d68ffa..aa40b859b3 -- baseboard/brya board/agah > board/anahera board/banshee board/brya board/crota board/felwinter > board/gimble board/kano board/mithrax board/osiris board/primus > board/redrix board/taeko board/taniks board/vell board/volmar > driver/bc12/pi3usb9201_public.* driver/charger/bq25710.* > driver/ppc/nx20p348x.* driver/ppc/syv682x_public.* > driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.* > driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake* > include/intel_x86.h power/alderlake* power/intel_x86.c > util/getversion.sh > > e6da633c38 driver: Sort header files > 234a87ae2d tcpci: Add FRS enable to driver structure > a56be59ccd tcpm_header: add test for tcpm_dump_registers > 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT > e420c8ff9a marasov: Modify TypeC and TypeA configuration. > 43b53e0045 Add default implementation of board_set_charge_limit > b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT > f1b563c350 baseboard: Sort header files > 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70 > ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT > 8f89f69a5b crota: disable lid angle sensor for clamshell > > BRANCH=None > BUG=b:260630630 b:163093572 b:259002141 b:255184961 b:259354679 > BUG=b:247100970 b:254328661 > TEST=`emerge-brya chromeos-ec` > > Force-Relevant-Builds: all > Change-Id: I0ecfa0e6af68631283c7a9e8f1afb9d827176c62 > Signed-off-by: YH Lin <yueherngl@google.com> Bug: b:260630630 b:163093572 b:259002141 b:255184961 b:259354679 Bug: b:247100970 b:254328661 Change-Id: Ia14942d1bd6a502062399d77cb59d1f4b549b2c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077247 Auto-Submit: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: YH Lin <yueherngl@chromium.org>
* core/cortex-m0: Use EC's builtins over compiler-rtTom Hughes2022-11-151-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When examining code size, it appears that the builtins in compiler-rt (especially for division) are larger than the ones in the EC source code: armv7m-cros-eabi-readelf -s ./build/servo_v4p1/RW/ec.RW.elf | sort -k3 -n -r __udivsi3: 418 bytes __aeabi_uidiv: 418 bytes Compiling with clang before this change: RO: 15560 bytes in flash and 864 bytes in RAM still available on servo_v4p1 RW: 848 bytes in flash and 7144 bytes in RAM still available on servo_v4p1 After this change: RO: 16456 bytes in flash and 864 bytes in RAM still available on servo_v4p1 RW: 1232 bytes in flash and 7144 bytes in RAM still available on servo_v4p1 BRANCH=none BUG=b:256193799 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I21eab7fba10795e7821be79d141002a009d396a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4021114 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* tree: Remove CONFIG_SOFTWARE_PANICTom Hughes2022-10-121-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | It's always enabled in the core/<core>/core_config.h files. The following script demonstrates that it's enabled in all boards: for board in `make print-boards`; do make print-configs board="${board}" | grep -q CONFIG_SOFTWARE_PANIC if [ $? -ne 0 ]; then echo "${board} failed" exit 1 fi done BRANCH=none BUG=none TEST=make buildall Cq-Depend: chromium:3943248 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: If683b244f17b48bedf3699f2b24e83b5ad6e849e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3933255 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/cortex-m0: Use compiler_rt version of clz and ctzTom Hughes2021-11-031-1/+6
| | | | | | | | | | | | | | | | | | | | | | | Use __clzsi2 and __ctzsi2 from compiler_rt instead of our own version. Using the compiler_rt versions result in a slightly smaller image. servo_micro before this change: RO: 18744 bytes in flash remaining RW: 23192 bytes in flash remaining servo_micro after this change: RO: 18808 bytes in flash remaining RW: 23256 bytes in flash remaining BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=servo_micro TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibc19a3670127dde211fb20d247c1284d0aec5f61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3199739 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-05-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Add software CTZ implementation when needeedGwendal Grignou2017-11-161-1/+2
| | | | | | | | | | | | | | | | | CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or nds32. Used in ST sensor drivers. BUG=none BRANCH=none TEST=compile Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767609 Commit-Ready: Ely Vazquez <nadia198877@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m*: Save panicinfo on non-exception panicsShawn Nematbakhsh2015-02-181-0/+1
| | | | | | | | | | | | | | | | | | Make non-exception "software" panics such as stack overflow and assert failure save a panic log. Log the panic type in r4, and misc. panic data in r5 so that panic reasons can be distinguished. BUG=chrome-os-partner:36744 TEST=Manual on samus_pd. Run 'crash divzero' then 'panicinfo' after reboot. Verify that panic info is printed with "r4 :dead6660". Trigger stack overflow, verify that panic info is printed with "r4 :dead6661". BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I5f7a8eb0a5c2ac5799d29bb241deb24fabf38f68 Reviewed-on: https://chromium-review.googlesource.com/249912 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Add Cortex-M0 core supportVincent Palatin2014-03-111-0/+16
The Cortex-M0 core is based on ARMv6-M instruction set rather than ARMv7-M as Cortex-M3 and M4. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run console on STM32F072, and pass all available unit-tests on target. Change-Id: I9bdf6637132ba4a3e739d388580a72b4c84e930e Reviewed-on: https://chromium-review.googlesource.com/188982 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
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