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* config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPIKeith Short2021-11-191-1/+1
| | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842 Tested-by: Michał Barnaś <mb@semihalf.com>
* core/cortex-m: Include subsections in bssTom Hughes2021-11-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The FPC library used on bloonchipper has bss subsections (e.g., bss.sensor_config). These subsections must be put within __bss_start and __bss_end or the initialization performed in core/cortex-m/init.S will not clear it, resulting in potentially random values in the variables rather than zero. Before this change: arm-none-eabi-objdump -h build/bloonchipper/RW/ec.RW.elf Sections: Idx Name Size VMA LMA File off Algn 0 .text 00022eee 08060000 08060000 00010000 2**5 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .rodata 00008ab8 08082ef0 08082ef0 00032ef0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .bss 000134b0 20000000 20000000 00050000 2**3 ALLOC ... 13 .bss.sensor_config 00000004 200134f0 200134f0 00050000 2**2 ALLOC ... 22 .data 000000b8 20013508 0808b9a8 00043508 2**3 CONTENTS, ALLOC, LOAD, DATA ... After this change: arm-none-eabi-objdump -h build/bloonchipper/RW/ec.RW.elf Sections: Idx Name Size VMA LMA File off Algn 0 .text 00022eee 08060000 08060000 00010000 2**5 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .rodata 00008ab8 08082ef0 08082ef0 00032ef0 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .bss 00013508 20000000 20000000 00050000 2**3 ALLOC 3 .data 000000b8 20013508 0808b9a8 00043508 2**3 CONTENTS, ALLOC, LOAD, DATA ... BRANCH=none BUG=b:172020503, b:201113851 TEST=On dragonclaw with servo_micro attached: > fpenroll > fpmatch TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I9a9187e05b8e734f9513ff27c49571ccb12d86df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219872 Reviewed-by: Patryk Duda <patrykd@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* core/cortex-m: Use symbolic name instead of r0Tom Hughes2021-11-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This assembly is supposed to force the compiler to use r0 for pregs and r12 for pstack. When compiling with clang, it uses r12 for pregs and r0 for pstack, so the "stmia r0" instruction is using the wrong value. Instead of assuming that pregs will be in r0 and pstack will be in r12, just use the symbolic name ("pregs") with the stmia instruction. This generates the correct behavior regardless of whether pregs or pstack use r0 or r12. With gcc, the generated assembly for exception_panic after this change removes the "mov r0, r0" instruction and adds a nop at the end: 00000000 <exception_panic>: 0: 480e ldr r0, [pc, #56] ; (3c <exception_panic+0x3c>) 2: f8df c03c ldr.w ip, [pc, #60] ; 40 <exception_panic+0x40> ; No more "mov r0, r0" here 6: f3ef 8109 mrs r1, PSP a: f3ef 8205 mrs r2, IPSR e: 466b mov r3, sp 10: 05d6 lsls r6, r2, #23 12: bf1c itt ne 14: 2400 movne r4, #0 16: 2500 movne r5, #0 18: f04f 0600 mov.w r6, #0 1c: f04f 0700 mov.w r7, #0 20: f04f 0800 mov.w r8, #0 24: f04f 0900 mov.w r9, #0 28: f04f 0a00 mov.w sl, #0 2c: f04f 0b00 mov.w fp, #0 30: e880 4ffe stmia.w r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 34: 46e5 mov sp, ip 36: f7ff fffe bl 0 <exception_panic> 3a: bf00 nop ; adds nop instruction BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=bloonchipper TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I150d685bde701171630ae02b16e6050e1e0e77a6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213606 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* task: Use bool for truthy return typesTom Hughes2021-11-091-2/+2
| | | | | | | | | | | | | | | | Using bool makes it clear that the function returns "true" or "false", rather than any integer. It also avoids the need to use "!!" to set the value to 0 or 1, since the compiler ensures that "bool" is always a 0 or 1, even if another value is assigned. BRANCH=none BUG=b:172020503 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I164e5c03c23fa2f0ffb61e87f5613e080814ce10 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262593 Reviewed-by: Keith Short <keithshort@chromium.org>
* tree: Make DECLARE_IRQ routine staticTom Hughes2021-11-081-1/+1
| | | | | | | | | | | | | For consistency, make all IRQ handler routines static. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I43dc4dd0a8cd593d6eb761768acc5c7b6b95e22b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227265 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/cortex-m[0]: Enable "-Oz" when using clangTom Hughes2021-10-291-1/+3
| | | | | | | | | | | | | | | | | | | | | | "-Oz" is like "-Os" (and thus "-O2"), but reduces code size further. dartmonkey, clang, -Os: RO: 733500 flash remaining RW: 979488 flash remaining dartmonkey, clang, -Oz: RO: 737980 flash remaining RW: 984776 flash remaining BRANCH=none BUG=b:172020503 TEST=make buildall TEST=CC=clang make BOARD=dartmonkey Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ia787845ffdeff26134162007a621b902bbc0d051 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3199737 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Add support for building dartmonkey firmware with clangTom Hughes2021-10-251-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default all builds will use gcc. To build with clang, set the environment variable CC=clang. At this point only dartmonkey has been tested with clang. BRANCH=none BUG=b:172020503 TEST=Using icetower, Segger J-Trace, and servo micro: make BOARD=dartmonkey -j ./flash_jlink.py -b dartmonkey -i ./build/dartmonkey/ec.bin --remote 127.0.0.1:2551 => console on icetower works TEST=CC=clang make BOARD=dartmonkey -j ./flash_jlink.py -b dartmonkey -i ./build/dartmonkey/ec.bin --remote 127.0.0.1:2551 => console on icetower works TEST=make buildall -j TEST=CC=clang make BOARD=dartmonkey tests -j TEST=make BOARD=dartmonkey tests -j TEST=./util/compare_build.sh -b all -j 120 => MATCH Change-Id: Ib7c067d0ebe0561becfd70373216adb445501f94 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1474577 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* tree: Remove .bss.slowTom Hughes2021-10-191-9/+0
| | | | | | | | | | | | | | | | | | The config option to enable .bss.slow was removed in commit b224441aaaa5dd08274811d65bb795b4abc231d8 because the option was only used with kunimitsu, which was removed from the EC codebase a long time ago. Remove the reference in the linker maps to complete the cleanup. BRANCH=none BUG=b:172020503, b:172221339 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibc519f9974cb26e6d15180e2ce0c359867ced1ac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219263 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* tree: Make all console commands staticTom Hughes2021-10-151-1/+1
| | | | | | | | | | | | | | Almost all of the console commands were already static. This change makes all of them static for consistency. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0ac46358b6fbafa65504c648ce4de0365cdbf723 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3224372 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/cortex-m: Invert if statement for readabilityTom Hughes2021-10-151-3/+3
| | | | | | | | | | | | BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I39f9d35b22d25c923a768bf86b3a16413b9f0a4b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219871 Reviewed-by: Keith Short <keithshort@chromium.org>
* core/cortex-m: Use original __data_lma_start when compiling with gccstabilize-14285.B-mainTom Hughes2021-10-151-0/+7
| | | | | | | | | | | | | | | | | | | | https://crrev.com/c/3169964 changed __data_lma_start from "." to LOADADDR(.data) to fix dartmonkey when compiling with clang. This changed the LMA address on some boards, such as voxel. Even though the new address looks correct (matches start of .data section), we are seeing an exception on voxel during startup. For now, keep clang and gcc separate until we can diagnose the issue. BRANCH=none BUG=b:172020503, b:202863352 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I8313210c89559a6159f311821a18e7b310a3ada6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3224378 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* core/cortex-m[0]: Work around clang inline-asm warningTom Hughes2021-10-131-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns that we're clobbering a reserved register: inline asm clobber list contains reserved registers: R7 [-Werror,-Winline-asm]. According to https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Clobbers-and-Scratch-Registers: When the compiler selects which registers to use to represent input and output operands, it does not use any of the clobbered registers. Before this change, the only remaining registers for the compiler to use to hold the values represented by the symbolic names "pregs" and "pstack" are R0 and R12. After this change, this still holds on clang, since it won't clobber the reserved register R7 even if it's not on the clobber list. BRANCH=none BUG=b:172020503 TEST=make V=1 CC=arm-none-eabi-clang BOARD=elm TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I5182ef24f4465d68c97f4160a45cd479fe52e017 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193273 Reviewed-by: Keith Short <keithshort@chromium.org>
* core/cortex-m: Fix __data_lma_startTom Hughes2021-10-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this change, the code compiles and links when using clang, but does not boot. __data_lma_start should be the LMA address of the .data section and is used in core/cortex-m/init.S to copy the data from the LMA address into the VMA address (flash to RAM). Before this change, examining the smap and map files shows that __data_lma_start (0x0800bcdc) does not match the LMA address of the .data section (0x800bce0): build/dartmonkey/RO/ec.RO.smap: 0800bcdc R __data_lma_start build/dartmonkey/RO/ec.RO.map VMA LMA Size Align Out In Symbol 24003538 800bce0 68 8 .data After the change, the LMA addresses match and the board boots correctly: build/dartmonkey/RO/ec.RO.smap: 0800bce0 A __data_lma_start build/dartmonkey/RO/ec.RO.map VMA LMA Size Align Out In Symbol 24003538 800bce0 68 8 .data When comparing the behavior of this change with gcc, we find that many boards match, but some do not (see TEST line). Looking at a few of the boards that do not match, there appears to be a one-byte difference in the RO portion. Investigating further on voxel: Original address from build/voxel/RO/ec.RO.smap: 100a2e20 R __data_lma_start New address from build/voxel/RO/ec.RO.smap after applying this change: 100a2e60 A __data_lma_start In both cases, when using objdump on RO.elf, .data's LMA address starts at 100a2e60, so this change appears to be correct: arm-none-eabi-objdump -h /tmp/compare_build.Ltgh/ec-53a576c00f1b0d609d23a68a83e0340a14ee8fe5/build/voxel/RO/ec.RO.elf Sections: Idx Name Size VMA LMA File off Algn 3 .data 00000538 200b8368 100a2e60 00058368 2**3 CONTENTS, ALLOC, LOAD, DATA arm-none-eabi-objdump -h /tmp/compare_build.Ltgh/ec-f0c36b07d9efa2f5b12e5de7e794d723e8468e26/build/voxel/RO/ec.RO.elf Sections: Idx Name Size VMA LMA File off Algn 5 .data 00000538 200b8368 100a2e60 00058368 2**3 CONTENTS, ALLOC, LOAD, DATA BRANCH=none BUG=b:172020503, b:202863352 TEST=make buildall TEST=make CC=arm-none-eabi-clang BOARD=dartmonkey TEST=./util/compare_build.sh -b all -j 150 All boards match, EXCEPT: adlrvpp_npcx akemi aleena ambassador anahera atlas berknip bloog bobba boldar brask brya bugzzy cappy2 careena casta chronicler coachz collis copano coral corori dalboz delbin dewatt dirinboz dood dooly dratini driblee drobit drobit_ecmodeentry eldrid elemi endeavour eve ezkinil felwinter fizz fleex foob garg genesis gimble grunt gumboz guybrush hatch helios herobrine_npcx9 homestar jinlon kano karma kindred kingoftown kohaku lalala lazor liara lick lindar lux madoo magolor marzipan meep metaknight moonbuggy morphius mrbland mushu nami nautilus nightfury nipperkin nocturne npcx7_evb npcx9_evb npcx_evb_arm npcx_evb nuwani palkia pazquel phaser pompom poppy primus puff quackingstick rammus redrix reef sasuke scout shuboz soraka stryke taeko treeya trembyle trogdor vilboz voema volet volteer_npcx797fc voxel voxel_ecmodeentry voxel_npcx797fc waddledoo2 woomax wormdingler yorp Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Icd3df244e202a50a577f21ffa4f8202eb3f8b8d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169964 Reviewed-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* core/cortex-m: Fix RW image alignment when using clang (lld)Tom Hughes2021-10-131-3/+1
| | | | | | | | | | | | | | | | | | | | | This change forces the LMA and VMA to start immediately after the .data section; both LMA and VMA are forced to be equal. The change removes the BYTE(0xFF), since lld will allocate space for this byte and throw off the alignment. The ASSERT line verifies that the __image_size is still correctly aligned when building with both gcc and clang. BRANCH=none BUG=b:172020503 TEST=make buildall TEST=make CC=arm-none-eabi-clang BOARD=dartmonkey Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I00d4e8f346232d1c5b8b04d397459760976a8a8b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169965 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* core/cortex-m[0]: Replace calculation with variable for readabilityTom Hughes2021-10-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | PANIC_DATA_PTR is defined as ((struct panic_data *)CONFIG_PANIC_DATA_BASE) which is CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE Instead of doing that calculation again, just re-use PANIC_DATA_PTR, which more clearly shows the relationship between pdata_ptr and pstack_addr. As indicated by the TEST line, this results in no change to the generated code. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I52f769b388dd47269b74d70a651868fcd6c339b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213285 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core: Fix flash size calculation when linking with lld (clang)Tom Hughes2021-10-111-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The map file generated by lld has a different format than the gnu linker (ld). (We save this map file into build/<board>/<image>/ec.<image>.map during the build.) Instead of trying to parse the different formats in the .map file, use the .smap file (the output of "nm"), which has the values of the symbols and has the same format whether using lld or ld. We need to add a new "__flash_size" symbol so that we can use that symbol to get the size from the .smap. This add flash sizes to a few boards that previously didn't have it: asurada_scp, cherry_scp, and kukui_scp, since the previous logic was always looking for FLASH and these use IROM. BRANCH=none BUG=b:172020503 TEST=make buildall -j TEST=make CC=arm-none-eabi-clang BOARD=elemi TEST=bcompare build_before_change build_after_change => only difference between space_free_flash.txt and space_free_ram.txt files in the two builds is that this change adds the space_free_flash.txt files for asurada_scp, cherry_scp, and kukui_scp. Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I7c64b6ba9bceeeb4044559188c1c1bebbf60471d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179314 Reviewed-by: Keith Short <keithshort@chromium.org>
* tree: Remove CONFIG_RO_HEAD_ROOM and CONFIG_RW_HEAD_ROOMTom Hughes2021-10-061-6/+0
| | | | | | | | | | | | | | | | | CONFIG_RO_HEAD_ROOM and CONFIG_RW_HEAD_ROOM are always defined as 0, so remove the values and associated code in order to simplify the code and improve readability. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie11d23befda674cc15dda9a2d66b9c43ea22d49e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3205489 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* core: Add assert to check alignmentTom Hughes2021-10-011-0/+5
| | | | | | | | | | | | | | | | Assert that the RW image size padding adding results in correct alignment. This assertion will make it easier to verify future clang changes. BRANCH=none BUG=b:172020503, b:188117811 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibdc6feaf31cf271f67594ae1e519272fd9a88cd4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179317 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* core/cortex-m: Disable warning in vecttable.c when building with clangTom Hughes2021-09-231-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | The vecttable logic explicitly routes unused IRQs to IRQ_UNUSED_OFFSET, and then assigns it to "null" at the very end. The result is something like: [8] = __attribute__((used, weak, alias("default_handler"))) irq_55_handler(void); [8] = __attribute__((used, weak, alias("default_handler"))) irq_56_handler(void); ... [8] = (void*)0 This is intentional so that it works with a varying values for CONFIG_IRQ_COUNT. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3ba4eeaa46cd2c50c65c922f4c0c463ce1bb585e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172038 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* cortex-m/panic: Introduce CONFIG_PANIC_STRIP_GPR optionPatryk Duda2021-09-161-1/+39
| | | | | | | | | | | | | | | | | | | | | | | If set, this option will prevent saving General Purpose Registers during panic. When software panic occurs, R4 and R5 will be saved, because they contain additional information about panic. This should be enabled on boards which are processing sensitive data and panic could cause the leak. BUG=b:193408648 BRANCH=none TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo' to check what was saved. When CPU exception occurred registers R0-R12 should be set to 0. In case of software panic, R4 and R5 can contain panic reason and additional information. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m/task: Check if interrupts are enabled before switching taskPatryk Duda2021-09-061-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switching task with disabled interrupts leads to Forced Hard Fault on Cortex-M3/M4/M7 because: - SVCall exception have configurable priority (full list can be found at 2.4.2 Exception types PM0253 Rev 5 p.40) - We are using 'cpsid i' to disable interrupts. This instruction sets PRIMASK bit (3.12.2 CPS PM0253 Rev 5 p.176) - When PRIMASK bit is set, all exceptions with configurable priority are disabled (PM0253 Rev 5 p.25), so SVCall is masked too - SVCall is escalated to Forced Hard Fault because "A fault occurs and the handler for that fault is not enabled" (PM0253 Rev 5 p.48) If Hard Fault is inevitable, it will be a good idea to catch this earlier. It will save time spent debugging why Forced Hard Fault happens. In functions responsible for enabling, disabling or making task ready we postpone task switch when interrupts are disabled BUG=b:190597666 BRANCH=none TEST=Compile and flash EC on boards with Cortex-M3/M4/M7 and make sure that it works properly. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I50976154b0cf0307c5334f6f03e4b3bc137a4ffc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953228 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Provide 'is_interrupt_enabled' function for all coresPatryk Duda2021-09-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function that will provide information if interrupts are enabled. This information will be used to fix shortcomings in common code for UART buffering and usleep(). BUG=b:190597666 BRANCH=none TEST=make -j buildall TEST=make runhosttests TEST=Note for running tests: this patch only adds function implementation so, to test this it is necessary to add some code which uses the function eg. console command which prints information if interrupt is enabled. Minute-ia core: It is necessary to compile firmware for ISH (Intel Sensor Hub) which is available on drallion board (eg. chromeos6-row1-rack9-host19). Firmware must be placed in /lib/firmware/intel/drallion_ish.bin (partition must be writeable, if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock it, don't forget about reboot). After copying firmware to /lib/firmware/intel/ it is necessary to reboot DUT. After reboot use `ectool --name=cros_ish version` to check if correct version is running. NDS32 core. This core is used in it8320dx chip which is present in ampton (octopus family). EC can be compiled using 'make BOARD=ampton' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which is based on risc-v. EC can be compiled using 'make BOARD=hayato' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Cortex-M, this is the most common core. Just compile EC for platform which contains Cortex-M core (eg. bloonchipper) and test if it works. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* builtin: Add math.hTom Hughes2021-08-311-3/+3
| | | | | | | | | | | | | | | | | | | | Add a "math.h" to "builtin" and rename "math.h" in the "core" directories to "fpu.h". "builtin" is the directory containing headers that mirror those in the standard library and is used for device builds. The host builds exclude the "builtin" directory and use the standard library. Without this change, building host tools such as "ectool" and attempting to include "math.h" would result in incorrectly picking up the "math.h" from the device "core" directory, not the standard library version. BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Id6b2df42cb0ff5ec2cfc07aa8f29861da6804bdf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130625 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cortex-m*: make watchdog code more readableRicardo Quesada2021-07-301-2/+10
| | | | | | | | | | | | | | | | | This CL makes the code more readable by adding comment / defines regarding the meaning of PSP[5] and PSP[6]. BUG=None TEST=make buildall BRANCH=None Change-Id: I0cbe7384e20f0287096624a00b0ec19c0fb7f9bd Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059814 Tested-by: Ricardo Quesada <ricardoq@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* atomic.h: atomic_clear_bits: return previously stored valueTing Shen2021-07-291-2/+2
| | | | | | | | | | | | | | | make the api consistent with other atomic methods BUG=b:192422592 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I6cae4d521b44706cf7f44c669bf6964a08855b4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058080 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cortex-m/ec.lds.S: Add padding to manage RW image sizeEthan Huang2021-07-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431 used in Munna), RW image size is not always 8-byte alignment which leads to the failure from flash_range_ok and therefore "EC sync update RW proecess" fails. Here is the proposal of RW image size alignment with CONFIG_FLASH_WRITE_SIZE. 1. Add output section .rw_image_size_alignment for padding 2. Expose new __image_size for hash afterward 3. Make output senction .rw_image_size_alignment !CONFIG_CHIP_INIT_ROM_REGION guarded BRANCH=main BUG=b:188117811 TEST=make buildall + checking symbols (execpt __image_size) listed in ec.R{O,R}.smap for all boards stay the same Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416 Signed-off-by: Ethan Huang <ethan.huang@stmicro.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32/system: Disable caches before rebootPatryk Duda2021-06-102-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* cortex-m/watchdog: Flush and invalidate D-cache while handling watchdogPatryk Duda2021-06-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with RO reporting 'sysjump' reset cause, but not 'watchdog' after issuing 'crash watchdog' command. Also, problem with missing task ID and PC in saved panic data was fixed too. These problems come from not flushing cache before reset occurs. When cache is enabled, it's not guaranteed that all memory changes will be saved in RAM. After reboot, cache is invalidated, so some of memory changes will be lost. In this case, 'magic' field from jump_data structure was not zeroed and part of panic data was missing. It caused RO to report sysjump after watchdog was triggered, and missing 'watchdog' reset cause (RO used reset cause from jump data). BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'crash watchdog'. Make sure that RO reports 'watchdog' reset cause. After sysjump to RW check panic data using 'panicinfo' command. Especially the following: - R4 register (crash reason) should be set to 0xdead6664 (watchdog) - R5 register (info) should be set to PC - PROCESS EXCEPTION value should be set to task ID Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ie8d861e5a07b58140445aeaa191cc0098618401b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923504 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/panic: Flush D-cache after panic data is filledPatryk Duda2021-06-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi After writing panic information it is good to flush cache to make sure that all changes are in RAM. Without this, 'panicinfo' will report incorrect values after reboot. BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, use 'crash' command to trigger panic (do not use 'crash watchdog' it uses different path). Make sure that after sysjump to RW panic data contains correct information. Panic data can be dumped using 'panicinfo' command. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Iabe2b1de00683d95f55a3124b46dfa600f8ac0bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923503 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* panic.c: force sync before reenabling bus faultsJosie Nordrum2021-05-111-0/+5
| | | | | | | | | | | | | | | | | | Force a sync between data and instruction pipelines before allowing bus faults. Remove sync from flash-stm32h7.c BRANCH=None BUG=b:157692395 TEST=tested with crrev.com/c/2576799 Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Id67324191b4447d9be10c0b5aecc87620aa69d1d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706039 Tested-by: Josie Nordrum <josienordrum@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Josie Nordrum <josienordrum@google.com> Auto-Submit: Josie Nordrum <josienordrum@google.com>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSJeremy Bettis2021-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac1d81e1430dbfbfba1376a23ab19dfa845d7ef. The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=chromium:1202406,b:180980668 TEST=make -j16 runhosttests buildall && zmake testall && \ /mnt/host/source/src/platform/ec/zephyr/firmware_builder.py --metrics \ /tmp/tmplt8ty8ci test ; echo $? BRANCH=none Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I5b5e58b30d936b5232e049827f458d9a2ed06340 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855320 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "config: rename CONFIG_FLASH to CONFIG_FLASH_CROS"stabilize-13935.B-mainJack Rosenthal2021-04-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a. Reason for revert: responsible for CQ failures (crbug.com/1202406) BUG=chromium:1202406 BRANCH=none TEST=CQ Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Original change's description: > config: rename CONFIG_FLASH to CONFIG_FLASH_CROS > > The config name collides with the same config name in zephyr. > > Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to > CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig > side. > > BUG=b:180980668 > TEST=make buildall > BRANCH=none > > Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 > Signed-off-by: Eric Yilun Lin <yllin@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 > Tested-by: Eric Yilun Lin <yllin@google.com> > Reviewed-by: Keith Short <keithshort@chromium.org> > Commit-Queue: Keith Short <keithshort@chromium.org> Bug: b:180980668 Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274 Auto-Submit: Jack Rosenthal <jrosenth@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-231-3/+3
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Hooks: Add HOOK_CHIPSET_HARD_OFFDiana Z2021-03-181-0/+4
| | | | | | | | | | | | | | | Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry to the G3 power state. BRANCH=None BUG=b:166787955,b:167996216,chromium:1045209 TEST=make -j buildall, runs on waddledee with no linking errors Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/m0: Add Debug Halting Control and Status RegisterTom Hughes2021-02-233-1/+50
| | | | | | | | | | | | | | | | | | | | | For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR" in the ARMv6-M Architecture Reference Manual. For other Cortex-M, see "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M Architecture Reference Manual or https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register. BRANCH=none BUG=b:180144572 TEST=Using Segger J-Trace Pro with icetower v0.1, verify debugger_is_connected is true when debugger is attached and false otherwise Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748fc26c0db4351be5a83086fdb843e5651b5425 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713753 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/cortex-m/mpu.c does not compileDenis Brockus2021-02-051-1/+2
| | | | | | | | | | | | | | | | | Fix for loop to be compatible with the tools used in the builders BUG=chromium:1175163, chromium:1175181 BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ic4d6f1b8aea0e20391eeb0d9496275289a7e21fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678794 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jae Hoon Kim <kimjae@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-141-8/+4
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m mpu: support configuring regions with difficult alignmentPeter Marheine2020-12-111-59/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing configuration code assumes that provided addresses are at least as aligned as the requested size, which is not true on NPCX797WC (and likely others) where RAM regions are only 64k-aligned but have larger sizes (like 256k). Use a new greedy approach to configuring the MPU which handles these situations corrently: for any given request take the largest possible chunk from the bottom of the memory region (subject to size and address alignment). Maximize the space by aggressively using MPU subregions- this means that in many well-aligned situations this algorithm selects a larger region than the requested size and enables one subregion, but in more difficult situations it is capable of enabling subregions with more exotic positions. BUG=b:169276765 BRANCH=zork TEST=With a test harness to print out computed configurations, manually verified the correctness of a variety taken from real chip configurations (request first, MPU region(s) indented): 0x20000000 size 0x1000 # stm32f03x 0x20000000 size 0x8000 srd fe 0x20000000 size 0x2000 # stm32f03x 0x20000000 size 0x10000 srd fe 0x20000000 size 0x2800 # stm32l100 0x20000000 size 0x4000 srd e0 0x20000000 size 0x4000 # stm32f412 0x20000000 size 0x20000 srd fe 0x80000 size 0xc000 # it8320 0x80000 size 0x20000 srd f8 0xff200000 size 0xa0000 # ish5p4 0xff200000 size 0x100000 srd e0 0x200b0000 size 0x20000 # npcx797wb 0x20080000 size 0x80000 srd e7 0x10070000 size 0x40000 # npcx797wb 0x10000000 size 0x80000 srd 7f 0x10080000 size 0x80000 srd f8 0x200c0000 size 0x10000 # npcx796f 0x20080000 size 0x80000 srd ef 0x10090000 size 0x30000 # npcx796f 0x10080000 size 0x80000 srd f1 0x10090000 size 0x20 0x10090000 size 0x100 srd fe Further verified MPU configuration with the new algorithm succeeds on Dalboz, and test/mpu.c passes on Dragonclaw. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I71d8e2b37c7e20fc7a39166b90eea0b7f7ebcf43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2434601 Reviewed-by: Edward Hill <ecgh@chromium.org>
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-022-2/+2
| | | | | | | | | | | | | | | | | Rename atomic_read_clear to atomic_clear to be consistent with the rest of the atomic functions, which return the previous value of the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* atomic: remove deprecated atomic functionsDawid Niedzwiecki2020-10-301-64/+0
| | | | | | | | | | | | | | Remove deprecated_atomic_* functions since only atomic_* are now used. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I6b25cc81aec126662ed779cf0f9309dcb77a754e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505142 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-15/+13
| | | | | | | | | | | | | | | | | | | | | | | It is done as a part of porting to Zephyr. Since the implementation of atomic functions is done for all architectures use atomic_* instead of deprecated_atomic_*. Sometimes there was a compilation error "discards 'volatile' qualifier" due to dropping "volatile" in the argument of the functions, thus some pointers casts need to be made. It shouldn't cause any issues, because we are sure about generated asm (store operation will be performed). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949 Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* core/cortex-m: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. The current state of ATOMIC_OP macro is not designed to return such value so instead of reworking it or writing new custom asm code just use builtin functions. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Iccd7a4d674601271f11f88834c8b2db08c537534 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428945 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-062-9/+9
| | | | | | | | | | | | | | | | | | Change the name of atomic_clear to atomic_clear_bits to make to name more clear - the function clears only selected bits, but the name may suggest that it clears the whole variable. It is done as a part of porting to Zephyr, where atomic_clear zeros the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I7b0b47959c6c54af40f61bca8d9baebaa0375970 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428943 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: support enhanced PSL functions in npcx9CHLin2020-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. In npcx7, the PSL (hibernation) wakeup source only can come from physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer) module is introduced to support wakeup from a configurable timeout. 2. support PSL wakeup from the VCC1_RST pin. This function is disabled by default and enabled (and locked) in the firmware in the npcx9 A1 chip. In the npcx9 A2 chip, this function is enabled (and locked) by booter. 3. Support pulse mode and open drain (if pulse mode is enabled) for PSL_OUT pin. 4. support one PSL general-purpose output pin which is powered by VSBY. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds. make sure the reset cause in the console is "power-on hibernate rtc-alarm" TEST="hibernate"; check EC wakes up from hibernate after pressing VCC1_RST button on the internal test board. Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1 power; check EC can wake up from hibernate with any input event. Test=configure the level of PSL_GPO before hibernation; check the level is kept after entering hibernation. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* cortex-m/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-9/+17
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Id4099d2a205f5e6118e83514dc4b88c980054ea9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381710 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-292-18/+29
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* coretex-m: fix __image_size value in linker scriptCaveh Jalali2020-09-251-0/+6
| | | | | | | | | | | | | | | | | | | | | This fixes a regression introduced by chromiun:2325768 that broke software sync and forced recovery mode due to an incorrect EC image size value when CONFIG_CHIP_DATA_IN_INIT_ROM is used. also, __image_size was set twice in the linker script with the latter taking precedence when CONFIG_CHIP_INIT_ROM_REGION is enabled. Made the 1st occurrence conditional to avoid confusion. BUG=none BRANCH=none TEST=EC console "hash" command now reports the correct image size and we no longer end up in recovery due to software sync. Change-Id: Ic0fb405f6918bdfa467be5919eed91eb17ef7c2a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428566 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* cortex-m: support locating .data section in ROM residentKeith Short2020-09-242-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize the RO and RW images so the .data section remains in flash and is not copied into code RAM by the bootloader. This frees effective flash space for more code in the .text and .rodata sections. The EC initialization is changed to copy the .data section directly from flash into data RAM so the runtime access of objects linked into .data are unchanged. This is controlled with a new config option CONFIG_CHIP_DATA_IN_INIT_ROM. This option is automatically enabled when the board enables the ROM resident section with CONFIG_CHIP_INIT_ROM_REGION and the EC chip supports memory mapped access to flash (CONFIG_MAPPED_STORAGE). On Volteer this change saves 1656 bytes of RW flash space. BUG=none BRANCH=none TEST=make buildall TEST=Run "ectool motionsense lid_angle" on Volteer. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2eff814ad240dfb46bfba400b83d78d1f69a8310 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325768 Reviewed-by: caveh jalali <caveh@chromium.org>
* cortex-m: Fix flash size calculation boards without flashKeith Short2020-08-181-25/+25
| | | | | | | | | | | | | | | | | | CL:2334389 broke the make debug output for the kukui_scp and flapjack_scp boards. The actual EC image was not affected. This change also cleans up the #ifdef usage to consolidate assignment of the output sections into one place. BUG=b:164696005 BRANCH=none TEST=make buildall TEST=Run "util/compare_board.sh -b cortex-m" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If69cb492e2aa5f1181e27be24ee66f63cc74ff62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359492 Reviewed-by: caveh jalali <caveh@chromium.org>
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