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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-0526-4146/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* core/cortex-m: Disable warning in vecttable.c when building with clangTom Hughes2021-09-231-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | The vecttable logic explicitly routes unused IRQs to IRQ_UNUSED_OFFSET, and then assigns it to "null" at the very end. The result is something like: [8] = __attribute__((used, weak, alias("default_handler"))) irq_55_handler(void); [8] = __attribute__((used, weak, alias("default_handler"))) irq_56_handler(void); ... [8] = (void*)0 This is intentional so that it works with a varying values for CONFIG_IRQ_COUNT. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3ba4eeaa46cd2c50c65c922f4c0c463ce1bb585e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172038 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* cortex-m/panic: Introduce CONFIG_PANIC_STRIP_GPR optionPatryk Duda2021-09-161-1/+39
| | | | | | | | | | | | | | | | | | | | | | | If set, this option will prevent saving General Purpose Registers during panic. When software panic occurs, R4 and R5 will be saved, because they contain additional information about panic. This should be enabled on boards which are processing sensitive data and panic could cause the leak. BUG=b:193408648 BRANCH=none TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo' to check what was saved. When CPU exception occurred registers R0-R12 should be set to 0. In case of software panic, R4 and R5 can contain panic reason and additional information. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m/task: Check if interrupts are enabled before switching taskPatryk Duda2021-09-061-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switching task with disabled interrupts leads to Forced Hard Fault on Cortex-M3/M4/M7 because: - SVCall exception have configurable priority (full list can be found at 2.4.2 Exception types PM0253 Rev 5 p.40) - We are using 'cpsid i' to disable interrupts. This instruction sets PRIMASK bit (3.12.2 CPS PM0253 Rev 5 p.176) - When PRIMASK bit is set, all exceptions with configurable priority are disabled (PM0253 Rev 5 p.25), so SVCall is masked too - SVCall is escalated to Forced Hard Fault because "A fault occurs and the handler for that fault is not enabled" (PM0253 Rev 5 p.48) If Hard Fault is inevitable, it will be a good idea to catch this earlier. It will save time spent debugging why Forced Hard Fault happens. In functions responsible for enabling, disabling or making task ready we postpone task switch when interrupts are disabled BUG=b:190597666 BRANCH=none TEST=Compile and flash EC on boards with Cortex-M3/M4/M7 and make sure that it works properly. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I50976154b0cf0307c5334f6f03e4b3bc137a4ffc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953228 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Provide 'is_interrupt_enabled' function for all coresPatryk Duda2021-09-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function that will provide information if interrupts are enabled. This information will be used to fix shortcomings in common code for UART buffering and usleep(). BUG=b:190597666 BRANCH=none TEST=make -j buildall TEST=make runhosttests TEST=Note for running tests: this patch only adds function implementation so, to test this it is necessary to add some code which uses the function eg. console command which prints information if interrupt is enabled. Minute-ia core: It is necessary to compile firmware for ISH (Intel Sensor Hub) which is available on drallion board (eg. chromeos6-row1-rack9-host19). Firmware must be placed in /lib/firmware/intel/drallion_ish.bin (partition must be writeable, if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock it, don't forget about reboot). After copying firmware to /lib/firmware/intel/ it is necessary to reboot DUT. After reboot use `ectool --name=cros_ish version` to check if correct version is running. NDS32 core. This core is used in it8320dx chip which is present in ampton (octopus family). EC can be compiled using 'make BOARD=ampton' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which is based on risc-v. EC can be compiled using 'make BOARD=hayato' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Cortex-M, this is the most common core. Just compile EC for platform which contains Cortex-M core (eg. bloonchipper) and test if it works. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* builtin: Add math.hTom Hughes2021-08-311-3/+3
| | | | | | | | | | | | | | | | | | | | Add a "math.h" to "builtin" and rename "math.h" in the "core" directories to "fpu.h". "builtin" is the directory containing headers that mirror those in the standard library and is used for device builds. The host builds exclude the "builtin" directory and use the standard library. Without this change, building host tools such as "ectool" and attempting to include "math.h" would result in incorrectly picking up the "math.h" from the device "core" directory, not the standard library version. BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Id6b2df42cb0ff5ec2cfc07aa8f29861da6804bdf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130625 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cortex-m*: make watchdog code more readableRicardo Quesada2021-07-301-2/+10
| | | | | | | | | | | | | | | | | This CL makes the code more readable by adding comment / defines regarding the meaning of PSP[5] and PSP[6]. BUG=None TEST=make buildall BRANCH=None Change-Id: I0cbe7384e20f0287096624a00b0ec19c0fb7f9bd Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059814 Tested-by: Ricardo Quesada <ricardoq@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* atomic.h: atomic_clear_bits: return previously stored valueTing Shen2021-07-291-2/+2
| | | | | | | | | | | | | | | make the api consistent with other atomic methods BUG=b:192422592 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I6cae4d521b44706cf7f44c669bf6964a08855b4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058080 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cortex-m/ec.lds.S: Add padding to manage RW image sizeEthan Huang2021-07-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431 used in Munna), RW image size is not always 8-byte alignment which leads to the failure from flash_range_ok and therefore "EC sync update RW proecess" fails. Here is the proposal of RW image size alignment with CONFIG_FLASH_WRITE_SIZE. 1. Add output section .rw_image_size_alignment for padding 2. Expose new __image_size for hash afterward 3. Make output senction .rw_image_size_alignment !CONFIG_CHIP_INIT_ROM_REGION guarded BRANCH=main BUG=b:188117811 TEST=make buildall + checking symbols (execpt __image_size) listed in ec.R{O,R}.smap for all boards stay the same Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416 Signed-off-by: Ethan Huang <ethan.huang@stmicro.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32/system: Disable caches before rebootPatryk Duda2021-06-102-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* cortex-m/watchdog: Flush and invalidate D-cache while handling watchdogPatryk Duda2021-06-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with RO reporting 'sysjump' reset cause, but not 'watchdog' after issuing 'crash watchdog' command. Also, problem with missing task ID and PC in saved panic data was fixed too. These problems come from not flushing cache before reset occurs. When cache is enabled, it's not guaranteed that all memory changes will be saved in RAM. After reboot, cache is invalidated, so some of memory changes will be lost. In this case, 'magic' field from jump_data structure was not zeroed and part of panic data was missing. It caused RO to report sysjump after watchdog was triggered, and missing 'watchdog' reset cause (RO used reset cause from jump data). BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'crash watchdog'. Make sure that RO reports 'watchdog' reset cause. After sysjump to RW check panic data using 'panicinfo' command. Especially the following: - R4 register (crash reason) should be set to 0xdead6664 (watchdog) - R5 register (info) should be set to PC - PROCESS EXCEPTION value should be set to task ID Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ie8d861e5a07b58140445aeaa191cc0098618401b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923504 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/panic: Flush D-cache after panic data is filledPatryk Duda2021-06-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi After writing panic information it is good to flush cache to make sure that all changes are in RAM. Without this, 'panicinfo' will report incorrect values after reboot. BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, use 'crash' command to trigger panic (do not use 'crash watchdog' it uses different path). Make sure that after sysjump to RW panic data contains correct information. Panic data can be dumped using 'panicinfo' command. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Iabe2b1de00683d95f55a3124b46dfa600f8ac0bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923503 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* panic.c: force sync before reenabling bus faultsJosie Nordrum2021-05-111-0/+5
| | | | | | | | | | | | | | | | | | Force a sync between data and instruction pipelines before allowing bus faults. Remove sync from flash-stm32h7.c BRANCH=None BUG=b:157692395 TEST=tested with crrev.com/c/2576799 Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Id67324191b4447d9be10c0b5aecc87620aa69d1d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706039 Tested-by: Josie Nordrum <josienordrum@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Josie Nordrum <josienordrum@google.com> Auto-Submit: Josie Nordrum <josienordrum@google.com>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSJeremy Bettis2021-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac1d81e1430dbfbfba1376a23ab19dfa845d7ef. The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=chromium:1202406,b:180980668 TEST=make -j16 runhosttests buildall && zmake testall && \ /mnt/host/source/src/platform/ec/zephyr/firmware_builder.py --metrics \ /tmp/tmplt8ty8ci test ; echo $? BRANCH=none Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I5b5e58b30d936b5232e049827f458d9a2ed06340 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855320 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "config: rename CONFIG_FLASH to CONFIG_FLASH_CROS"stabilize-13935.B-mainJack Rosenthal2021-04-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a. Reason for revert: responsible for CQ failures (crbug.com/1202406) BUG=chromium:1202406 BRANCH=none TEST=CQ Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Original change's description: > config: rename CONFIG_FLASH to CONFIG_FLASH_CROS > > The config name collides with the same config name in zephyr. > > Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to > CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig > side. > > BUG=b:180980668 > TEST=make buildall > BRANCH=none > > Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 > Signed-off-by: Eric Yilun Lin <yllin@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 > Tested-by: Eric Yilun Lin <yllin@google.com> > Reviewed-by: Keith Short <keithshort@chromium.org> > Commit-Queue: Keith Short <keithshort@chromium.org> Bug: b:180980668 Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274 Auto-Submit: Jack Rosenthal <jrosenth@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-231-3/+3
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* Hooks: Add HOOK_CHIPSET_HARD_OFFDiana Z2021-03-181-0/+4
| | | | | | | | | | | | | | | Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry to the G3 power state. BRANCH=None BUG=b:166787955,b:167996216,chromium:1045209 TEST=make -j buildall, runs on waddledee with no linking errors Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/m0: Add Debug Halting Control and Status RegisterTom Hughes2021-02-233-1/+50
| | | | | | | | | | | | | | | | | | | | | For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR" in the ARMv6-M Architecture Reference Manual. For other Cortex-M, see "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M Architecture Reference Manual or https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register. BRANCH=none BUG=b:180144572 TEST=Using Segger J-Trace Pro with icetower v0.1, verify debugger_is_connected is true when debugger is attached and false otherwise Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748fc26c0db4351be5a83086fdb843e5651b5425 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713753 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/cortex-m/mpu.c does not compileDenis Brockus2021-02-051-1/+2
| | | | | | | | | | | | | | | | | Fix for loop to be compatible with the tools used in the builders BUG=chromium:1175163, chromium:1175181 BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ic4d6f1b8aea0e20391eeb0d9496275289a7e21fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678794 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jae Hoon Kim <kimjae@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-141-8/+4
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m mpu: support configuring regions with difficult alignmentPeter Marheine2020-12-111-59/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing configuration code assumes that provided addresses are at least as aligned as the requested size, which is not true on NPCX797WC (and likely others) where RAM regions are only 64k-aligned but have larger sizes (like 256k). Use a new greedy approach to configuring the MPU which handles these situations corrently: for any given request take the largest possible chunk from the bottom of the memory region (subject to size and address alignment). Maximize the space by aggressively using MPU subregions- this means that in many well-aligned situations this algorithm selects a larger region than the requested size and enables one subregion, but in more difficult situations it is capable of enabling subregions with more exotic positions. BUG=b:169276765 BRANCH=zork TEST=With a test harness to print out computed configurations, manually verified the correctness of a variety taken from real chip configurations (request first, MPU region(s) indented): 0x20000000 size 0x1000 # stm32f03x 0x20000000 size 0x8000 srd fe 0x20000000 size 0x2000 # stm32f03x 0x20000000 size 0x10000 srd fe 0x20000000 size 0x2800 # stm32l100 0x20000000 size 0x4000 srd e0 0x20000000 size 0x4000 # stm32f412 0x20000000 size 0x20000 srd fe 0x80000 size 0xc000 # it8320 0x80000 size 0x20000 srd f8 0xff200000 size 0xa0000 # ish5p4 0xff200000 size 0x100000 srd e0 0x200b0000 size 0x20000 # npcx797wb 0x20080000 size 0x80000 srd e7 0x10070000 size 0x40000 # npcx797wb 0x10000000 size 0x80000 srd 7f 0x10080000 size 0x80000 srd f8 0x200c0000 size 0x10000 # npcx796f 0x20080000 size 0x80000 srd ef 0x10090000 size 0x30000 # npcx796f 0x10080000 size 0x80000 srd f1 0x10090000 size 0x20 0x10090000 size 0x100 srd fe Further verified MPU configuration with the new algorithm succeeds on Dalboz, and test/mpu.c passes on Dragonclaw. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I71d8e2b37c7e20fc7a39166b90eea0b7f7ebcf43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2434601 Reviewed-by: Edward Hill <ecgh@chromium.org>
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-022-2/+2
| | | | | | | | | | | | | | | | | Rename atomic_read_clear to atomic_clear to be consistent with the rest of the atomic functions, which return the previous value of the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* atomic: remove deprecated atomic functionsDawid Niedzwiecki2020-10-301-64/+0
| | | | | | | | | | | | | | Remove deprecated_atomic_* functions since only atomic_* are now used. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I6b25cc81aec126662ed779cf0f9309dcb77a754e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505142 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-15/+13
| | | | | | | | | | | | | | | | | | | | | | | It is done as a part of porting to Zephyr. Since the implementation of atomic functions is done for all architectures use atomic_* instead of deprecated_atomic_*. Sometimes there was a compilation error "discards 'volatile' qualifier" due to dropping "volatile" in the argument of the functions, thus some pointers casts need to be made. It shouldn't cause any issues, because we are sure about generated asm (store operation will be performed). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949 Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* core/cortex-m: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. The current state of ATOMIC_OP macro is not designed to return such value so instead of reworking it or writing new custom asm code just use builtin functions. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Iccd7a4d674601271f11f88834c8b2db08c537534 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428945 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-062-9/+9
| | | | | | | | | | | | | | | | | | Change the name of atomic_clear to atomic_clear_bits to make to name more clear - the function clears only selected bits, but the name may suggest that it clears the whole variable. It is done as a part of porting to Zephyr, where atomic_clear zeros the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I7b0b47959c6c54af40f61bca8d9baebaa0375970 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428943 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: support enhanced PSL functions in npcx9CHLin2020-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. In npcx7, the PSL (hibernation) wakeup source only can come from physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer) module is introduced to support wakeup from a configurable timeout. 2. support PSL wakeup from the VCC1_RST pin. This function is disabled by default and enabled (and locked) in the firmware in the npcx9 A1 chip. In the npcx9 A2 chip, this function is enabled (and locked) by booter. 3. Support pulse mode and open drain (if pulse mode is enabled) for PSL_OUT pin. 4. support one PSL general-purpose output pin which is powered by VSBY. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds. make sure the reset cause in the console is "power-on hibernate rtc-alarm" TEST="hibernate"; check EC wakes up from hibernate after pressing VCC1_RST button on the internal test board. Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1 power; check EC can wake up from hibernate with any input event. Test=configure the level of PSL_GPO before hibernation; check the level is kept after entering hibernation. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* cortex-m/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-9/+17
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Id4099d2a205f5e6118e83514dc4b88c980054ea9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381710 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-292-18/+29
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* coretex-m: fix __image_size value in linker scriptCaveh Jalali2020-09-251-0/+6
| | | | | | | | | | | | | | | | | | | | | This fixes a regression introduced by chromiun:2325768 that broke software sync and forced recovery mode due to an incorrect EC image size value when CONFIG_CHIP_DATA_IN_INIT_ROM is used. also, __image_size was set twice in the linker script with the latter taking precedence when CONFIG_CHIP_INIT_ROM_REGION is enabled. Made the 1st occurrence conditional to avoid confusion. BUG=none BRANCH=none TEST=EC console "hash" command now reports the correct image size and we no longer end up in recovery due to software sync. Change-Id: Ic0fb405f6918bdfa467be5919eed91eb17ef7c2a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428566 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* cortex-m: support locating .data section in ROM residentKeith Short2020-09-242-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize the RO and RW images so the .data section remains in flash and is not copied into code RAM by the bootloader. This frees effective flash space for more code in the .text and .rodata sections. The EC initialization is changed to copy the .data section directly from flash into data RAM so the runtime access of objects linked into .data are unchanged. This is controlled with a new config option CONFIG_CHIP_DATA_IN_INIT_ROM. This option is automatically enabled when the board enables the ROM resident section with CONFIG_CHIP_INIT_ROM_REGION and the EC chip supports memory mapped access to flash (CONFIG_MAPPED_STORAGE). On Volteer this change saves 1656 bytes of RW flash space. BUG=none BRANCH=none TEST=make buildall TEST=Run "ectool motionsense lid_angle" on Volteer. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2eff814ad240dfb46bfba400b83d78d1f69a8310 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325768 Reviewed-by: caveh jalali <caveh@chromium.org>
* cortex-m: Fix flash size calculation boards without flashKeith Short2020-08-181-25/+25
| | | | | | | | | | | | | | | | | | CL:2334389 broke the make debug output for the kukui_scp and flapjack_scp boards. The actual EC image was not affected. This change also cleans up the #ifdef usage to consolidate assignment of the output sections into one place. BUG=b:164696005 BRANCH=none TEST=make buildall TEST=Run "util/compare_board.sh -b cortex-m" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If69cb492e2aa5f1181e27be24ee66f63cc74ff62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359492 Reviewed-by: caveh jalali <caveh@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-151-4/+13
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* npcx: add support for rom resident sectionsKeith Short2020-08-131-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC images are copied in full from flash to RAM. When the code RAM size is smaller than 1/2 the flash size, the EC image size is limited to the code RAM size, leaving unused flash space. Create a new linker section .init_rom used to store data objects that are single use in the previously unused flash area. Data objects can be used at runtime by copying into RAM using the flash_read() function. This change is tied to the NPCX flash layout, with asserts to ensure builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by the chip. CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until the predecessor CL:2325764 is available in CPFE images. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=With debug code, use the _init_rom macro and validate the data can be read using flash_read(). TEST=Using hex editor, verify .init_rom section located at 192K boundary and unused bytes are filled with 0xFF. TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-121-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Revert "task: Fix mutex_lock() assert (reland)"caveh jalali2020-08-071-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8d46141f4d45c65712a9ca7509b7b60128fa4d89. Reason for revert: getting EC boot loop on volteer: (note that you have to flash EC-RO to get this) 20-08-07 00:22:33.520 --- UART initialized after reboot --- 20-08-07 00:22:33.531 [Image: RO, volteer_1.1.9999-4284ce1 @caveh] 20-08-07 00:22:33.531 [Reset cause: reset-pin] 20-08-07 00:22:33.531 [0.005149 KB boot key mask 0] 20-08-07 00:22:33.543 [0.005438 init buttons] 20-08-07 00:22:33.543 [0.005669 VB Main] 20-08-07 00:22:33.543 [0.005872 VB Ping Cr50] 20-08-07 00:22:33.543 [0.007148 hash start 0x00040000 0x0002f61c] 20-08-07 00:22:33.833 [0.300169 hash done e4ddc3d0ffd015db085389d94faa38d3922e42290b6887baa8de3067ce846c13] 20-08-07 00:22:33.833 [0.300289 VB Verifying hash] 20-08-07 00:22:33.833 ��������������������������������EC\0 \0 �������S��O�8Ӓ.B) h����0g΄l[0.317577 VB Received 0xec00] 20-08-07 00:22:33.850 [0.317899 Jumping to image RW] 20-08-07 00:22:33.850 20-08-07 00:22:33.850 ASSERTION FAILURE '!in_interrupt_context() && task_start_called()' in mutex_lock() at core/cortex-m/task.c:868 20-08-07 00:22:33.861 20-08-07 00:22:33.861 === HANDLER EXCEPTION: 00 ====== xPSR: 0000000a === 20-08-07 00:22:33.861 r0 :00000364 r1 :100b6815 r2 :100b72ab r3 :100956bd 20-08-07 00:22:33.873 r4 :dead6663 r5 :00000364 r6 :200c1c20 r7 :00000001 20-08-07 00:22:33.873 r8 :00001388 r9 :100b4108 r10:100b4158 r11:00000013 20-08-07 00:22:33.884 r12:10095811 sp :200c0320 lr :200c1c20 pc :200c14f8 20-08-07 00:22:33.884 20-08-07 00:22:33.884 cfsr = 0, shcsr = 70000, hfsr = 0, dfsr = 0 20-08-07 00:22:33.884 20-08-07 00:22:33.884 =========== Process Stack Contents =========== 20-08-07 00:22:33.889 00000000: 100cfc00 00002a3d 00002751 00002731 20-08-07 00:22:33.901 00000010: 00002741 00002711 000027e1 00002791 20-08-07 00:22:33.901 00000020: 000027a1 000027b1 00002771 000027c1 20-08-07 00:22:33.901 00000030: 00002721 00002781 00002761 000027d1 20-08-07 00:22:33.906 20-08-07 00:22:33.906 Rebooting... 20-08-07 00:22:33.996 20-08-07 00:22:33.996 20-08-07 00:22:33.996 --- UART initialized after reboot --- Original change's description: > task: Fix mutex_lock() assert (reland) > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also assert task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > This was first submitted as CL:2309057, then reverted by CL:2323704 > because it broke jump to RW (b/162302011). Fix this by adding check > for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP, jump to RW > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I070a265a95d2128643b536814e608509d81adbe3 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> Bug: b:160975910 Change-Id: I9e37b1eac7344cddbd756fb45b130d7e0aee661b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341706 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. This was first submitted as CL:2309057, then reverted by CL:2323704 because it broke jump to RW (b/162302011). Fix this by adding check for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I070a265a95d2128643b536814e608509d81adbe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* linker: change symbol used to track available flashKeith Short2020-08-051-17/+13
| | | | | | | | | | | | | | | | | | | | | | Change the linker symbol used to track available flash from __image_size to __flash_used. __image_size is now only used on the struct image_data header. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=Run compare_build.sh against the following boards: cortex-m: volteer (npcx chipset) cortex-m0: honeybuns (stm32f0 chipset) minute-ia: not changed nds32: waddledee (it83xx) riscv-rv32i: asurada (i8xxx2) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I94f5b4827cc0da1055520685cfeb1fafc0119e1c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334389 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* linker: Add flash sizes as linker defined labelsKeith Short2020-08-051-0/+11
| | | | | | | | | | | | | | | | | Add linker defined labels for the configured flash sizes. This is only used for image analysis. BUG=none BRANCH=none TEST=make buildall TEST=To see the labels run "nm -n build/<board>/RW/ec.RW.elf | grep __config" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ib4db8478b19a8d93776c68fa24ee31fb21a50a24 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325765 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: change usage of dummySam Hurst2020-08-053-3/+3
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* hooks: Introduce chipset resume init and suspend complete hooksWai-Hong Tam2020-07-301-0/+10
| | | | | | | | | | | | | | | | | | | | | These hooks are only enabled through a new CONFIG. The resume init hook will be used to initialize the SPI driver, which goes to sleep on suspend. Require to initialize it first such that it can receive a host resume event, that notifies the normal resume hook. The suspend complete hook is paired with the resume init hook, which reverts the initialization of the SPI driver. BRANCH=None BUG=b:148149387 TEST=make buildall -j TEST=Build successfully on both default off and defining this CONFIG. Change-Id: I615e2bf92c75f83a7b0ab3eded61a1ef241dbdcf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321875
* Revert "task: Fix mutex_lock() assert"Edward Hill2020-07-281-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d53b71c17f7845a591fe4099b53717ec28bf5ccf. Reason for revert: Breaks jump to RW due to assert failing in chip/npcx/flash.c. Reverting while I come up with a better fix. Original change's description: > task: Fix mutex_lock() assert > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also add a check for task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I1a941fa78849a4efe586e66bb4787aa5a2a67732 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2309057 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> Bug: b:160975910 b:160208802 b:162302011 Change-Id: Idb38bfc69892fd34a18b9fdc2b46bf8e086f97dd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2323704 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* task: Fix mutex_lock() assertEdward Hill2020-07-241-1/+14
| | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also add a check for task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. BUG=b:160975910 BRANCH=none TEST=boot AP Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I1a941fa78849a4efe586e66bb4787aa5a2a67732 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2309057 Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* ec: change usage of "sane" per inclusive languagePaul Fagerburg2020-07-221-1/+1
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the terms "sane", "sanity check", and similar with inclusive/non-stigmatizing alternatives. BUG=b:161832469 BRANCH=None TEST=`make buildall -j` succeeds. `grep -Eir "sane|sanity" .` shows results only in third-party code or documentation. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I29e78ab27f84f17b1ded75cfa10868fa4e5ae88c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311169 Reviewed-by: Jett Rink <jettrink@chromium.org>
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-061-0/+4
| | | | | | | | | | | | | | | | | | | A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are called from the chipset task, while the system has already shut down and all the suspend rails are already off. It will be used for executing pending EC reboot at the chipset shutdown. The EC reboot should be executed when the chipset is completely off. BRANCH=None BUG=b:156981868 TEST=Built all boards. Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* test: Add on-device test for calculating MPU regions for RWYicheng Li2020-05-303-18/+36
| | | | | | | | | | | | | | | | MPU logic needs to represent RW with no more than 2 MPU regions when locking RW. Add on-device unit test for this calculation. BRANCH=none BUG=b:155410753 TEST=make -j BOARD=bloonchipper TEST=make -j BOARD=nucleo-f412zg test-mpu Then flash the test binary to nucleo board runtest on device ==> Pass Change-Id: Idc746efa9419d31cdae9c6fccc499c92160ac593 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2218595
* cortex-m: Use MPU REGION_CODE_RAM to lock rollback if neededYicheng Li2020-05-291-1/+1
| | | | | | | | | | | | | | | On chips with only 8 MPUs, we need to lock the rollback with unused MPU regions. Since REGION_STORAGE2 may be used to lock RW, use REGION_CODE_RAM instead. BRANCH=none BUG=b:155410753 TEST=make -j buildall Change-Id: Iec0f33b668474ed539809a319bf94d11cb52f64a Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219578 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m: Lock RW flash using aligned MPU regionsYicheng Li2020-05-291-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | On Cortex-M3, Cortex-M4, and Cortex-M7, the base address used for an MPU region must be aligned to the size of the region: https://developer.arm.com/docs/dui0553/a/cortex-m4-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0646/a/cortex-m7-peripherals/optional-memory-protection-unit/mpu-region-base-address-register#BABDAHJG Try to represent RW flash using aligned MPU regions before configuring MPU. Otherwise configuring MPU will fail. BRANCH=none BUG=b:155410753 TEST=triggered mpu_lock_rw_flash() on bloonchipper and dartmonkey and checked that configuring MPU succeeded. TEST=on bloonchipper and dartmonkey, verified that the MPU configurations make sense by adding logging. Change-Id: Ib460354ea60e96d7b6ac4a4c12730b0db7c6aaac Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: Init the MPU to check for correct operationAndrew McRae2020-05-272-2/+25
| | | | | | | | | | | | | | | | Disable all a MPU regions using the smallest supported size. BUG=chromium:1085868 TEST=Boot successfully on Puff TEST=Boot successfully on Volteer BRANCH=none Change-Id: Ie6924c3d9691ba6f4b218c9897b4e42b35b12bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212010 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
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