| Commit message (Collapse) | Author | Age | Files | Lines |
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BRANCH=none
BUG=b:151105339, b:155229277
TEST=make BOARD=bloonchipper test-mpu -j && \
./util/flash_jlink.py --board bloonchipper \
--image ./build/bloonchipper/mpu/mpu.bin
=> On console: "runtest"
=> All tests pass, except last which correctly panics:
Data access violation, mfar = 20000000
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I1c759f50da5075b1e9027cdba253d8c06843be5a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202852
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Expose definitions that we want to use in unit tests, but are internal
details that should not be used by other EC code using the rollback
functionality.
BRANCH=none
BUG=b:155229277, b:156501835
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Iab14a0cf17d4a986f1a1d9b77d27957976962078
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202851
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
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BRANCH=none
BUG=b:155229277, b:156501835
TEST=Compile and flash "rollback" test on dragonclaw with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8020000"
=> PASS
TEST=Compile and flash "rollback" test on dragonclaw with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8040000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80c0000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80e0000"
=> PASS
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ibba15e5319832ba0e0efde913275d618e249bc44
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202850
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The MPU was only being enabled when CONFIG_ARMV7_CACHE and
CONFIG_CHIP_UNCACHED_REGION were enabled; these are enabled for the
STM32H743 (dartmonkey), but not the STM32F412 (bloonchipper).
BRANCH=none
BUG=b:155229277, b:156501835
TEST=Compile and flash "rollback" test on dragonclaw with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8020000"
=> PASS
TEST=Compile and flash "rollback" test on dragonclaw with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8040000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80c0000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80e0000"
=> PASS
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I7bca3864205bd1dd6797732aa903bc3bc325ac6f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200201
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Rollback MPU support was initially added for the Cortex-M7, which can
support 16 MPU regions. REGION_ROLLBACK was defined as MPU region 10.
For the Cortex-M4, there are at most 8 regions, so we have to repurpose
some of the existing (unused) regions.
BRANCH=none
BUG=b:155229277, b:156501835
TEST=Compile and flash "rollback" test on dragonclaw with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8020000"
=> PASS
TEST=Compile and flash "rollback" test on dragonclaw with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8040000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80c0000"
=> PASS
TEST=Compile and flash "rollback" test on dragontalon with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80e0000"
=> PASS
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I748b7ea0654dee01d27bb560e82491665025d1ef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200200
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Yicheng Li <yichengli@chromium.org>
Tested-by: Yicheng Li <yichengli@chromium.org>
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Add error checking for failures and use IS_ENABLED combined with helper
functions for readability.
BRANCH=none
BUG=b:155229277, b:156501835
TEST=Compile and flash "rollback" test on dragonclaw with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 8020000"
=> PASS
TEST=Compile and flash "rollback" test on dragonclaw with region 1
On console: "runtest"
=> Memory is successfully read
=> FAIL
TEST=Compile and flash "rollback" test on dragontalon with region 0
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80c0000"
=> PASS
TEST=Compile and flash "rollback" on dragontalon with region 1
On console: "runtest"
=> Reboots with "Data access violation, mfar = 80e0000"
=> PASS
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I0f8d149c8c5c568241457a6779079c65eb38ce32
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200199
Commit-Queue: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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On Puff we need to increase some IRQ priorities to meet strict timing
requirements. To support that, provide a function encapsulating the bit
manipulations to adjust the priority of a single IRQ and update task.c
to take advantage of it.
BUG=None
BRANCH=None
TEST=Still builds.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456
Reviewed-by: Andrew McRae <amcrae@chromium.org>
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The code originally comes from libaeabi-cortexm0. It is unclear
which exact git commit the code comes from, but since we have used
it without issue for 5 years, it is reliable, and a refresh is
probably not required at this stage.
BRANCH=none
BUG=chromium:884905
TEST=make buildall -j, which also include basic tests.
Change-Id: I910c1c4e6a46b2f0fe8b7a429f1b6f0f50c2dc21
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1599762
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR;
the Configurable Fault Status Register. MMFS is the low byte of this
value, so it's misleading to refer to the whole 32-bit value as MMFS;
instead call it CFSR to make it clear that the value we store
encompasses the MMFSR, BFSR and UFSR.
BUG=None
BRANCH=None
TEST=make buildall
Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807
Reviewed-by: Keith Short <keithshort@chromium.org>
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BUG=b:149350081
BRANCH=none
TEST=build all, and emerged ec related packages for host and octopus.
$ make buildall -j
$ cros_workon --host list
chromeos-base/chromeos-cr50-dev
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools
$ sudo emerge chromeos-cr50-dev -j
$ sudo emerge chromeos-ec -j
$ sudo emerge chromeos-ec-headers -j
$ sudo emerge ec-devutils -j
$ sudo emerge ec-utils -j
$ sudo emerge ec-utils-test -j
$ sudo emerge hdctools -j
$ cros_workon-octopus list
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools
$ sudo emerge-octopus chromeos-ec -j
$ sudo emerge-octopus chromeos-ec-headers -j
$ sudo emerge-octopus ec-devutils -j
$ sudo emerge-octopus ec-utils -j
$ sudo emerge-octopus ec-utils-test -j
$ sudo emerge-octopus hdctools -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: If751b26b0635b0021c077338e96eaa8e8dcf17a5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080631
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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BRANCH=none
BUG=none
TEST=make buildall -j
TEST=make BOARD=nucleo-h743zi
# Reboot H743 into bootloader using boot0 pin and reset
# Flash nucleo over FTDI and STM32 bootloader
stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200
# Reset without boot0
# Open console
minicom -D/dev/ttyACM0
reboot soft
# Verify soft reset was used
reboot hard
# Verify hard reboot was used
Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This is just a cleanup of the linker scripts for cortex-m chips.
This brings no functional change.
BRANCH=none
BUG=none
TEST=make buildall
Change-Id: If9fa43157e8955fed7c7426b910c6af957794b0b
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930392
Reviewed-by: Jett Rink <jettrink@chromium.org>
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In order to make our printf more standard, utilize %ll for long long
arguments, rather than %l. This does cost a little bit in flash space
for that extra l in a couple of places, but enables us to turn on
compile-time printf format checking.
For this commit only, the semantics are such that both %l and %ll
take 64-bit arguments. In the next commit, %l goes to its correct
behavior of taking a sizeof(long) argument.
BUG=chromium:984041
TEST=make -j buildall
BRANCH=none
Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029
Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Enable CONFIG_PRESERVE_LOGS to gather more information
when SCP is crashed.
TEST=1. crash scp
2. restart scp
3. restart timberslide to ensure the logs are fetched
4. see that untransmitted logs are fetched into /var/log/cros_scp.log
BUG=b:140220117
BRANCH=none
Change-Id: I12635afa6c92fd8fa9cc889ce75999f855f18db0
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833943
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Provide API to disable/enable tasks.
All the tasks are marked enabled after hook_task starts.
We need a way to control the tasks when it shouldn't run in some states.
BUG=b:136240895
TEST=Disable the tasks and see it won't be scheudled when task_wake().
BRANCH=None
Change-Id: I2662f3619b22ed28387fe3c783001ba2a745620c
Signed-off-by: Yilun Lin <yllin@google.com>
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753562
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I had a hard time reading this section, so figured I may as well
rewrite it to use IS_ENABLED while I was here.
Gave CONFIG_{RO,RW}_HEAD_ROOM a default value of zero here, which
makes the math work out for boards without it anyway.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I87dc2d73838c350088916b57aa51d5f368c5592f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727570
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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This option was only used with kunimitsu, which was removed from the
EC codebase a long time ago. The EC code won't even compile with this
option enabled anymore.
Remove it!
BUG=chromium:989301
BRANCH=none
TEST=buildall
Change-Id: I8ede226ec1e7b300ded6bb1769d82e142db1b0aa
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727569
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This CL fixes DRAM section loaded at the wrong location, and
also relayouts the DRAM section to have a smaller flat binary.
Current DRAM region layout is as below:
.dram.data LMA | LOAD
.dram.data VMA |
.dram.bss | NOLOAD
.dram.rodata | LOAD
.dram.text | LOAD
This will create a flat binary file as following layout:
.dram.data
.dram.bss
.dram.rodata
.dram.text
and loader will load .flat.dram to .dram.data LMA's starting section.
This leads to .dram.bss, .dram.rodata and .dram.text been loaded at
the wrong location, where .dram.data VMA resides.
This CL fixes the issue by reorganize the sections into:
.dram.text | LOAD
.dram.rodata | LOAD
.dram.data LMA | LOAD
.dram.data VMA |
.dram.bss | NOLOAD
and thus we have a flat binary as:
.dram.text
.dram.rodata
.dram.data
so that:
1. everything will be placed at the correct address.
2. have a smaller flat binary.
The CL also removes .dram.keep.* section, which is not used so far.
BUG=b:134079593
BRANCH=master
TEST=With crrev.com/c/1646691, check the output of object header:
1. SIZEOF(.dram.text + .dram.rodata + .dram.data) = SIZEOF(.image.RW.dram)
0x68 0x18 0x14 0x94
2. ADDR(.dram.data LMA) + SIZEOF(.dram.data) = ADDR(.dram.data VMA)
0x10000080 0x14 0x10000094
arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf
Idx Name Size VMA LMA File off Algn
5 .dram.text 00000068 10000000 10000000 00030000 2**3
CONTENTS, ALLOC, LOAD, READONLY, CODE
6 .dram.rodata 00000018 10000068 10000068 00030068 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .dram.data 00000014 10000094 10000080 00030094 2**0
CONTENTS, ALLOC, LOAD, DATA
8 .dram.bss 00000004 100000a8 100000a8 000300a8 2**0
ALLOC
arm-none-eabi-objdump -h build/kukui_scp/ec.obj
Idx Name Size VMA LMA File off Algn
2 .image.RW.dram 00000094 50000000 50000000 00020000 2**0
CONTENTS, ALLOC, LOAD, READONLY, CODE
TEST=With crrev.com/c/1646691, see the console has correct output:
dram_bss_val = 0
dram_data_val[0]= 1
dram_data_val[1]= 2
dram_data_val[2]= 3
dram_data_val[3]= 4
dram_data_val[4]= 5
dram_data_val[5]= 6
dram_data_val[6]= 7
dram_data_val[7]= 8
dram_data_val[8]= 9
dram_data_val[9]= 10
dram_data_val[10]= 11
dram_data_val[11]= 12
dram_data_val[12]= 13
dram_data_val[13]= 14
dram_data_val[14]= 15
dram_data_val[15]= 16
dram_data_val[16]= 17
dram_rodata_val[0]= 55
dram_rodata_val[1]= 56
dram_rodata_val[2]= 57
dram_rodata_val[3]= 58
dram_rodata_val[4]= 59
dram_rodata_val[5]= 60
Change-Id: Ic6836c6ad553d0ceae4d55df92caa1896fee905d
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646690
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Auto-Submit: Yilun Lin <yllin@chromium.org>
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get_interrupt_context is only called from code inside #ifdef
CONFIG_TASK_PROFILING.
clang emits an unused function warning for this:
core/cortex-m/task.c:238:19: error: unused function
'get_interrupt_context' [-Werror,-Wunused-function]
static inline int get_interrupt_context(void)
BRANCH=none
BUG=chromium:931797
TEST=make buildall -j
Change-Id: I5ba68d1a58a966eeecb5abdb3cb87fa2684f359b
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660017
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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.dram.bss section is like .bss section that all the contents should
be initialized to zero.
TEST=build a image with .dram.bss section, and verify it only has
ALLOC attribute.
$ arm-none-eabi-objdump -h build/kukui_scp/RW/ec.RW.elf
7 .dram.bss 00000acb 3009aaa8 3009aaa8 0010aaa8 2**2
ALLOC
BUG=b:134079593, b:122058243
BRANCH=master
Change-Id: I853b2977465b83458f566c5dd953458147d4e10e
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646689
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
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This patch adds a hook for USB PD connect event.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/127228934
BRANCH=none
TEST=buildall. Verify a hook is called on BC12 charger connection.
Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3
Reviewed-on: https://chromium-review.googlesource.com/1597794
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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ld won't complain .data LMA overlapping if using a computed LMA
address. This CL workaround this by assigning a load memory region.
Related discussion:
https://github.com/rust-embedded/cortex-m-rt/issues/86
TEST=make buildall -j
TEST=cherry-pick https://crrev.com/c/1592972
make BOARD=kukui_scp -j
and see it ld reports failure for LMA overlapping:
build/kukui_scp/RW/ec.RW.elf section `.data' will not fit in region `IROM'
region `IROM' overflowed by 3784 bytes
TEST=w/o this CL; make buildall -j; cp -r build build.old
w/ this CL; comment out EC version rules
#.PHONY: $(out)/ec_version.h
make buildall -j
compares the .flat files by:
for f in $(ls build/*/*/ec.*.flat | sed -e 's|build/||');
do
echo "###### diff ${f}"
diff <(xxd build/${f}) <(xxd build.old/${f})
done
and see that all the .flat are the same, except that
some boards(aquila, arcadia, cr5*, granite,
haven_dev, hg_*, hotelgolf, hslt_*, indus, proto2, red,
starcard, tk-x001) using g-chip have different content at
addr 0x0~0x360 (related to regen key?), and this change
is not likely to touch that address.
BUG=b:131641213
BRANCH=None
Change-Id: I54c697669ef3836c93027bce90f507c33283c6f3
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1588297
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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kukui_scp is loaded into SRAM. We would like to protect
the memory from a modified code RAM content and executing injected
code in data RAM.
BRANCH=None
BUG=b:123269246
TEST=Apply MPU test patch https://crrev.com/c/1530265.
Test data ram XN:
1. mpu 0 # disable MPU
2. mpu_test # see it prints
3. mpu 1 # enable MPU
4. mpu_test # memory access violation, and reset.
5. mpu_test # memory access violation, and reset
# again. (MPU enabled by default)
Test code ram RO:
1. rw 0x8 0x5566 # Write to code RAM and see memory
# access violation and reset.
2. mpu 0 # disable MPU
3. rw 0x8 0x5566 # Nothing happended
4. rw 0x8 # Read 0x5566
5. mpu 1 # enable MPU
6. rw 0x8 0x5566 # memory access violation.
Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530264
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
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Currently, kukui_scp's memory layout interleaves with RO and RW
sections. This complicates the MPU region configuration, and it
even unconfigurable.
This CL propose to simplify the layout and configuration by introducing
an IROM region, and re-layout the memory.
New layout would be:
---------------------------- 0x0
RO| .stepping_stone
| .text .rodata .data LMA
---------------------------- 0x100000
RW| .bss .data stack
| ipi shared buffer
---------------------------- 0x7C0000
BRANCH=None
BUG=b:123269246
TEST=1. w/o this CL: make buildall -j; mv build build.old
2. w/ this CL: make buildall -j;
3. compare smap by: ls build/*/*/ec.*.smap | \
sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
and sees that only kukui_scp's smap changed.
Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1530263
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Overlapping LMA section with other VMA section will fail lld.
This CL makes the linker script to be compatible with both ld and lld.
BRANCH=None
BUG=b:128269393
TEST=On m/master; make buildall -j; mv build build.old
After this CL:
make buildall -j
ls build/*/*/ec.*.smap | sed -e 's|build/||' | \
xargs -I{} diff build/{} build.old/{}
=> no difference except that __data_lma_start's attribute changes
from D to R.
e.g., 0011a4a0 D __data_lma_start becomse
0011a4a0 R __data_lma_start
TEST=diff build/kukui_scp/RW/ec.RW.flat build.old/kukui_scp/RW/ec.RW.flat
are the same, except the version strings.
TEST=CC=clang make BOARD=kukui_scp and see that __bss_start and
__data_lma_start not overlapping in kukui_scp/RW/ec.RW.smap
TEST=CC=clang make BOARD=nocturne_fp -j and build pass.
Change-Id: I4a6ece8d2279124e2797e0dc71b228a470f029d9
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1514436
Commit-Ready: Tom Hughes <tomhughes@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Text section name is adding ",\"a\" @" to the section name.
arm-none-eabi-objdump --disassemble-all \
./build/nocturne_fp/RO/core/cortex-m/vecttable.o
Before:
Disassembly of section .text.vecttable,"a" @:
00000000 <vectors>:
...
After:
Disassembly of section .text.vecttable:
00000000 <vectors>:
...
Comparing the text.vecttable elf section headers for gcc before and
after this change, there is no difference to flags:
arm-none-eabi-objdump -h \
./build/nocturne_fp/RO/core/cortex-m/vecttable.o
.text.vecttable 00000298 00000000 00000000 00000050 2**2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
One difference when compiling with clang is that it sets the DATA
attribute in the header, while gcc sets CODE. Since this is an array of
addresses, not executable code, I think clang is actually correct:
.text.vecttable 00000298 00000000 00000000 00000060 2**2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
BRANCH=nocturne,nami
BUG=chromium:931797
TEST=make buildall -j
Change-Id: I16e57ccd988a8644ed179bed057647c16e96e134
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1470779
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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Compared the disassembly between compiling with gcc before this change
and compiling with clang after the change:
arm-none-eabi-objdump --disassemble
build/nocturne_fp/RW/core/cortex-m/uldivmod.o
--- gcc-uldivmod.txt 2019-02-12 14:54:47.283162092 -0800
+++ clang-uldivmod.txt 2019-02-12 14:52:50.098690222 -0800
@@ -103,5 +103,5 @@
000000b8 <__aeabi_ldiv0>:
b8: 4c01 ldr r4, [pc, #4] ; (c0 <__aeabi_ldiv0+0x8>)
ba: f7ff fffe bl 0 <exception_panic>
- be: 0000 .short 0x0000
+ be: bf00 nop
c0: dead6660 .word 0xdead6660
BRANCH=nocturne,nami
BUG=chromium:931797
TEST=compare disassembly (see above)
Change-Id: I9ab7eb18ffa9bf3e319cdd1f81047577218a0dad
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1470777
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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The previous version could only work on single lines, let's add
functions to work on ranges.
BRANCH=none
BUG=b:123676508
TEST=fill; flush; fill to generate incoherent DRAM/cache content
TEST=flush 0x10000000 16 c => clean a single line
flush 0x10000020 32 c => clean a single line
flush 0x10000040 64 c => clean 2 lines
TEST=flush 0x10000080 16 i => invalidate 1 line
flush 0x100000a0 32 i => invalidate 1 line
flush 0x100000c0 64 i => invalidate 2 lines
Change-Id: Ib386eeb4ce5d2f64a23e558c7f562eba234e6b0d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1475105
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Yilun Lin <yllin@chromium.org>
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For performance reasons, we want to be able to flush/invalidate
only specific cache lines/addresses.
BRANCH=none
BUG=b:123676508
TEST=fill; flush; fill to generate incoherent DRAM/cache content:
cached:
10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07
10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f
direct:
30000000: 3848c300 3848c301 3848c302 3848c303 3848c304 3848c305 3848c306 3848c307
30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f
=> Then clean a cache line
> flush 0x10000000 c
Clean
cached:
10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07
10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f
direct:
30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07
30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f
=> memory is updated
=> Then invalidate a cache line
> flush 0x10000020 i
Inval 10000020
cached:
10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07
10000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f
direct:
30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07
30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f
=> cache content is thrown away, and matches memory
Change-Id: I5dbcc366236fef56f7cb048ce313247cf3d51276
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1475092
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Yilun Lin <yllin@chromium.org>
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It creates smaller code.
BUG=chromium:851727,b:65441143
BRANCH=none
TEST=builds with the new compiler
Change-Id: I569c6f75a595331fb489323d8b3f02d5dd2d5050
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1450713
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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We manually copy other .data from the original section on boot, and
clear DRAM .bss.
This way, a single object file (or archive) can be moved fully to
DRAM.
BRANCH=none
BUG=b:122058243
TEST=With next CL, dram_test works
Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1445652
Reviewed-by: Jett Rink <jettrink@chromium.org>
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With tpm2 makefile now re-naming .bss section in the produced objects,
there is need to try grouping files by module name, especially since
this does not even work when linking object modules directly instead
of the library.
BRANCH=cr50, cr50-mp
BUG=b:65253310
TEST=make BOARD=cr50 -j produces an image with the same _bss_libtpm2
section.
Change-Id: I38f8ec3efa0364a0ad58781b7822a0eb52b636bb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1457602
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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gcc injects calls to that function without notifying LTO.
BRANCH=cr50, cr50-mp
BUG=b:65253310
TEST=after the entire stack was applied Cr50 builds successfully with
CONFIG_LTO enabled, and passes TCG test suite.
Change-Id: Ie116423a2e8a394dae9d6c7c373786615d9fba4c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1411540
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If .text, .rodata and .bss section are all puts in the same memory
space, e.g. RAM (.data section's LMA is usually located right
after .rodata section, and right before .bss section.).
.data section's LMA might be overlapped with .bss section so that
it would get cleared to zero on program startup.
TEST=Remove ". = ALIGN(512);" in .bss section in linker script,
and check build/kukui_scp/RW/ec.RW.smap, and we have
__data_lma_start = 0x74b4
__bss_start = 0x74f8
__data_start = 0x8ae0
__data_end = 0x8b20
__data_end - __data_start = 64
__bss_start - __data_lma_start = 68 # .data is able to fit in.
check .data section LMA won't be overlapped with .bss section VMA.
BUG=b:122084384
BRANCH=None
Change-Id: Ic6ae7ad7c6a080ce7aa6375c4f0e01ac9474cdc7
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1404640
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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The name of __ro_end is confusing. The variable is
actually used as a label tagging that it is the starting
address of .data LMA. Renames to __data_lma_start to
be more decriptive.
BRANCH=None
TEST=make buildall -j
BUG=b:122084384
Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1433160
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This adds a generic task_reset function that can reset any task
that declares it supports being reset. Tasks that support reset
must call task_reset_cleanup() on startup, and be prepared to
perform any cleanup / re-initialisation necessary. The task can
control when it can be reset using task_enable_resets() and
task_disable_resets().
A task can request another task be reset at any point; if the
reset cannot happen immediately, it will be queued and will happen
at the earliest point allowed by the task to be reset.
Task resets can be blocking or non-blocking, as specified by
the requestor.
BUG=b:73771117
BRANCH=none
TEST=manual testing on local device
Change-Id: I972184381b005c342374fa16c4dce2ac83e89854
Signed-off-by: Louis Collard <louiscollard@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1230394
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This allows to store specific code/data in a .dram region. This
is used by mt_scp to run code off DRAM, as we plan to have more
code than what can fit in SRAM.
BRANCH=none
BUG=b:122058243
TEST=make BOARD=kukui_scp -j
objdump -x build/kukui_scp/ec.obj
=> Some code is loaded in DRAM
TEST=Load kukui_scp, icachetest works
Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1391542
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We would like to keep a symbol in a chip memory region from GC in link
time. However __attribute__((used)) cannot fulfill the requirement in such
situation. This CL adds a "name.keep" section to prevent all the symbols
in this section in a chip memory region from GC. Also, we would like to
support a non-NOLOAD section, which can load default value on runtime.
BUG=b:120825336
TEST=make buildall -j
BRANCH=none
Change-Id: I76cf445f6b4c0b61c20182a1aaf5a44f962049ae
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1373949
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Linker script verifies flash size and layout when generating firmware
binary. This configuration macro removes FLASH section and asserts.
BRANCH=none
BUG=b:114326670
TEST=make buildall -j
Change-Id: I3c9ce6f930260d780839e52b45055f88cc22f85f
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1208771
Commit-Ready: Yilun Lin <yllin@chromium.org>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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"time in exceptions" looks unreasonable after > 4294s (when 32-bit
microsecond timer wraps around).
This is because core/cortex-m/task.c:svc_handler records time
exc_start_time just before the interrupt handler for 32-bit
timer interrupt runs, so the high word of the system clock
(clksrc_high) is not updated yet (while the low 32-bits already
wrapped around). After the handler runs, clksrc_high is updated,
so there appear to be a 4294s gap between the 2 measurements.
Fix this by recording the low 32-bit timer value only. There will
never be more than 4294s between exceptions, and this fixes the
wrap-around issue as well.
BRANCH=none
BUG=chromium:914208
TEST=Flash kukui (cortex-m0) and kukui_scp (cortex-m), let system
run for 4300+s, no more accounting error in "Time in exceptions".
Change-Id: If52855ef093ac1a1d38432555694c83742feb8f1
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1372876
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If we keep it assembly-only, the link time optimizer gets confused and
eliminates seemingly unused functions, to then replace references to
them with the "no handler" defaults in a later step.
Similar approach as with vecttable: Implement the table in C so LTO
knows the entire story.
BUG=b:65441143
BRANCH=none
TEST=usb_ep_{rx,tx,reset} and usb_iface_request look more reasonable in
disassembly on cr50.
Change-Id: I72103af742164c29aac38e9929d1a83d8c154b53
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1177711
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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Different versions of the linker behave differently when mixing object
built with lto enabled (desirable for code size reduction) and disabled
(assembler code), especially when they refer to each other symbols:
The file evaluation order of the linker becomes important as it
eliminates dead code at various points in time, and LTO code referring
to non-LTO code or vice versa, is not visible at early runs.
Sadly, just changing the order on the command line isn't sufficient:
What works for gcc8 breaks gcc6 (and may behave different in even more
ways on gcc4 or other versions).
Therefore, implement the vector table in C, so it's compiled in LTO
mode, just like the code it refers to.
This is a port of Change-Id: I9b75f6558f0357e18000ff1161096c8f9c94a8ac
BUG=b:65441143
BRANCH=none
TEST=with this change the vector table for whiskers looks much more
reasonable (ie. not mostly empty)
Change-Id: Ifd39289ecb16b81cdf41427ce190984510d3fd3c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1120333
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1177382
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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Update header, C code, trim unnecessary bits.
Also add a test with vectors taken from BoringSSL tests.
BRANCH=none
BUG=b:111160949
TEST=make run-aes -j
TEST=make BOARD=nocturne_fp test-aes -j
flash_fp_mcu aes.bin
runtest => pass
(C implementation speed: 909555 us for 1000 iterations)
(ASM implementation speed: 596690 us for 1000 iterations)
Change-Id: Ief54a8441d26ba44de4c3ac81e203cab7472269f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1141446
Commit-Ready: Nicolas Norvez <norvez@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
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Copied over from upstream BoringSSL at commit
859679518d3433cdd0dd6cf534bd7bdb2a32dd60 .
cp boringssl/crypto/fipsmodule/modes/gcm.c \
third_party/boringssl/common/gcm.c
cp crypto/fipsmodule/modes/internal.h \
third_party/boringssl/include/aes-gcm.h
=> Remove non-GCM definitions
perl boringssl/crypto/fipsmodule/modes/asm/ghash-armv4.pl \
> third_party/boringssl/core/cortex-m/ghash.S
BRANCH=none
BUG=b:111160949
TEST=none
Change-Id: I34702ff315c8c44e6f4868243058700aaf026099
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1141445
Reviewed-by: Adam Langley <agl@chromium.org>
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Update header, C code, and tweak the assembly for ARMv7-M.
Rename aes_now_* functions to AES_* to avoid the need for a
separate wrapper.
Also add a test with FIPS-197 test vectors, and speed test.
BRANCH=none
BUG=b:111160949
TEST=make run-aes -j
TEST=make BOARD=nocturne_fp test-aes -j
flash_fp_mcu aes.bin
runtest => pass
(C implementation speed: 11977 us for 1000 iterations)
(ASM implementation speed: 5815 us for 1000 iterations)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I2048aae73decccb893bc1724b2617b0b902dd992
Reviewed-on: https://chromium-review.googlesource.com/1120340
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Adam Langley <agl@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Copied over from upstream BoringSSL at commit
859679518d3433cdd0dd6cf534bd7bdb2a32dd60 .
cp boringssl/LICENSE third_party/boringssl/LICENSE
cp boringssl/src/crypto/fipsmodule/aes/aes.c \
third_party/boringssl/common/aes.c
cp boringssl/include/openssl/aes.h \
third_party/boringssl/include/aes.h
perl boringssl/crypto/fipsmodule/aes/asm/aes-armv4.pl \
> third_party/boringssl/core/cortex-m/aes.S
BRANCH=none
BUG=b:111160949
TEST=none
Change-Id: Ia1fbb57b23e039ca5dec3d56984c83c19b7d6cd6
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1120339
Reviewed-by: Adam Langley <agl@chromium.org>
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In our design once enter BIST test data mode, Hw don't
interrupt Fw due to any Rx received packet. But when port
partner re-connect in this mode, it will cause that our
pd port doesn't respond packet which port partner transmits.
When port partner disconnects, so we need to reset our pd
port protocol layer and PHY to leave BIST test data mode and
let Hw can interrupt Fw. With this modify it can pass
GRL-USB-PD compliance TDA2.1.2.2 test item.
BUG=b:112602596
BRANCH=none
TEST=GRL-USB-PD compliance test.
Change-Id: I30526b5d796e3eabc9af2f524071c98bb0ef5abf
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1170718
Reviewed-by: Jett Rink <jettrink@chromium.org>
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