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* core/*/ec.lds.S: quote paths containing OUTDIRPatrick Georgi2016-02-101-4/+7
| | | | | | | | | | | | | | | | | | | If OUTDIR brings in a "@", the build breaks because that delimits the path, leading to invalid file names. This can happen (and happened) when building on a Jenkins CI instance which uses jobname@number as path for parallel checkouts on a single build node. BRANCH=none BUG=none TEST=build with make out=foo@bar ... failed and works now. Change-Id: Id0594f0d7312419110091443755ec11b5f8ee2d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/327110 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* chip: it83xx: fix EC interrupt vector registers issueDino Li2016-01-282-29/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a limitation for EC interrupt vector registers. System may read incorrect interrupt number in ISR so we need to add a workaround to prevent it. The following is a example that got incorrect interrupt number: 1. REG IVCTx = 0x10. (no interrupt pending) 2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR. 3. Read interrupt vector register to determine interrupt number. 4. Higher priority interrupt of same interrupt group occurs (for example: INT134, IVCTx = 0x96) while the system is reading the interrupt vector register for EC INT6, we may end up with an incorrect interrupt number between 0x16 and 0x96. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart, LPC, I2C, and PECI. 2. Console command 'taskinfo'. Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17 Reviewed-on: https://chromium-review.googlesource.com/322097 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* core: nds32: add task_wait_event_mask() function to nds32 coreDino Li2016-01-051-3/+29
| | | | | | | | | | | | | | | | | | | | | [task] 1. Copy task_wait_event_mask() function of cortex-m0. [system] 2. Include host_command.h for host_command_pd_request_hibernate(). [i2c] 3. Update i2c handler to use task_wait_event_mask. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chromium:435611,chromium:435612 TEST=1. console commands: i2cscan, i2cxfer, and battery. Change-Id: If5bb4407460d28c0b021ab133ca4b635ff7bc3c9 Reviewed-on: https://chromium-review.googlesource.com/320440 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: start_irq_handler() use system stackDino Li2015-12-163-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [symptom] The 'vboot_hash_start()' always return busy error and variable 'in_progress' got a strange value(should be 0 or 1). 'start_irq_handler()' causes scratchpad overflow in first context switch. It must be called after SP switch to system stack in ISR. NOTE: The scratchpad is still also need more size even if 'start_irq_handler()' is using system stack. following is detail: 1. uint32_t scratchpad[19] 0x81d34 ~ 0x81d7f [__task_start:] 2. /* put the dummy stack pointer at the top of the stack in scratchpad */ addi $sp, $r3, 4 * 18 -> SP 0x81d7c 3. syscall push return address (-4) -> SP 0x81d78 [ISR:] 4. push r15, fp, lp, and sp (-0x10) -> SP 0x81d68 5. push r0 ~ r5 (-0x18) -> SP 0x81d50 [__switch_task:] 6. /* save ipsw, ipc, r6, r7, r8, r9, r10 on the current process stack */ (-0x1C) -> SP 0x81d34 Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. hash done. 2. console command 'taskinfo'. 3. the scratchpad does not overflow after first context switch. Change-Id: If5d89ff5c945a777010492fcfb54bf41f434ed69 Reviewed-on: https://chromium-review.googlesource.com/317468 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: fix ldsDino Li2015-11-121-0/+1
| | | | | | | | | | | | | | | | | | symptom: .bss.slow won't be cleared during initialization. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=.bss.slow = 0. Change-Id: I6a8b84807b36a64f29732f09f56947e17d5ba898 Reviewed-on: https://chromium-review.googlesource.com/312155 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: modify hwtimer and LPC wake upDino Li2015-11-051-34/+7
| | | | | | | | | | | | | | | | | | | | | | | | | 1. In combinational mode and clock source is 8MHz, if timer 3 counter register always equals to 7, then timer 4 will be a 32-bit MHz free-running counter. 2. Fix TIMER_32P768K_CNT_TO_US(), each count should be 30.5175 us, not 32.768us. 3. Fix TIMER_CNT_8M_32P768K(). 4. Make sure LPC wake up interrupt is enabled before entering doze / deep doze mode. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Console commands: 'gettime', 'timerinfo', 'waitms', and 'forcetime'. 2. Enabled Hook debug, no warning message received (48hrs). 3. Tested ectool command 'version' x 2000. Change-Id: I796d985361d3c18bc5813c58705b41923e28c5b1 Reviewed-on: https://chromium-review.googlesource.com/310039 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: fix interruptDino Li2015-11-012-0/+22
| | | | | | | | | | | | | | | | | | | | | | 1. To enable INT_PRI (hardware interrupt priority level 0~3) register, bit0@INT_CTRL = 0. 2. GIE need to be enabled before UART is initialized. [symptom] To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on: after RW image is verified, firmware stuck in uart_flush_output(). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. bit0@INT_CTRL = 0. 2. The RW image is verified and jump to image RW. Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b Reviewed-on: https://chromium-review.googlesource.com/309400 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: Increase DLM sizeDino Li2015-10-251-0/+12
| | | | | | | | | | | | | | | | 1. Total DLM size is 48KB. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=DLM 0x84000 ~ 0x8BFFF read/write OK. Change-Id: I2340aeefca60ad59062254ddd363c703c30cfd24 Reviewed-on: https://chromium-review.googlesource.com/307006 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix clock moduleDino Li2015-10-251-5/+40
| | | | | | | | | | | | | | | | | | | | 1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=test the following items in deep doze mode. 1. WUI interrupts wake-up OK. (For example, power button, lid, uart rx, keyboard ksi, and so on) 2. LPC access interrupt wake-up OK. 3. Enabled Hook debug, no warning message received (48hrs). Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4 Reviewed-on: https://chromium-review.googlesource.com/307060 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: fix panicDino Li2015-10-073-5/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support saving panic data for nds32 core. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console commands 'crash' and 'panicinfo'. 2. ectool command 'panicinfo' crash assert ASSERTION FAILURE '0' in command_crash() at common/panic_output.c:162 === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 > crash divzero === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access > crash stack +1+2+3+4+5+6+7+8+9+10+11+12+13+14+15+16+17 Stack overflow in CONSOLE task! === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 > crash watchdog Pre-watchdog warning! IPC: 00009c6c panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=0 === R0 00000000 R1 00000000 R2 00000000 R3 00000000 R4 00000000 R5 00000000 R6 dead6664 R7 00000000 R8 00000000 R9 00000000 R10 00000000 R15 00000000 FP 00000000 GP 00000000 LP 00000000 SP 00000000 IPC 00009c6c IPSW 00000 SWID of ITYPE: 0 Software panic reason PANIC_SW_WATCHDOG Software panic info 0x0 > Change-Id: I3d491ecd0789335db4633f9bf2ca09cf85503ed9 Reviewed-on: https://chromium-review.googlesource.com/303286 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix hw timer and related function.Dino Li2015-10-014-2/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [chip config] 1. No hardware specific udelay(). 2. Enable watchdog. [watchdog] 3. Watchdog period is "CONFIG_WATCHDOG_PERIOD_MS" of config.h. 4. Watchdog auxiliary timer period is "CONFIG_AUX_TIMER_PERIOD_MS". [task and irq] 5. Write 1 to clear interrupt pending status, no |. 6. A global variable for store interrupt number of software interrupt. [uart] 7. Always reset UART module before config it. [hwtimer] 8. Use more external timers for HW timer module. [task] 9. Fix task profiling. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=[watchdog] 1. console "waitms 1100", only pre-watchdog warning message. 2. console "waitms 1600", warning message and watchdog reset. [hwtimer] 3. console commands "gettime", "timerinfo", and "forcetime". 4. enable hook debug and there is no delayed by more than 10% warning message over 48 hours. 5. There is no watchdog reset too. [task] 6. console 'taskinfo' Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000000 32.927724 308/512 1 HOOKS 00000000 0.034267 372/768 2 R CONSOLE 00000000 0.116763 468/768 3 HOSTCMD 00000000 0.000641 372/512 4 KEYPROTO 00000000 0.000042 212/512 5 KEYSCAN 00000000 0.000908 356/512 IRQ counts by type: 38 2932 155 1 158 261 160 67 Service calls: 87 Total exceptions: 3348 Task switches: 167 Task switching started: 0.001999 s Time in tasks: 33.282819 s Time in exceptions: 0.164717 s Change-Id: I234085cec231cd855d2a5e639ea1b0966c61d796 Reviewed-on: https://chromium-review.googlesource.com/296939 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: Add __fls functionGwendal Grignou2015-09-211-3/+3
| | | | | | | | | | | | | | | Returns the most significant bit set. Replace 31 - __builtin_clz(x), so x must be different from 0. Use get_next_bit when not on the performance path, on performance path set the bit field just after reading it. BRANCH=smaug BUG=none TEST=compile, check Ryu still works. Change-Id: Ie1a4cda4188f45b4bf92d0549d5c8fb401a30e5d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301300
* it8380dev: fix idle task and chip idDino Li2015-09-181-1/+23
| | | | | | | | | | | | | | | | | | | | | 1. Fix system_get_chip_name() and system_get_chip_revision(). 2. Fix EC doze mode. 3. Enable LPC cycle wake-up EC from doze / deep doze function. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console "version". Chip: ite it8390 cx 2. EC doze mode is normally. 3. ectool "version" command x 2000. Change-Id: I167dbfb965e557eb86ed83f45a945e4315f5fa9f Reviewed-on: https://chromium-review.googlesource.com/299110 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cleanup: Remove COMPILE_FOR_RAM option from linker scriptsBill Richardson2015-09-081-12/+0
| | | | | | | | | | | | | | | This option was added way back in January 2012 for early EC bringup, and never used since. We can probably remove it. BUG=none BRANCH=none TEST=make buildall Change-Id: Idc8c3099388f2e28d620848a0e78b555b02fba9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297334 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* UART: Remove unused uart.h header includesAnton Staaf2015-09-082-2/+0
| | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ife068807f79f6435292643c49afa1a9a30ae7080 Reviewed-on: https://chromium-review.googlesource.com/296733 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: use INT_MASK instead of GIEDino Li2015-08-203-34/+66
| | | | | | | | | | | | | | | | | | | | | | | | | When there is an interrupt event, N8 CPU will save PSW register to IPSW register and clear GIE then jump to interrupt service routine. N8 will restore PSW from IPSW after "iret" instruction (the above are purely hardware mechanism). Nested interrupt will occur if we set GIE again in interrupt context. symptom: power button pressed while LID open -> exception or unknown reset. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Manually pressed power button x200. 2. Console "eflash" erase and write eflash OK. Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f Reviewed-on: https://chromium-review.googlesource.com/289437 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add __muldi3.SDino Li2015-08-142-1/+41
| | | | | | | | | | | | | | | | | | | | symptom: Enable debugging and profiling statistics for hook functions (#define CONFIG_HOOK_DEBUG), and __muldi3 function is missing while link. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. compile successful and hook_notify starting to print message. 2. console "hookstats" Change-Id: Ia2815bcefd0f9ac06dab9c75ea6ee06312878ca2 Reviewed-on: https://chromium-review.googlesource.com/293432 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* Atomic: Mark the modified uint32_t volatileAnton Staaf2015-07-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | The atomic_* functions are often used in contexts where the data they will operate on are volatile (due to being shared between tasks or a task and an interrupt handler). Adding volatile here makes using the atomic_* functions a little easier in those cases and removes a cast from the call sites (which could be obscuring a bug, if for instance the variable was modified to be a uint16_t). Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e Reviewed-on: https://chromium-review.googlesource.com/287516 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* hooks: Move HOOK_INIT to after task switching.Aseda Aboagye2015-07-131-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | This commit changes the way in which tasks are started. Instead of having all tasks marked as ready to run upon initialization, only the hooks task is marked as ready to run. HOOK_INITs are now run at the beginning of the hooks task. After the HOOK_INITs, the hooks task calls back to enable the rest of the tasks, reschedules, and proceeds as usual. This also allows the removal of checks for task_start_called(). BUG=chrome-os-partner:27226 BRANCH=None TEST=Built and flash EC image for samus and verified that EC boot was successful as well as AP boot. Additionally, verified that charging, keyboard, tap-for-battery were all still functional. TEST=make -j buildall tests Change-Id: Iea53670222c803c2985e9c86c96974386888a4fe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/283657 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* it8380dev: add flash module and fix system jumpDino Li2015-07-082-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add flash control module for emulation board. 2. Fix system jump for Andes core. 3. Change the physical size of the flash on the chip to 256KB. note: 1. Only IT839x series supports flash write protect by registers. 2. Static DMA method of flash code only for IT839x series and IT838x Dx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command flashwp and flashinfo 1-a. flashwp enable 1-b. WP asserted and reboot 1-c. flashinfo RO protected now 1-d. WP deasserted and reboot 1-e. No protected 1-f. flashwp disable 1-g. WP asserted and reboot 1-h. No protected 2. console sysjump and sysinfo 2-a. sysjump rw 2-b. jumping to image RW 2-c. sysinfo, Copy : RW, Jumped : yes 2-d. sysjump ro 2-e. jumping to image RO 2-f. sysinfo, Copy : RO, Jumped : yes 3. RO/RW firmware image test 3-a. sysjump rw 3-b. use console command "eflash" to erase RO region, erase OK and system still work. 3-c. reflash firmware 3-d. sysjump rw, sysjump ro 3-e. use console command "eflash" to erase RW region, erase OK and system still work. Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8 Reviewed-on: https://chromium-review.googlesource.com/271390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* nds32: remove macro "RO"Dino Li2015-07-011-13/+0
| | | | | | | | | | | | | | | | | | | "RO" is a workaround for GP base instructions. And now we have added "-mno-gp-direct" option in the NDS32 toolchain. So the compiler would not generate GP base instructions directly, and we can remove this "RO". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:24378 TEST=console "version" and "gpioget" Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/281862 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-184-12/+12
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: add pmc control moduleDino Li2015-06-172-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pmc(LPC ACPI) control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. 62h/66h port. 1-a. out 66h 80h, out 62h 00h, in 62h 02h 1-b. out 66h 81h, out 62h 01h, out 62h 55h 1-c. out 66h 80h, out 62h 01h, in 62h 55h 1-d. out 66h 80h, out 62h 02h, in 62h aah 2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF and host read only. 3. 80h port, console command port80. 4. host command. 4-a. host request (LPC I/O 800h ~ 807h) 03 FD 00 00, 00 00 00 00 out 204h DAh, in 200h 00h host response (LPC I/O 800h ~ 80Bh) 03 F7 00 00, 04 00 00 00, 02 00 00 00 4-b. host request 03 EE 01 00, 00 00 04 00, 01 02 03 04 out 204h DAh, in 200h 00h host response 03 E5 00 00, 04 00 00 00, 05 05 05 05 Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e Reviewed-on: https://chromium-review.googlesource.com/269271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* core: Assert if task_get_current() cannot return a valid task IDShawn Nematbakhsh2015-06-121-0/+4
| | | | | | | | | | | | | | | | | | | If task_get_current() is called early during initialization when we have not yet done a context switch, our current_task pointer is invalid. Add an assert to detect this case and put it behind CONFIG_DEBUG_BRINGUP, a new config that's intended to enable possibly-costly pre-production debugging. BUG=chrome-os-partner:40677 TEST=Manual on glados. Define CONFIG_DEBUG_BRINGUP, then call i2c_write from board_init and verify the new assert fails. Remove the i2c_write and verify the new assert passes. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6014ccf739dcc4c8f4f960be2b89f01e423b65b5 Reviewed-on: https://chromium-review.googlesource.com/273541 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: add KBC/KMSC moduleDino Li2015-03-221-0/+6
| | | | | | | | | | | | | | | | | 1. DLM 16KB. 2. Add KBC/KMSC module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + x86 MB can boot into DOS and keyboard works. Change-Id: Ia5cc2d4f1733ce07879d410b0447b2d48e50cd95 Reviewed-on: https://chromium-review.googlesource.com/259923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* hooks: add hook for battery state of charge changeAlec Berg2015-02-031-0/+4
| | | | | | | | | | | | | | Add hook for battery state of charge change. Hook will be used to cleanup the samus charging workarounds to follow. BUG=none BRANCH=samus TEST=make -j buildall Change-Id: I99cbb8264783802139cac689804b056623063695 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/245252 Reviewed-by: Shawn N <shawnn@chromium.org>
* Stop mutex_lock() from eating pending eventsBill Richardson2014-11-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When another task is holding the lock, mutex_lock() should call task_wait_event_mask() to wait only for TASK_EVENT_MUTEX events. If it calls task_wait_event(), any pending events are silently discarded while its waiting for the the lock. BUG=chromium:435611 BRANCH=ToT,samus TEST=make buildall -j, and: Before this change, I watched the EC console while shutting down and rebooting Samus. I saw the request event arrive: [37.576295 LB lightbar_resume() requests 5 S3S0] [46.055725 LB_version] But the lightbar task never saw it. Adding a bunch of debug messages showed that it was being lost in mutex_lock(). After this change, the event is delivered: [30.167670 LB lightbar_resume() requests 5 S3S0] [30.171009 LB cur_seq 2 S3 returned pending msg 5 S3S0] [30.173816 LB running cur_seq 5 S3S0. prev_seq 2 S3] [32.410073 LB cur_seq 5 S3S0 returned value 0] [32.410865 LB running cur_seq 3 S0. prev_seq 2 S3] [39.938388 LB_version] Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I011838538960cc57171f0a3c4cdee113d156e9ff Reviewed-on: https://chromium-review.googlesource.com/231370 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-2/+2
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix firmware can't startup (re-generate)Dino Li2014-03-182-4/+5
| | | | | | | | | | | | | | | | | | | | | | Some section(entry point, interrupt vector, e-flash signature and so on) of linker script file are not linked. The start address of e-flash signature should always at 00000080h. Default firmware treats VCC logic high to prevent pin 11 logic low but use following functions. (EC2I, KBC, SWUC, PMC, CIR, SSPI, UART, BRAM, and PECI) Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Firmware can startup on IT8380 emulation board. Change-Id: I9860ac5b99dcc6e9e00dbc9d1e79a141237b7789 Reviewed-on: https://chromium-review.googlesource.com/190008 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* discard unused functions at link timeVincent Palatin2014-03-111-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Put each functions in a separate section by using -ffunction-sections, then discard the non-referenced ones in the linker with -gc-sections. Force keeping a few special symbols by using the KEEP() linker directive. This modification is not saving a lot of spaces per se, but will enable larger code pruning with future optional features. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall, manually check discarded symbols in the .map file and run on Spring and Link. The size delta is the following: Link: total 85.7k -> 84.9k (.text 60.3k -> 59.5k) Spring: total 59.2k -> 57.2k (.text 44.4k -> 42.5k) Change-Id: Ib6eb0d3f2cc4fc172c9fc26acac2e486921690a3 Reviewed-on: https://chromium-review.googlesource.com/189224 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Move CLZ emulation to common codeVincent Palatin2014-03-062-39/+5
| | | | | | | | | | | | | | | | | | | Move the CLZ instruction emulation C code to the common directory, so it can be reused for all CPU cores missing a CLZ instruction (e.g. CortexM0). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board with Cortex-M0 core, and pass all available unit-tests on target. Change-Id: Ief56cac7430fcb0fbced8a8925250c89cbd0bcfc Reviewed-on: https://chromium-review.googlesource.com/188981 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* nds32: WORKAROUND for toolchain bug on rodataVincent Palatin2013-12-101-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the toolchain tries to put a relocation which is not suitable to access variables in a read-only section. The nds32 gcc uses GP-relative signed 17-bit relocation to access variables stored in .rodata (eg lwi.gp $r0, [ +gp ]) That's wrong since $gp is pointing in the middle of .data and .bss in the SRAM, while .rodata is sitting in flash. Since on IT8380, the flash is at 0x00000 and the SRAM is at 0x80000 (512kB further), the linker will fail trying to create the signed 17-bit relocation (it detect that it needs to truncate it) Force the compiler to put another relocation as a workaround for now. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24378 TEST=./util/make_all.sh ; make BOARD=it8380dev check "version" and "gpioget" on spring, link and it8380dev. Change-Id: Ife50adf3a26be28f113292f73a1a70e8d74b5d8c Reviewed-on: https://chromium-review.googlesource.com/176913 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ite: Port OS layer to Andestar v3m architectureVincent Palatin2013-12-1011-0/+1310
This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
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