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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-55/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* Revert "core/riscv-rv32i: Add exception_panic"Nicolas Boichat2021-01-111-4/+0
| | | | | | | | | | | | | | | | | | This reverts commit b3584dd1ea0b11c269424ab7693cb9609b15e568. We found a more efficient way to trap integer division by zero, so this code is technically not required anymore. BRANCH=none BUG=b:173969773 TEST=make buildall Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I3a89ab17477258c46a701935af121c3a4b0d41b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612227 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Add exception_panicNicolas Boichat2020-12-301-0/+4
| | | | | | | | | | | | | | | | | | | software_panic is meant for exceptions that are usually software-driven (stack overflow, etc.). Create a new exception_panic function that can be used for the corner cases where we want to replicate exception behaviour of other cores (e.g. integer division by zero), that we do not want to be disabled by CONFIG_SOFTWARE_PANIC. BRANCH=none BUG=b:173969773 TEST=buildall Change-Id: I2253383e356637a62a401f0e695388e514de330f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606167 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* risc-v: add comments about not needing 16-byte stack frame alignmentDino Li2020-05-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we are not actually executing on a stack frame that is not 16-byte aligned, we are following the guidance (linked below). Add comments for future developers to explain why. Also, saving system stack pointer in the switch to function since the isr function takes special care to not over write the stack pointer when we are already using the system stack. According to documentation, the stack frame should be 128-bit aligned upon entering function boundaries. "In the standard RISC-V calling convention, the stack pointer sp is always 16-byte aligned" from https://riscv.org/specifications/isa-spec-pdf/ "The stack grows downwards (towards lower addresses) and the stack pointer shall be aligned to a 128-bit boundary upon procedure entry" from https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md See also documentation issues discussing this https://github.com/riscv/riscv-elf-psabi-doc/issues/21 BRANCH=none BUG=none TEST=ITE RISC-V FPU implementation still works Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I3460e6ee2b68c7793c72517e7d2d9bc645aaea65 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2173119 Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core:RISC-V / chip:IT83202Dino Li2019-06-111-0/+51
The IT83202 is an embedded controller with RISC-V core. It supports maximum ram size to 256KB and internal flash to 1MB. BUG=none BRANCH=none TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...) on it83202 EVB. Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>