Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | core/riscv-rv32i: remove return values | Tzung-Bi Shih | 2020-06-04 | 1 | -6/+3 |
* | core/riscv-rv32i: do not expose get_sw_int() | Tzung-Bi Shih | 2020-05-19 | 1 | -5/+0 |
* | core/riscv-rv32i: move interrupt details to IT83XX specific | Tzung-Bi Shih | 2020-05-19 | 1 | -0/+10 |
* | core:RISC-V / chip:IT83202 | Dino Li | 2019-06-11 | 1 | -0/+59 |