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* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-022-2/+2
* atomic: remove deprecated atomic functionsDawid Niedzwiecki2020-10-301-56/+0
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-11/+10
* core/riscv-rv32i: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-131-0/+38
* core/riscv-rv32i: rename atomic inc and decDawid Niedzwiecki2020-10-071-4/+4
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-062-6/+6
* riscv-rv32i/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-19/+25
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-292-17/+29
* it83xx: read_clear_int_mask() read and clear interrupt bit.Dino Li2020-09-241-8/+8
* riscv-rv32i: Enable FPU extension only if CONFIG_FPU is enabledDino Li2020-08-201-1/+3
* npcx: add support for rom resident sectionsKeith Short2020-08-131-0/+13
* linker: change symbol used to track available flashKeith Short2020-08-051-2/+8
* linker: Add flash sizes as linker defined labelsKeith Short2020-08-051-0/+11
* ec: change usage of dummySam Hurst2020-08-051-2/+2
* hooks: Introduce chipset resume init and suspend complete hooksWai-Hong Tam2020-07-301-0/+10
* core: nds32/riscv-rv32i: fix issue of time in exceptions is negativeDino Li2020-07-241-7/+8
* ec: change usage of "sane" per inclusive languagePaul Fagerburg2020-07-222-2/+2
* riscv-rv32i: correct printf formatEric Yilun Lin2020-07-221-7/+7
* core/riscv-rv32i: add atomic_inc and atomic_decTzung-Bi Shih2020-07-031-6/+11
* core/riscv-rv32i: set volatile for in_interruptTzung-Bi Shih2020-06-101-1/+1
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-061-0/+4
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-041-6/+3
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-042-10/+21
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-031-0/+6
* core/riscv-rv32i: remove get_sw_int()Tzung-Bi Shih2020-05-291-9/+1
* core/riscv-rv32i: define dummy implementation for CPU_INTTzung-Bi Shih2020-05-191-0/+5
* core/riscv-rv32i: add default __idle()Tzung-Bi Shih2020-05-191-0/+4
* core/riscv-rv32i: clean up header inclusionsTzung-Bi Shih2020-05-193-10/+4
* core/riscv-rv32i: do not expose get_sw_int()Tzung-Bi Shih2020-05-192-6/+1
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-192-9/+12
* core/riscv-rv32i: guard more IT83XX chip specific itemsTzung-Bi Shih2020-05-191-10/+7
* core/riscv-rv32i: separate CHIP_FAMILY_IT8XXX2 specific memory regionsTzung-Bi Shih2020-05-191-9/+55
* risc-v: add comments about not needing 16-byte stack frame alignmentDino Li2020-05-133-7/+48
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-211-0/+15
* core/riscv-rv32: link libgcc for 64-bit divisionDino Li2020-02-251-0/+1
* riscv-rv32i: Add sqrtf functionDino Li2020-01-223-1/+33
* core/riscv-rv32i: enable software ctzDino Li2020-01-221-0/+5
* core/riscv-rv32i: Format linker scriptCraig Hesling2019-12-161-221/+228
* core/nds32 and riscv-rv32i/ec.lds.S: no assert if section is not presenttim2019-11-221-1/+2
* Remove uses of %lEvan Green2019-10-051-4/+4
* core/riscv-rv32i: misc fixesDino Li2019-10-022-32/+29
* task: Add task_enable_task() and task_disable_task()Yilun Lin2019-08-221-0/+13
* core/riscv-rv32i: remove panic_sw_reasons[] from panic.cDino Li2019-06-141-16/+2
* core/riscv-rv32i: remove TODO from build.mkDino Li2019-06-141-4/+0
* core:RISC-V / chip:IT83202Dino Li2019-06-1113-0/+1975
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