summaryrefslogtreecommitdiff
path: root/core
Commit message (Collapse)AuthorAgeFilesLines
...
* | make verified boot feature optionalVincent Palatin2012-05-021-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this fixes the build breakage on stm32-based platforms. In the linker script, remove the ASSERT since this macro is not designed to work in that context and this size condition is already verified by the linker by setting the "length" of the "FLASH" memory region. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=daisy boot on Link and Daisy Change-Id: I08964749d44f47caa0a359bc93c303a9611e5d73
* | Add basic FMAP to EC firmware image.Bill Richardson2012-05-011-0/+13
|/ | | | | | | | | | | | | | | | | | | | | | | This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff. Still, you should be able to do things like this: flashrom -p internal:bus=lpc -r ec.bin flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat BUG=chrome-os-partner:8198 TEST=manual Build the image, look for the FMAP in it. cd src/platform/ec make BOARD=link dump_fmap ./build/link/ec.bin Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* close race condition window in expired timer processingVincent Palatin2012-04-271-30/+30
| | | | | | | | | | | | | ensure we cannot miss any timer, no matter how slow is the CPU and how many simultaneous timer we set. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9319 TEST=boot Link EC and do long key press, see the EC watchdog panic no longer happening. Change-Id: I1ecc88fc06698175444fd86cce4c0abb5e846996
* Watchdog fixesRandall Spangler2012-04-252-38/+63
| | | | | | | | | | | | | | | | | | 1) When frequency changes, reload the watchdog timer right away, or it may expire before the next reload. (Only matters when re-enabling the PLL.) 2) Split out the timer/task debug output used by the watchdog into their own routines, instead of assuming it's safe to call the command handlers. Also make the flushes in those print routines safe to call from interrupt level. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=waitms 1500; should print task dump again Change-Id: I07e0ed24a526ae499566dab0bbeb0f5755cd5be6
* Only chain from interrupt to svc_handler if an event was set.Randall Spangler2012-04-252-35/+56
| | | | | | | | | | | | | | | | (Or, if profiling is enabled.) Also, track the number of task switches if profiling is enabled. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9274 TEST=taskinfo Also test by commenting out CONFIG_TASK_PROFILING in board.h; code should still compile and run. Change-Id: Ib3dbce74b6ccfba2bbe18c7309136412c30f364e
* Use console output instead of uart output for console commandsRandall Spangler2012-04-241-9/+9
| | | | | | | | | | | | This completes console output cleanup. The remaining calls to uart_puts() and uart_printf() actually need to be that way. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual Change-Id: Ib1d6d370d30429017b3d11994894fece75fab6ea
* Refactor async console outputRandall Spangler2012-04-241-15/+19
| | | | | | | | | | | | | | | | | | This adds a 'ch' command which prints/sets which channels are active This handles all the async output; the remaining debug commands will be refactored to use ccprintf() / ccputs() in a followup CL. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual ch --> all channels active ch 0x100 -> just port80 active powerbtn -> system boots; only port 80 codes shown on console Change-Id: I9efc43acec919b62b78c2c82c61946d32380adfe
* Implement task profilingRandall Spangler2012-04-242-26/+130
| | | | | | | | | | | | | | Also tracks the distribution of IRQs, so we can see what's triggering interrupts. Task profiling is optional, enabled via CONFIG_TASK_PROFILING. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=taskinfo Change-Id: I266f2b49bff9648cda446210d5a302b460fec244
* Implement 64-bit integer printing in uart_printf()Randall Spangler2012-04-201-13/+15
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7490 TEST=timerinfo; numbers should look reasonable Change-Id: I698be99c87bf311013427ac0ed9e93e5687f40c0
* Implement HOOK_SYSJUMP and use it to preserve LPC host event maskRandall Spangler2012-04-192-0/+13
| | | | | | | | | | | | | | | | | | | | This also changes shared_mem to use all the remaining RAM, instead of reserving a fixed-size buffer. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9161 TEST=manual hostevent --> all masks should be 0 hostevent smi 0x12300000 hostevent --> should confirm SMI mask was set sysjump b hostevent --> should confirm SMI mask is still set reboot hostevent --> should confirm SMI mask is back to 0 Change-Id: Iccb6da6ccc93ee5036a3f478d24b717a462d9150
* Move externs from .lds file into a header fileRandall Spangler2012-04-194-9/+39
| | | | | | | | | | | Fewer magic externs = good. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: Ifadeb1701400c5492c40d2eaf8f68f2d70189648
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-191-1/+3
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* Add hooks module so modules can be notified of system-level events.Randall Spangler2012-04-191-0/+11
| | | | | | | | | | | | This will be used for sleep/wake/sysjump/etc. For now it's just wired up to clock frequency changing. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual: use nopll command, should still work Change-Id: Iedcea5830bc18eacfd955c29b8f793aba8905dd8
* fix task stuck on timer wake-up eventVincent Palatin2012-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | When we are in interrupt context and doing a task_set_event, if we are interrupted by a timer interrupt firing, we might end resetting the runnable bit added by the expiration of a timer (when finishing the interrupted read-modify-write to tasks_ready). So we need to have an atomic access there. We don't need to atomic primitives (and the associated overhead) on other tasks_ready accesses because there are always done at the highest priority. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8721 TEST=from Linux, run "ectool lightbar test" several times and see that the keyboard task no longer ends up stuck with a timer event set and no runnable bit. Change-Id: Ied45ee33cb6aba4549626d35d694f1c259f2400c
* Re-enable watchdog in watchdog_reload()Randall Spangler2012-04-121-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8971 TEST=manual waitms 1500 (see watchdog trace) waitms 1500 (should see watchdog trace again) waitms 3000 (should see trace, then system should reboot) Change-Id: Ieb5009d7a7bc9e1ed795e58efb0cb44a1eeb2706
* Stack overflow detectionVic Yang2012-04-101-8/+11
| | | | | | | | | | | | | Fix some mistakes in previous commit. Modified some comments and moved guard value initialization to a more readable place. Signed-off-by: Vic Yang <victoryang@google.com> BUG=chrome-os-partner:8069 TEST=Compile with detection enabled. Cause a task to overflow and see device halted. Hook gdb and see it stopped at the assertion. Change-Id: I608ee9aec3fda8c3945e1874d4bbb2c4ae1fc6dd
* Stack overflow detectionVic Yang2012-04-101-2/+14
| | | | | | | | | | | | Use guard value to detect stack overflow Signed-off-by: Vic Yang <victoryang@google.com> BUG=chrome-os-partner:8069 TEST=Compile with detection enabled. Cause a task to overflow and see device halted. Hook gdb and see it stopped at the assertion. Change-Id: I3417cca8edf4e1291ccb7848bd564b631a9ce463
* Support dynamically changing the system clockRandall Spangler2012-04-092-2/+14
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
* Change task messages to eventsRandall Spangler2012-04-062-27/+14
| | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7461 TEST=manual make BOARD={bds,link,daisy} make tests flash link system and make sure it boots Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
* Support warm reboot from one EC image to another.Randall Spangler2012-03-193-7/+24
| | | | | | | | | | | | | | | | | | | | | This is necessary at init-time for verified boot to jump from RO to one of the RW images. It's also used by factory EC update to update one image and then jump to the updated image to finish the update. In this case, the x86 does NOT reboot. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8449 TEST=manual 1) power on x86 and log in 2) sysjump a --> system is in a; x86 has not rebooted 3) sysjump ro --> system is back in RO; x86 has not rebooted 4) reboot -> system is in RO; x86 HAS rebooted Change-Id: I9dbadcf9775e146a0718abfd4ee0758b65350a87
* ensure the re-scheduling is not interruptedVincent Palatin2012-03-141-3/+2
| | | | | | | | | | | | | | The re-scheduling is protected by increasing our priority to -1, according to ARMv-M architecture manual, we need an ISB after setting the faultmask register to ensure that the new priority is visible. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8492 TEST=run on proto-0.5 and see that the temperature sensor and battery tasks are longer hanging (see the bug for details how to check it) Change-Id: Ia55859cf5c9101a09c61be7647a920126fc0a3b9
* mutex: retry immediatly if we could not get exclusive accessVincent Palatin2012-03-141-2/+5
| | | | | | | | | | | | | | | When updating the lock field of the mutex to acquire it, if the store exclusive fails, we want to retry immediatly else if the failure has been triggered by the other user doing the mutex_unlock we might not be woken up. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8492 TEST=run on proto-0.5 and see that the temperature sensor and battery tasks are longer hanging (see the bug for details how to check it) Change-Id: I0c8a4e997666a7781b3837f0dbbc47ffbc06b6c3
* Add a trap for tasks which exit their task functionsRandall Spangler2012-03-062-11/+21
| | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8350 TEST=manual Hack a task function to return. Then see that it prints an error to the debug console and the EC continues running, instead of seeing a hard-fault. Change-Id: Iacd2b83c4d4845bb8e6c61e07c3150df8edc7e49
* update versioning information stored in the ECVincent Palatin2012-03-022-5/+10
| | | | | | | | | | | | | | | Add build information (date/time/builder) which can be displayed at the EC console. Generate a version from the board name and the branch tag. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chromium-os:27013 TEST=on BDS, run version command on the console. inspect the built binary. Change-Id: Idb1f68898ba6b811d02919f17ab4536ed9f8934a
* Register host commands the same clever way we do console commandsRandall Spangler2012-02-281-0/+3
| | | | | | | BUG=none TEST=run assorted ectool commands Change-Id: I830d3cbf2d1557b3ab455ec8736d3de5e5d3e697
* Change TMP006 temperature calculation to use FP.Vic Yang2012-02-151-9/+12
| | | | | | | | | | | | | | The temperature calculation currently uses fixed point operations. Change it to use floating point for better readability and maintenance. Also changes disable_fpu() to accept parameter which serves as optimization barrier to prevent floating point operations after disabling FPU. BUG=chrome-os-partner:7801 TEST=In console, tempremote "tempremote 29715 -105000 6390" gives 28506. Change-Id: Ib766904b8feb9a78eac9f7cd53afeca85091c5a5 Signed-off-by: Vic Yang <victoryang@chromium.org>
* Sqrt function for Cortex-MVic Yang2012-02-161-0/+24
| | | | | | | | | | Add an arch include folder. Implement sqrtf for Cortex-M in math.h. BUG=chrome-os-partner:7920 TEST=none Change-Id: Ib7b480b6a0bf7760f014a1f73df54673a9016cb6 Signed-off-by: Vic Yang <victoryang@chromium.org>
* FPU controlVic Yang2012-02-164-0/+58
| | | | | | | | | | | | | Implement enable_fpu() and disable_fpu(). enable_fpu() disables interrupt and then enables FPU. disable_fpu() disables FPU and enables interrupt. Also added a CONFIG_FPU flag. BUG=chrome-os-partner:7920 TEST=none Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521 Signed-off-by: Vic Yang <victoryang@chromium.org>
* Remove useless header includesVincent Palatin2012-01-261-1/+0
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 2/4 Avoid introducing platform specific dependencies in common files where they are not necessary. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=build for BDS and Link Change-Id: If2ccd022e4956425222b55a5a48ca7522857e7f0
* Move SoC-independant headers to another directoryVincent Palatin2012-01-261-0/+65
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 1/4 The atomic operations are SoC independant since they are only using LDREX/STREX instructions which are just core specific ARMv7-M). The watchdog header defines the API which is common to all platforms. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands
* NVIC registers are not SoC specificVincent Palatin2012-01-252-6/+29
| | | | | | | | | | | | | Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
* Add configuration parameters for the panic UART codeVincent Palatin2012-01-251-9/+6
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 4/5 Allow to use the common code for most SoC. Also simplify the UART code, we don't need speed on the panic path. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=trigger a panic and check the UART output on BDS Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
* Move OS files to a CPU specific directoryVincent Palatin2012-01-257-0/+1226
Preparatory work to introduce a second SoC : 3/5 We split the drivers files which contain SoC specific drivers from the OS files which only depend the actual CPU core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and test a few commands on the console. Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
View Lorry Controller Status