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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-0597-12564/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* core/minute-ia: Remove .func and .endfuncTom Hughes2021-09-291-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | .func and .endfunc were used to emit STABS debug information (not DWARF). These only have an effect with -gstabs, which we're not using. I suspect their inclusion was not intentional. STABS is not supported when building with clang, so it generates the following errors: core/minute-ia/switch.S:27:1: error: unknown directive .func __task_start ^ core/minute-ia/switch.S:42:1: error: unknown directive .endfunc See https://bugs.llvm.org/show_bug.cgi?id=20424 and https://sourceware.org/gdb/current/onlinedocs/stabs.html. As indicated by the TEST line, the output is indentical before and after this change. BRANCH=none BUG=b:172020503 TEST=make CC=clang V=1 BOARD=arcada_ish TEST=./util/compare_build.sh -b all -j 70 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1e1e5f57fb382797e01dcf797d72de0468150054 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193271 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core: Add forward declaration for IRQ handler routineTom Hughes2021-09-274-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns when attribute declarations do not precede definitions: error: attribute declaration must precede definition [-Werror,-Wignored-attributes] The cortex-m/irq_handler.h file uses the "__keep" attribute on "routine". The declaration with the attribute must come before the definition or the compiler will ignore it. This results in link errors when using LTO with lld since it is optimized out. In order to fix this, the DECLARE_IRQ instances must be moved before the function definitions. However, if DECLARE_IRQ instances are moved without this change, we will get an implicit declaration compiler error: error: implicit declaration of function 'uart_interrupt' This change does not change the resulting output as verified by the "compare_builds.sh" script. BRANCH=none BUG=b:172020503 TEST=./util/compare_builds.sh -b all -j 70 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Icb282cb0f0a0557d6bc1d184378c5923d0e3a72d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182634 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* core/cortex-m0: Fix assemblyTom Hughes2021-09-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling with clang, the following error is reported: core/cortex-m0/switch.S:107:12: error: unknown token in expression ldr r0, =#0xe000ed04 @ load 0xe000ed04's address ^ This change fixes the syntax, which generates the identical output before and after the change: /opt/coreboot-sdk/bin/arm-eabi-objdump -d build/servo_micro/RW/core/cortex-m0/switch.o 0000006a <pendsv_handler>: 6a: b508 push {r3, lr} 6c: 4807 ldr r0, [pc, #28] ; (8c <pendsv_handler+0x22>) BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 70 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I379510f7aa00f61ae24ae8463c49d9cd3b832752 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3183391 Reviewed-by: Patryk Duda <patrykd@google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/cortex-m: Disable warning in vecttable.c when building with clangTom Hughes2021-09-231-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | The vecttable logic explicitly routes unused IRQs to IRQ_UNUSED_OFFSET, and then assigns it to "null" at the very end. The result is something like: [8] = __attribute__((used, weak, alias("default_handler"))) irq_55_handler(void); [8] = __attribute__((used, weak, alias("default_handler"))) irq_56_handler(void); ... [8] = (void*)0 This is intentional so that it works with a varying values for CONFIG_IRQ_COUNT. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3ba4eeaa46cd2c50c65c922f4c0c463ce1bb585e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172038 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* cortex-m/panic: Introduce CONFIG_PANIC_STRIP_GPR optionPatryk Duda2021-09-161-1/+39
| | | | | | | | | | | | | | | | | | | | | | | If set, this option will prevent saving General Purpose Registers during panic. When software panic occurs, R4 and R5 will be saved, because they contain additional information about panic. This should be enabled on boards which are processing sensitive data and panic could cause the leak. BUG=b:193408648 BRANCH=none TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo' to check what was saved. When CPU exception occurred registers R0-R12 should be set to 0. In case of software panic, R4 and R5 can contain panic reason and additional information. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m0/task: Check if interrupts are enabled before switching taskPatryk Duda2021-09-061-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Switching task with disabled interrupts leads to Hard Fault on Cortex-M0 because: - SVCall exception have configurable priority (full list can be found at 2.3.2 Exception types PM0215 p.23) - We are using 'cpsid i' to disable interrupts. This instruction sets PRIMASK bit (3.7.2 CPSID CPSIE PM0215 p.62) - When PRIMASK bit is set, all exceptions with configurable priority are disabled (PM0215 p.16), so SVCall is masked too If Hard Fault is inevitable, it will be a good idea to catch this earlier. It will save time spent debugging why Forced Hard Fault happens. In functions responsible for enabling, disabling or making task ready we postpone task switch when interrupts are disabled BUG=b:190597666 BRANCH=none TEST=Compile and flash EC on boards with Cortex-M0 and make sure that it works properly. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Id3be74e977ae5d5eed79aad78ee378fa413ed4ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953229 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/task: Check if interrupts are enabled before switching taskPatryk Duda2021-09-061-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switching task with disabled interrupts leads to Forced Hard Fault on Cortex-M3/M4/M7 because: - SVCall exception have configurable priority (full list can be found at 2.4.2 Exception types PM0253 Rev 5 p.40) - We are using 'cpsid i' to disable interrupts. This instruction sets PRIMASK bit (3.12.2 CPS PM0253 Rev 5 p.176) - When PRIMASK bit is set, all exceptions with configurable priority are disabled (PM0253 Rev 5 p.25), so SVCall is masked too - SVCall is escalated to Forced Hard Fault because "A fault occurs and the handler for that fault is not enabled" (PM0253 Rev 5 p.48) If Hard Fault is inevitable, it will be a good idea to catch this earlier. It will save time spent debugging why Forced Hard Fault happens. In functions responsible for enabling, disabling or making task ready we postpone task switch when interrupts are disabled BUG=b:190597666 BRANCH=none TEST=Compile and flash EC on boards with Cortex-M3/M4/M7 and make sure that it works properly. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I50976154b0cf0307c5334f6f03e4b3bc137a4ffc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953228 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Provide 'is_interrupt_enabled' function for all coresPatryk Duda2021-09-066-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a function that will provide information if interrupts are enabled. This information will be used to fix shortcomings in common code for UART buffering and usleep(). BUG=b:190597666 BRANCH=none TEST=make -j buildall TEST=make runhosttests TEST=Note for running tests: this patch only adds function implementation so, to test this it is necessary to add some code which uses the function eg. console command which prints information if interrupt is enabled. Minute-ia core: It is necessary to compile firmware for ISH (Intel Sensor Hub) which is available on drallion board (eg. chromeos6-row1-rack9-host19). Firmware must be placed in /lib/firmware/intel/drallion_ish.bin (partition must be writeable, if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock it, don't forget about reboot). After copying firmware to /lib/firmware/intel/ it is necessary to reboot DUT. After reboot use `ectool --name=cros_ish version` to check if correct version is running. NDS32 core. This core is used in it8320dx chip which is present in ampton (octopus family). EC can be compiled using 'make BOARD=ampton' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which is based on risc-v. EC can be compiled using 'make BOARD=hayato' and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to be disabled using 'set_gbb_flags.sh 0x200' Cortex-M, this is the most common core. Just compile EC for platform which contains Cortex-M core (eg. bloonchipper) and test if it works. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227 Commit-Queue: Marcin Wojtas <mwojtas@google.com> Tested-by: Patryk Duda <patrykd@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* builtin: Add math.hTom Hughes2021-08-315-15/+15
| | | | | | | | | | | | | | | | | | | | Add a "math.h" to "builtin" and rename "math.h" in the "core" directories to "fpu.h". "builtin" is the directory containing headers that mirror those in the standard library and is used for device builds. The host builds exclude the "builtin" directory and use the standard library. Without this change, building host tools such as "ectool" and attempting to include "math.h" would result in incorrectly picking up the "math.h" from the device "core" directory, not the standard library version. BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Id6b2df42cb0ff5ec2cfc07aa8f29861da6804bdf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130625 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* riscv: panic: S0/S1 are clobbered registers in software_panic()Dino Li2021-08-231-2/+2
| | | | | | | | | | | | | | | | So compiler won't use these two registers to store any other value in the function. This fixed software panic info isn't correct issue when LTO is enabled. BRANCH=asurada BUG=b:179206540 TEST=Run "crash assert" on hayato, the software panic info is correct. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I4a94e7ea94ebc0bf4f056de58edb66c2962d669d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3113485 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* Revert "make: Compile host tests in 32-bit mode"Evan Green2021-08-021-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 1821e9423af84c7a126a4a15303c6492dd44e94b. Reason for revert: This change broke the build. BUG=b:195332627 TEST=None BRANCH=None Original change's description: > make: Compile host tests in 32-bit mode > > Compile the host tests in 32-bit mode instead of 64-bit mode as it's > more likely to match the actual environments our ECs run on. For > instance, in 32-bit mode the tests might actually have a prayer of > finding a torn read or write bug, whereas in 64-bit mode 64-bit integers > are always operated on atomically. > > BUG=b:179062230 > BRANCH=none > TEST=make -j runhosttests BOARD=host on x86_64 and i686 > > Signed-off-by: Evan Green <evgreen@chromium.org> > Change-Id: I02517066337ec08c311c1f7daae5d3de84b1f4c2 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059231 > Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Bug: b:179062230 Change-Id: I35bcac77deeb1d031a31b32d911781f5fed4ab13 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067826 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Reviewed-by: Allen Webb <allenwebb@google.com> Tested-by: Evan Green <evgreen@chromium.org>
* test: Start host test timer near 32-bit rolloverEvan Green2021-08-021-2/+12
| | | | | | | | | | | | | | | Rather than starting the timestamp at 0 for each test, let's start it just before the 32-bit rollover. This gives us more of a chance to catch 32-bit rollover issues in the tests. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: Ia0551b4409c4bc63938f319312f6c66acf7c6cd9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059233 Reviewed-by: Diana Z <dzigterman@chromium.org>
* make: Compile host tests in 32-bit modeEvan Green2021-08-021-1/+3
| | | | | | | | | | | | | | | | | Compile the host tests in 32-bit mode instead of 64-bit mode as it's more likely to match the actual environments our ECs run on. For instance, in 32-bit mode the tests might actually have a prayer of finding a torn read or write bug, whereas in 64-bit mode 64-bit integers are always operated on atomically. BUG=b:179062230 BRANCH=none TEST=make -j runhosttests BOARD=host on x86_64 and i686 Signed-off-by: Evan Green <evgreen@chromium.org> Change-Id: I02517066337ec08c311c1f7daae5d3de84b1f4c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059231 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m*: make watchdog code more readableRicardo Quesada2021-07-302-4/+20
| | | | | | | | | | | | | | | | | This CL makes the code more readable by adding comment / defines regarding the meaning of PSP[5] and PSP[6]. BUG=None TEST=make buildall BRANCH=None Change-Id: I0cbe7384e20f0287096624a00b0ec19c0fb7f9bd Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059814 Tested-by: Ricardo Quesada <ricardoq@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ricardo Quesada <ricardoq@chromium.org> Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
* atomic.h: atomic_clear_bits: return previously stored valueTing Shen2021-07-296-11/+14
| | | | | | | | | | | | | | | make the api consistent with other atomic methods BUG=b:192422592 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I6cae4d521b44706cf7f44c669bf6964a08855b4c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058080 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cortex-m/ec.lds.S: Add padding to manage RW image sizeEthan Huang2021-07-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431 used in Munna), RW image size is not always 8-byte alignment which leads to the failure from flash_range_ok and therefore "EC sync update RW proecess" fails. Here is the proposal of RW image size alignment with CONFIG_FLASH_WRITE_SIZE. 1. Add output section .rw_image_size_alignment for padding 2. Expose new __image_size for hash afterward 3. Make output senction .rw_image_size_alignment !CONFIG_CHIP_INIT_ROM_REGION guarded BRANCH=main BUG=b:188117811 TEST=make buildall + checking symbols (execpt __image_size) listed in ec.R{O,R}.smap for all boards stay the same Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416 Signed-off-by: Ethan Huang <ethan.huang@stmicro.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32/system: Disable caches before rebootPatryk Duda2021-06-102-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* cortex-m/watchdog: Flush and invalidate D-cache while handling watchdogPatryk Duda2021-06-091-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with RO reporting 'sysjump' reset cause, but not 'watchdog' after issuing 'crash watchdog' command. Also, problem with missing task ID and PC in saved panic data was fixed too. These problems come from not flushing cache before reset occurs. When cache is enabled, it's not guaranteed that all memory changes will be saved in RAM. After reboot, cache is invalidated, so some of memory changes will be lost. In this case, 'magic' field from jump_data structure was not zeroed and part of panic data was missing. It caused RO to report sysjump after watchdog was triggered, and missing 'watchdog' reset cause (RO used reset cause from jump data). BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'crash watchdog'. Make sure that RO reports 'watchdog' reset cause. After sysjump to RW check panic data using 'panicinfo' command. Especially the following: - R4 register (crash reason) should be set to 0xdead6664 (watchdog) - R5 register (info) should be set to PC - PROCESS EXCEPTION value should be set to task ID Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ie8d861e5a07b58140445aeaa191cc0098618401b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923504 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cortex-m/panic: Flush D-cache after panic data is filledPatryk Duda2021-06-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi After writing panic information it is good to flush cache to make sure that all changes are in RAM. Without this, 'panicinfo' will report incorrect values after reboot. BUG=b:170432597 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, use 'crash' command to trigger panic (do not use 'crash watchdog' it uses different path). Make sure that after sysjump to RW panic data contains correct information. Panic data can be dumped using 'panicinfo' command. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Iabe2b1de00683d95f55a3124b46dfa600f8ac0bf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923503 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-091-1/+1
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* panic.c: force sync before reenabling bus faultsJosie Nordrum2021-05-111-0/+5
| | | | | | | | | | | | | | | | | | Force a sync between data and instruction pipelines before allowing bus faults. Remove sync from flash-stm32h7.c BRANCH=None BUG=b:157692395 TEST=tested with crrev.com/c/2576799 Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Id67324191b4447d9be10c0b5aecc87620aa69d1d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706039 Tested-by: Josie Nordrum <josienordrum@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Josie Nordrum <josienordrum@google.com> Auto-Submit: Josie Nordrum <josienordrum@google.com>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSJeremy Bettis2021-04-274-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac1d81e1430dbfbfba1376a23ab19dfa845d7ef. The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=chromium:1202406,b:180980668 TEST=make -j16 runhosttests buildall && zmake testall && \ /mnt/host/source/src/platform/ec/zephyr/firmware_builder.py --metrics \ /tmp/tmplt8ty8ci test ; echo $? BRANCH=none Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I5b5e58b30d936b5232e049827f458d9a2ed06340 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855320 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "config: rename CONFIG_FLASH to CONFIG_FLASH_CROS"stabilize-13935.B-mainJack Rosenthal2021-04-244-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a. Reason for revert: responsible for CQ failures (crbug.com/1202406) BUG=chromium:1202406 BRANCH=none TEST=CQ Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Original change's description: > config: rename CONFIG_FLASH to CONFIG_FLASH_CROS > > The config name collides with the same config name in zephyr. > > Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to > CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig > side. > > BUG=b:180980668 > TEST=make buildall > BRANCH=none > > Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 > Signed-off-by: Eric Yilun Lin <yllin@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 > Tested-by: Eric Yilun Lin <yllin@google.com> > Reviewed-by: Keith Short <keithshort@chromium.org> > Commit-Queue: Keith Short <keithshort@chromium.org> Bug: b:180980668 Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274 Auto-Submit: Jack Rosenthal <jrosenth@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-234-12/+12
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* riscv-rv32i/task: Remove the remove_me functionDino Li2021-04-081-12/+0
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=buildall. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I2cd176556f2294de304eca3d2e3d29f68cff85dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531769 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Hooks: Add HOOK_CHIPSET_HARD_OFFDiana Z2021-03-186-0/+24
| | | | | | | | | | | | | | | Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry to the G3 power state. BRANCH=None BUG=b:166787955,b:167996216,chromium:1045209 TEST=make -j buildall, runs on waddledee with no linking errors Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/riscv-rv32i: rearrange symbols in ILMTing Shen2021-03-031-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbol `current_image_data` must be located in a static place, so EC-RO can always find the required information inside EC-RW. Move the symbol to a lower offset to make it's location not affected by future code change. BUG=b:181203269 TEST=1) bootable on hayato 2) ec.RW.smap: 80080000 T __flash_dma_start 80080000 t __startup 80080004 t __irq 80080008 t __ec_intc 80080080 T eflash_sig 80080090 T current_image_data 80080090 T __image_data_offset 800800c0 T __entry_irq_0 ... 800800fc T __entry_irq_15 80080100 T __entry_syscall 80080104 t __irq_isr BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iaf05ed8f758d99981eec432afbe404ac2c469dec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722051 Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cortex-m/m0: Add Debug Halting Control and Status RegisterTom Hughes2021-02-236-2/+53
| | | | | | | | | | | | | | | | | | | | | For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR" in the ARMv6-M Architecture Reference Manual. For other Cortex-M, see "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M Architecture Reference Manual or https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register. BRANCH=none BUG=b:180144572 TEST=Using Segger J-Trace Pro with icetower v0.1, verify debugger_is_connected is true when debugger is attached and false otherwise Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748fc26c0db4351be5a83086fdb843e5651b5425 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713753 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/riscv-rv32i: set in_interrupt at beginning of exception handlerTzung-Bi Shih2021-02-192-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 3 paths when receiving an excaption in core/riscv-rv32i/init.S: 1. __irq_handler 2. excep_handler 3. unhandled_interrupt Originally, in_interrupt_context() returns true only if it goes to 1st path. However, the rest paths are also in interrupt context, especially some function may rely on in_interrupt_context(), for example, uart_flush_output() in common/uart_buffering.c. Note that, only the 1st goes back to normal context. The rest of paths are all going to panic and reset. Sets in_interrupt at the beginning of exception handler instead of start_irq_handler() so that the flag is ON when receiving an exception. BRANCH=none BUG=b:180571536 BUG=b:163300760 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Iba689c506c02c4b5bb1668766f1d7ab5f86f72a4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2702999 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* cortex-m0: convert "b" register constraints to "l"Peter Marheine2021-02-181-4/+4
| | | | | | | | | | | | | | | | | | GCC defines the "b" constraint for ARM targets as the union of the stack register and low registers (r0-r7), but that constraint is marked as internal (not intended for general use) and is not supported by Clang. Instead use "l" (the low registers only), which is intended for general use and supported by clang. BUG=b:172221010 TEST=builds BRANCH=None Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I584274b2aa1c68dfdfef80de779191d1f4d0e7b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695054 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* core/cortex-m/mpu.c does not compileDenis Brockus2021-02-051-1/+2
| | | | | | | | | | | | | | | | | Fix for loop to be compatible with the tools used in the builders BUG=chromium:1175163, chromium:1175181 BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ic4d6f1b8aea0e20391eeb0d9496275289a7e21fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678794 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jae Hoon Kim <kimjae@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* riscv-rv32i: store EC interrupt number in panic infoDino Li2021-02-042-24/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change stores EC INT number in panic info (TP register) if the number isn't valid. For CPU interrupt and exception code, we can check mcause register in panic info. BUG=b:179206540 BRANCH=none TEST=fire an invalid EC INT (eg, number 188) and checking panic info to see if the number is stored in TP: === EXCEPTION: MCAUSE=8000000b === S11 00000000 S10 00000000 S9 00000000 S8 00000000 S7 00000000 S6 00000000 S5 ffe17b7f S4 fff0bdc0 S3 0000fffe S2 00000000 S1 00000000 S0 00000000 T6 00000000 T5 00000000 T4 00000058 T3 00000009 T2 00000000 T1 00000010 T0 00000800 A7 00000000 A6 00000001 A5 80026860 A4 ffffffff A3 00000008 A2 80109be8 A1 00000000 A0 0000f304 TP bad000bc GP 80103930 RA 80000f2c SP 80106bb8 MEPC 80000dee Exception type: Environment call from M-mode Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If4ead38266d1c5b3453d5dd5e5f65de5af793f57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2638998 Commit-Queue: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-154-4/+4
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* core/riscv-rv32i: correct inline assembly constraint modifierTzung-Bi Shih2021-01-141-1/+1
| | | | | | | | | | | | | | | | | | | To make compiler translate the inline assembly well, use '&' modifier to tell compiler that the `locked' variable is written before the instruction is finished using the input operands[1]. [1]: https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#Modifiers BRANCH=none BUG=b:176959740 BUG=b:177287581 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3f6e5741afeaf98bf8f8e736c6d8db58daac6a17 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2623869 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Revert "core/riscv-rv32i: Add exception_panic"Nicolas Boichat2021-01-112-16/+7
| | | | | | | | | | | | | | | | | | This reverts commit b3584dd1ea0b11c269424ab7693cb9609b15e568. We found a more efficient way to trap integer division by zero, so this code is technically not required anymore. BRANCH=none BUG=b:173969773 TEST=make buildall Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I3a89ab17477258c46a701935af121c3a4b0d41b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612227 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Use -fsanitize-undefined-trap-on-errorNicolas Boichat2021-01-112-11/+3
| | | | | | | | | | | | | | | | | | | Let's use -fsanitize-undefined-trap-on-error instead, to trap division by zero. This only adds 2 instructions to each division (a branch and an ebreak). BRANCH=none BUG=b:173969773 TEST=crash divzero crashes asurada TEST=tast run -var servo=localhost:9999 dut9999 crash.ECCrash passes Change-Id: I50d6016d457089ddcb105026656e1bf09bd1df81 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612226 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Enable integer division by zero UBSANNicolas Boichat2020-12-302-0/+12
| | | | | | | | | | | | | | | | | | Allows us to trap divisions by zero. It might be better to add a new compiler flag for this (e.g. -mcheck-zero-division that is only only available on MIPS currently). BRANCH=none BUG=b:173969773 TEST=crash divzero actually crashes the system, failing address available in RA register. Change-Id: Id82e035b16e05ba2970779367dd6dc8d10f4955a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605039 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Add exception_panicNicolas Boichat2020-12-302-7/+16
| | | | | | | | | | | | | | | | | | | software_panic is meant for exceptions that are usually software-driven (stack overflow, etc.). Create a new exception_panic function that can be used for the corner cases where we want to replicate exception behaviour of other cores (e.g. integer division by zero), that we do not want to be disabled by CONFIG_SOFTWARE_PANIC. BRANCH=none BUG=b:173969773 TEST=buildall Change-Id: I2253383e356637a62a401f0e695388e514de330f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606167 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Make it possible to enable LTONicolas Boichat2020-12-291-0/+5
| | | | | | | | | | | | | | | This is especially useful to reduce the total code size if we enable division by zero UBSAN. BRANCH=none BUG=b:173969773 TEST=Enable on asurada[_scp], boot Change-Id: I86212a5834e5dd86e75bc3247f4365a6e102c45e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605037 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it8xxx2: enable ILM0Dino Li2020-12-171-0/+6
| | | | | | | | | | | | | | | | | | This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/flash: workaround of IMMU tag is nds32 onlyDino Li2020-12-171-2/+0
| | | | | | | | | | | | | | This change excluded the workaround from core riscv. BUG=b:111808417 BRANCH=none TEST=On asurada and drawcia, no error while erasing and writing flash of address 0x7e000 ~ 0x7f000 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If6510b181173862684552607d688b3afb046aa2c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563356 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-146-45/+38
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m mpu: support configuring regions with difficult alignmentPeter Marheine2020-12-111-59/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing configuration code assumes that provided addresses are at least as aligned as the requested size, which is not true on NPCX797WC (and likely others) where RAM regions are only 64k-aligned but have larger sizes (like 256k). Use a new greedy approach to configuring the MPU which handles these situations corrently: for any given request take the largest possible chunk from the bottom of the memory region (subject to size and address alignment). Maximize the space by aggressively using MPU subregions- this means that in many well-aligned situations this algorithm selects a larger region than the requested size and enables one subregion, but in more difficult situations it is capable of enabling subregions with more exotic positions. BUG=b:169276765 BRANCH=zork TEST=With a test harness to print out computed configurations, manually verified the correctness of a variety taken from real chip configurations (request first, MPU region(s) indented): 0x20000000 size 0x1000 # stm32f03x 0x20000000 size 0x8000 srd fe 0x20000000 size 0x2000 # stm32f03x 0x20000000 size 0x10000 srd fe 0x20000000 size 0x2800 # stm32l100 0x20000000 size 0x4000 srd e0 0x20000000 size 0x4000 # stm32f412 0x20000000 size 0x20000 srd fe 0x80000 size 0xc000 # it8320 0x80000 size 0x20000 srd f8 0xff200000 size 0xa0000 # ish5p4 0xff200000 size 0x100000 srd e0 0x200b0000 size 0x20000 # npcx797wb 0x20080000 size 0x80000 srd e7 0x10070000 size 0x40000 # npcx797wb 0x10000000 size 0x80000 srd 7f 0x10080000 size 0x80000 srd f8 0x200c0000 size 0x10000 # npcx796f 0x20080000 size 0x80000 srd ef 0x10090000 size 0x30000 # npcx796f 0x10080000 size 0x80000 srd f1 0x10090000 size 0x20 0x10090000 size 0x100 srd fe Further verified MPU configuration with the new algorithm succeeds on Dalboz, and test/mpu.c passes on Dragonclaw. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I71d8e2b37c7e20fc7a39166b90eea0b7f7ebcf43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2434601 Reviewed-by: Edward Hill <ecgh@chromium.org>
* core/riscv-rv32i: support DRAM cacheTzung-Bi Shih2020-11-191-0/+64
| | | | | | | | | | | | | Allocates memory space for dram.* sections. BRANCH=none BUG=b:156222459 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I0825c9daf06d88929ef3410a14c176099bfa1ace Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531753 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: move essential code to ram_code only if supportsTzung-Bi Shih2020-11-191-1/+3
| | | | | | | | | | | | | | | | | | Commit "it83xx: pull more functions into __ram_code section" (https://crrev.com/c/2535899) breaks Asurada SCP. It moves some essential code to .ram_code section but only IT8XXX2 family includes .ram_code in linker script. Moves the context switch code to ram_code only if it supports. BRANCH=none BUG=none TEST=make BOARD=asurada_scp && make BOARD=asurada Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I8602f7ef0103282feeddbfe1757f7cf7fb5512dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546722 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx: pull more functions into __ram_code sectionDino Li2020-11-182-2/+4
| | | | | | | | | | | | | | | | | | Because we have space in the section, so we pulled more functions into the section. If a function is cached in __ram_code section (static cache), we can save latency of fetching code of the function from flash. (Fetching 64 bytes code from flash takes about 4us latency) BUG=none BRANCH=none TEST=buildall. Asurada and Drawcia are both able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8b413bd577c4e5b73a5c67018d17955da1ed0c55 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2535899 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nds32/task: return invalid task id if task scheduling is not yet startDino Li2020-11-182-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The send_to_cr50() uses task_disable_task() to disable console task, and task_disable_task() will also suspend a task if it is the current task (tskid == task_get_current()). But send_to_cr50() is called in main routine (task scheduling is not yet start). If a specified FW image hits condition of "tskid == task_get_current()", EC will start scheduling with unexpected status. (eg. at CL:2540390: current_task=0x80880, tasks=0x877a8, and uint8_t current_task - tasks = 9 ) BUG=b:172460745 BRANCH=none TEST=No WDT loops on drawcia Change-Id: If42ef14a198ab5f99686f8e7212151b2d6b573f5 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2544291 Tested-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Zephyr: add more compliant implementation for irq_(un)lockYuval Peress2020-11-081-2/+2
| | | | | | | | | | | | | | | | | | This change replaces the stubbed irq_(un)lock static functions defined in task.h with new functions that behave more like the Zephyr implementation of irq_(un)lock functions. This should make the migration from interrupt_(dis|en)able to Zephyr more seamless. BRANCH=none BUG=b:172060699 TEST=Added unit tests, make runtests -j, and built for various boards: eve, volteer, arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ia7ad2b8d7d411a11699353bf5d3cc36a261fad14 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511720
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