| Commit message (Collapse) | Author | Age | Files | Lines |
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Move the atomic_t definition to a separated file, common for all cores.
It will be useful for removing include loops in incoming commits related
to modifying atomic_t caused by a change in Zephyr upstream (atomic_t
from int to long).
For Zephyr, just include atomic.h which doesn't have any dependencies.
BUG=b:207082842
TEST=make buildall && zmake testall && build_compare.sh -b all
BRANCH=main
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I80910c03051cf8bb46ef79350aed2a510b65c420
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3295567
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Previous version of the Cortex-M architecture enumerated a few
possible values of the lr register, upon entering an exception
handler. The value would indicate aspects of the processor state
before being interrupted, and correspondingly how the core should
restore state when that value was loaded into the pc register upon
completion of the exception handler.
The values listed for M0 were:
0xFFFFFFF1: Return to Handler mode.
0xFFFFFFF9: Return to Thread mode.
0xFFFFFFFD: Return to Thread mode.
All other values: Reserved.
(There are differences between the two "Thread mode" value, which are
not important for this discussion.)
However, while developing code for STM32L5xx, which is Cortex-M33, I
encountered other values besides the above, and it turns out bit 3
indicates whether to return to thread mode or handler mode. See
section 2.4.7.2 in this document for details:
https://www.st.com/resource/en/programming_manual/pm0264-stm32-cortexm33-mcus-programming-manual-stmicroelectronics.pdf
With the above knowledge, I have updated the condition in task.c to
handle previously reserved values.
BRANCH=none
BUG=b:192262089
TEST=Stress test on STM32L552 Nucleo board
Change-Id: If9b1995dad39cc87490bd825ee7e35a096712923
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3297049
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the
host interface selection configs distinct from configs used to
enable/disable specific host commands.
BUG=b:195416058
BRANCH=main
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842
Tested-by: Michał Barnaś <mb@semihalf.com>
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When compiling with clang (linking with lld), there are many .data and
.bss subsections that are not being included in .data and .bss. For
example, .data.board_get_version.ver and .bss.usart3_usb_state.
The following shows the complete section output when compiling with
clang before this change:
arm-none-eabi-objdump -h build/servo_v4/RO/ec.RO.elf
build/servo_v4/RO/ec.RO.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000c39c 08000000 08000000 00010000 2**3
CONTENTS, ALLOC, LOAD, CODE
1 .rodata 00002b44 0800c39c 0800c39c 0001c39c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .data.board_get_version.ver 00000004 20000000 20000000 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
3 .data..compoundliteral.158 0000003a 20000004 20000004 00020004 2**1
CONTENTS, ALLOC, LOAD, DATA
4 .data.iface_next 00000001 2000003e 2000003e 0002003e 2**0
CONTENTS, ALLOC, LOAD, DATA
5 .data.last_tx_ok 00000004 20000040 20000040 00020040 2**2
CONTENTS, ALLOC, LOAD, DATA
6 .data.print_reg.rname 00000003 20000044 20000044 00020044 2**0
CONTENTS, ALLOC, LOAD, DATA
7 .data..L_MergedGlobals 00000068 20000048 20000048 00020048 2**3
CONTENTS, ALLOC, LOAD, DATA
8 .vtable 000000c0 200000b0 200000b0 000200b0 2**0
ALLOC
9 .bss 00000480 20000170 20000170 000200b0 2**0
ALLOC
10 .data 00000000 200005f0 0800eee0 000205f0 2**0
CONTENTS, ALLOC, LOAD, DATA
11 .usb_ram 00000278 40006000 40006000 000205f0 2**3
ALLOC
12 .bss.usart3_usb_state 00000008 200005f0 0800eee0 000205f0 2**2
ALLOC
13 .bss.usart4_usb_state 00000008 200005f8 0800eee8 000205f0 2**2
ALLOC
14 .bss..compoundliteral.64 00000008 20000600 0800eef0 000205f0 2**2
ALLOC
15 .bss..compoundliteral.66 00000040 20000608 0800eef8 000205f0 2**0
ALLOC
...
61 .bss..L_MergedGlobals.845 00000070 20003550 08011e40 000205f0 2**2
ALLOC
62 .debug_info 00014398 00000000 00000000 000205f0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
...
When compiling with gcc (and clang with this fix), we see that there is
only a single .data and .bss section (all of the subsections have been
included in .data and .bss):
build/servo_v4/RO/ec.RO.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 0000c390 08000000 08000000 00010000 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .rodata 00002a50 0800c390 0800c390 0001c390 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .vtable 000000c0 20000000 20000000 00030000 2**0
ALLOC
3 .bss 00003408 200000c0 200000c0 00030000 2**3
ALLOC
4 .data 000000b8 200034c8 0800ede0 000234c8 2**3
CONTENTS, ALLOC, LOAD, DATA
...
The output for all boards is exactly the same before and after this
change when compiling with gcc.
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=servo_v4
TEST=./util/compare_board.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Id8ae9689c739779fe048c3577e105280c3c6869b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229480
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The FPC library used on bloonchipper has bss subsections (e.g.,
bss.sensor_config). These subsections must be put within __bss_start and
__bss_end or the initialization performed in core/cortex-m/init.S will
not clear it, resulting in potentially random values in the variables
rather than zero.
Before this change:
arm-none-eabi-objdump -h build/bloonchipper/RW/ec.RW.elf
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00022eee 08060000 08060000 00010000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .rodata 00008ab8 08082ef0 08082ef0 00032ef0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .bss 000134b0 20000000 20000000 00050000 2**3
ALLOC
...
13 .bss.sensor_config 00000004 200134f0 200134f0 00050000 2**2
ALLOC
...
22 .data 000000b8 20013508 0808b9a8 00043508 2**3
CONTENTS, ALLOC, LOAD, DATA
...
After this change:
arm-none-eabi-objdump -h build/bloonchipper/RW/ec.RW.elf
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00022eee 08060000 08060000 00010000 2**5
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .rodata 00008ab8 08082ef0 08082ef0 00032ef0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
2 .bss 00013508 20000000 20000000 00050000 2**3
ALLOC
3 .data 000000b8 20013508 0808b9a8 00043508 2**3
CONTENTS, ALLOC, LOAD, DATA
...
BRANCH=none
BUG=b:172020503, b:201113851
TEST=On dragonclaw with servo_micro attached:
> fpenroll
> fpmatch
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I9a9187e05b8e734f9513ff27c49571ccb12d86df
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219872
Reviewed-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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With gcc, the generated assembly for exception_panic after this change
removes a "adds r0, r0, #0" instruction and a nop.
00000000 <exception_panic>:
0: 4b08 ldr r3, [pc, #32] ; (24 <exception_panic+0x24>)
2: 4809 ldr r0, [pc, #36] ; (28 <exception_panic+0x28>)
4: 469c mov ip, r3
; No more "adds r0, r0, #0" here
6: f3ef 8109 mrs r1, PSP
a: f3ef 8205 mrs r2, IPSR
e: 466b mov r3, sp
10: c0fe stmia r0!, {r1, r2, r3, r4, r5, r6, r7}
12: 4641 mov r1, r8
14: 464a mov r2, r9
16: 4653 mov r3, sl
18: 465c mov r4, fp
1a: 4675 mov r5, lr
1c: c03e stmia r0!, {r1, r2, r3, r4, r5}
1e: 46e5 mov sp, ip
20: f7ff fffe bl 0 <exception_panic>
; No more nop here
24: 20003f70 .word 0x20003f70
28: 20003f74 .word 0x20003f74
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=c2d2
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I5282369fd97a21b5927175adecff2ba74c4f8fc3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213608
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This assembly is supposed to force the compiler to use r0 for pregs and
r12 for pstack. When compiling with clang, it uses r12 for pregs and r0
for pstack, so the "stmia r0" instruction is using the wrong value.
Instead of assuming that pregs will be in r0 and pstack will be in r12,
just use the symbolic name ("pregs") with the stmia instruction. This
generates the correct behavior regardless of whether pregs or pstack use
r0 or r12.
With gcc, the generated assembly for exception_panic after this change
removes the "mov r0, r0" instruction and adds a nop at the end:
00000000 <exception_panic>:
0: 480e ldr r0, [pc, #56] ; (3c <exception_panic+0x3c>)
2: f8df c03c ldr.w ip, [pc, #60] ; 40 <exception_panic+0x40>
; No more "mov r0, r0" here
6: f3ef 8109 mrs r1, PSP
a: f3ef 8205 mrs r2, IPSR
e: 466b mov r3, sp
10: 05d6 lsls r6, r2, #23
12: bf1c itt ne
14: 2400 movne r4, #0
16: 2500 movne r5, #0
18: f04f 0600 mov.w r6, #0
1c: f04f 0700 mov.w r7, #0
20: f04f 0800 mov.w r8, #0
24: f04f 0900 mov.w r9, #0
28: f04f 0a00 mov.w sl, #0
2c: f04f 0b00 mov.w fp, #0
30: e880 4ffe stmia.w r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, lr}
34: 46e5 mov sp, ip
36: f7ff fffe bl 0 <exception_panic>
3a: bf00 nop ; adds nop instruction
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=bloonchipper
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I150d685bde701171630ae02b16e6050e1e0e77a6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213606
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This is the same as commit 0907090490b07357902927f089228d63a775cdf0,
which made the same change for core/cortex-m/vecttable.c.
The vecttable section was attempting to add the "a" flag, which
indicates the section is allocatable:
https://sourceware.org/binutils/docs/as/Section.html.
Comparing the "text.vecttable" ELF section headers for gcc before and
after this change, in both cases the ALLOC flag is set and there are no
other difference in flags:
arm-none-eabi-objdump -h \
build/discovery-stm32f072/RO/core/cortex-m0/vecttable.o
Sections:
Idx Name Size VMA LMA File off Algn
...
4 .text.vecttable 000000c0 00000000 00000000 0000003c 2**2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
...
However, if we examine the clang section headers before this change we
see that before the change the section name is .text.vecttable,"a",
rather than .text.vecttable:
arm-none-eabi-objdump -h \
build/discovery-stm32f072/RO/core/cortex-m0/vecttable.o
Sections:
Idx Name Size VMA LMA File off Algn
...
3 .text.vecttable,"a" @ 000000c0 00000000 00000000 00000044 2**2
CONTENTS, ALLOC, LOAD, RELOC, DATA
...
After the change, the section is correctly named .text.vecttable:
Sections:
Idx Name Size VMA LMA File off Algn
...
3 .text.vecttable 000000c0 00000000 00000000 00000044 2**2
CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
...
We also see that the ALLOC flag is correctly set.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I8d84f44266fe3bfe3a942401d9fdbe7760c6af53
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253650
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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"lsl" is not a valid instruction for Cortex-M0:
https://developer.arm.com/documentation/ddi0432/c/CHDCICDF.
Instead of "lsl", gcc will silently emit the correct variant of the
instruction ("lsls" which updates condition codes).
However, when using clang, it fails to compile due to the invalid
instruction:
core/cortex-m0/task.c:178:7: error: invalid instruction, any one of the
following would fix this:
"lsl %0, #23\n" : "=r"(ret)); /* exception bits are the 9 LSB */
^
<inline asm>:2:1: note: instantiated into assembly here
lsl r0, #23
^
core/cortex-m0/task.c:178:7: note: instruction requires: thumb2
"lsl %0, #23\n" : "=r"(ret)); /* exception bits are the 9 LSB */
^
<inline asm>:2:1: note: instantiated into assembly here
lsl r0, #23
^
core/cortex-m0/task.c:178:7: note: no flag-preserving variant of this
instruction available
"lsl %0, #23\n" : "=r"(ret)); /* exception bits are the 9 LSB */
^
Instead of writing assembly to do the shifting, use C. The generated
code adds a few instructions since we're now returning a "bool" (0 or 1)
instead of the raw shifted value:
Before:
arm-none-eabi-objdump -d build/servo_micro/RO/core/cortex-m0/task.o
00000000 <in_interrupt_context>:
0: f3ef 8005 mrs r0, IPSR
4: 05c0 lsls r0, r0, #23
6: 4770 bx lr
After:
arm-none-eabi-objdump -d build/servo_micro/RO/core/cortex-m0/task.o
00000000 <in_interrupt_context>:
0: f3ef 8005 mrs r0, IPSR
4: 05c0 lsls r0, r0, #23
6: 1e43 subs r3, r0, #1
8: 4198 sbcs r0, r3
a: b2c0 uxtb r0, r0
c: 4770 bx lr
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=servo_micro -j
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I530896186c2dbbd582f7c9973d1157ebe3601b34
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3197756
Reviewed-by: Keith Short <keithshort@chromium.org>
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Using bool makes it clear that the function returns "true" or "false",
rather than any integer. It also avoids the need to use "!!" to set the
value to 0 or 1, since the compiler ensures that "bool" is always a 0 or
1, even if another value is assigned.
BRANCH=none
BUG=b:172020503
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I164e5c03c23fa2f0ffb61e87f5613e080814ce10
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262593
Reviewed-by: Keith Short <keithshort@chromium.org>
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For consistency, make all IRQ handler routines static.
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I43dc4dd0a8cd593d6eb761768acc5c7b6b95e22b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227265
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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clang warns about the following invalid instructions in the inline
assembly:
core/cortex-m0/atomic.h:44:9: error: invalid instruction, any one of the
following would fix this:
<inline asm>:4:1: note: instantiated into assembly here
orr r3, r3, r2
^
<inline asm>:4:1: note: instantiated into assembly here
bic r2, r2, r1
^
ld.lld: error: <inline asm>:1:5: invalid instruction, any one of the
following would fix this:
mov r1, #0
^
ld.lld: error: <inline asm>:4:1: invalid instruction, any one of the
following would fix this:
sub r2, r2, r1
^
The Cortex M0 instruction set only has the variant of these instructions
that set the condition codes (e.g., "bics", "orrs"):
https://developer.arm.com/documentation/ddi0432/c/CHDCICDF.
The "s" at the end indicates that the condition flags will be updated,
but we already indicate that we are clobbering condition codes with "cc"
in the inline asm.
We need to add ".syntax unified" to tell gcc's assembler we're using
unified assembler language
(https://developer.arm.com/documentation/dui0473/c/BABJIHGJ):
/tmp/ccnA5Gkb.s:15936: Error: instruction not supported in Thumb16 mode
-- `orrs r1,r1,r3'
/tmp/ccnA5Gkb.s:15996: Error: instruction not supported in Thumb16 mode
-- `bics r1,r1,r3'
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=burnet
TEST=CC=clang make BOARD=servo_micro
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ifafaf67080e25ab2c5d2aad3efc90a9d61978bf9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3188639
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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Use __clzsi2 and __ctzsi2 from compiler_rt instead of our own version.
Using the compiler_rt versions result in a slightly smaller image.
servo_micro before this change:
RO: 18744 bytes in flash remaining
RW: 23192 bytes in flash remaining
servo_micro after this change:
RO: 18808 bytes in flash remaining
RW: 23256 bytes in flash remaining
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=servo_micro
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ibc19a3670127dde211fb20d247c1284d0aec5f61
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3199739
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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When compiling with clang, use the builtins from compiler-rt rather than
our own hand-rolled versions. When trying to compile with our versions,
clang fails to link:
ld.lld: error: core/cortex-m0/div.S:52:(.text.__aeabi_idiv+0x10):
unrecognized relocation R_ARM_THM_JUMP8
ld.lld: error: core/cortex-m0/div.S:97:(.text.__aeabi_idivmod+0x24):
unrecognized relocation R_ARM_THM_JUMP8
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=servo_v4
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I33db397c13bcdcb63bd931d0d8425f9f02a76327
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3188640
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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"-Oz" is like "-Os" (and thus "-O2"), but reduces code size further.
dartmonkey, clang, -Os:
RO: 733500 flash remaining
RW: 979488 flash remaining
dartmonkey, clang, -Oz:
RO: 737980 flash remaining
RW: 984776 flash remaining
BRANCH=none
BUG=b:172020503
TEST=make buildall
TEST=CC=clang make BOARD=dartmonkey
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ia787845ffdeff26134162007a621b902bbc0d051
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3199737
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The panic information currently dumps by debug_print API which
implemented on SCP UART. This implies that the panic information
can only be observed on SCP UART. We cannot have any information
about crashed SCP on non-development environment.
Add a new panic API to dump information on console channel, so that
panic information can be transmitted to kernel side via host command.
BRANCH=None
BUG=b:199444513
BUG=b:189356151
TEST=build pass
Change-Id: I2167d16a709fa2814f3b0a208411ae5e7f51f70b
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3225807
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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"-mno-accumulate-outgoing-args" is not a flag that clang understands.
BRANCH=ish
BUG=b:172020503
TEST=none
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I897a491d7b7c91d21d8cfa1cfb9d8470c1240650
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193274
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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By default all builds will use gcc. To build with clang, set
the environment variable CC=clang.
At this point only dartmonkey has been tested with clang.
BRANCH=none
BUG=b:172020503
TEST=Using icetower, Segger J-Trace, and servo micro:
make BOARD=dartmonkey -j
./flash_jlink.py -b dartmonkey -i ./build/dartmonkey/ec.bin
--remote 127.0.0.1:2551
=> console on icetower works
TEST=CC=clang make BOARD=dartmonkey -j
./flash_jlink.py -b dartmonkey -i ./build/dartmonkey/ec.bin
--remote 127.0.0.1:2551
=> console on icetower works
TEST=make buildall -j
TEST=CC=clang make BOARD=dartmonkey tests -j
TEST=make BOARD=dartmonkey tests -j
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Change-Id: Ib7c067d0ebe0561becfd70373216adb445501f94
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1474577
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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The config option to enable .bss.slow was removed in commit
b224441aaaa5dd08274811d65bb795b4abc231d8 because the option was only
used with kunimitsu, which was removed from the EC codebase a long time
ago.
Remove the reference in the linker maps to complete the cleanup.
BRANCH=none
BUG=b:172020503, b:172221339
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ibc519f9974cb26e6d15180e2ce0c359867ced1ac
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219263
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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When compiling with clang, it warns:
core/cortex-m0/task.c:182:19: error: unused function 'get_interrupt_context'
[-Werror,-Wunused-function]
static inline int get_interrupt_context(void)
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I914a2a8f950a340c570f5d105859a80be3efb82a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229479
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Almost all of the console commands were already static. This change
makes all of them static for consistency.
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I0ac46358b6fbafa65504c648ce4de0365cdbf723
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3224372
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I39f9d35b22d25c923a768bf86b3a16413b9f0a4b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3219871
Reviewed-by: Keith Short <keithshort@chromium.org>
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https://crrev.com/c/3169964 changed __data_lma_start from "." to
LOADADDR(.data) to fix dartmonkey when compiling with clang. This
changed the LMA address on some boards, such as voxel. Even though the
new address looks correct (matches start of .data section), we are
seeing an exception on voxel during startup. For now, keep clang and gcc
separate until we can diagnose the issue.
BRANCH=none
BUG=b:172020503, b:202863352
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I8313210c89559a6159f311821a18e7b310a3ada6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3224378
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
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clang warns that we're clobbering a reserved register:
inline asm clobber list contains reserved registers: R7
[-Werror,-Winline-asm].
According to
https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Clobbers-and-Scratch-Registers:
When the compiler selects which registers to use to represent input and
output operands, it does not use any of the clobbered registers.
Before this change, the only remaining registers for the compiler to use
to hold the values represented by the symbolic names "pregs" and
"pstack" are R0 and R12. After this change, this still holds on clang,
since it won't clobber the reserved register R7 even if it's not on the
clobber list.
BRANCH=none
BUG=b:172020503
TEST=make V=1 CC=arm-none-eabi-clang BOARD=elm
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I5182ef24f4465d68c97f4160a45cd479fe52e017
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193273
Reviewed-by: Keith Short <keithshort@chromium.org>
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Without this change, the code compiles and links when using clang, but
does not boot.
__data_lma_start should be the LMA address of the .data section and is
used in core/cortex-m/init.S to copy the data from the LMA address into
the VMA address (flash to RAM). Before this change, examining the smap
and map files shows that __data_lma_start (0x0800bcdc) does not match
the LMA address of the .data section (0x800bce0):
build/dartmonkey/RO/ec.RO.smap:
0800bcdc R __data_lma_start
build/dartmonkey/RO/ec.RO.map
VMA LMA Size Align Out In Symbol
24003538 800bce0 68 8 .data
After the change, the LMA addresses match and the board boots correctly:
build/dartmonkey/RO/ec.RO.smap:
0800bce0 A __data_lma_start
build/dartmonkey/RO/ec.RO.map
VMA LMA Size Align Out In Symbol
24003538 800bce0 68 8 .data
When comparing the behavior of this change with gcc, we find that many
boards match, but some do not (see TEST line). Looking at a few of the
boards that do not match, there appears to be a one-byte difference in
the RO portion. Investigating further on voxel:
Original address from build/voxel/RO/ec.RO.smap:
100a2e20 R __data_lma_start
New address from build/voxel/RO/ec.RO.smap after applying this change:
100a2e60 A __data_lma_start
In both cases, when using objdump on RO.elf, .data's LMA address starts
at 100a2e60, so this change appears to be correct:
arm-none-eabi-objdump -h
/tmp/compare_build.Ltgh/ec-53a576c00f1b0d609d23a68a83e0340a14ee8fe5/build/voxel/RO/ec.RO.elf
Sections:
Idx Name Size VMA LMA File off Algn
3 .data 00000538 200b8368 100a2e60 00058368 2**3
CONTENTS, ALLOC, LOAD, DATA
arm-none-eabi-objdump -h
/tmp/compare_build.Ltgh/ec-f0c36b07d9efa2f5b12e5de7e794d723e8468e26/build/voxel/RO/ec.RO.elf
Sections:
Idx Name Size VMA LMA File off Algn
5 .data 00000538 200b8368 100a2e60 00058368 2**3
CONTENTS, ALLOC, LOAD, DATA
BRANCH=none
BUG=b:172020503, b:202863352
TEST=make buildall
TEST=make CC=arm-none-eabi-clang BOARD=dartmonkey
TEST=./util/compare_build.sh -b all -j 150
All boards match, EXCEPT:
adlrvpp_npcx akemi aleena ambassador anahera atlas berknip bloog
bobba boldar brask brya bugzzy cappy2 careena casta chronicler
coachz collis copano coral corori dalboz delbin dewatt dirinboz dood
dooly dratini driblee drobit drobit_ecmodeentry eldrid elemi
endeavour eve ezkinil felwinter fizz fleex foob garg genesis gimble
grunt gumboz guybrush hatch helios herobrine_npcx9 homestar jinlon
kano karma kindred kingoftown kohaku lalala lazor liara lick lindar
lux madoo magolor marzipan meep metaknight moonbuggy morphius
mrbland mushu nami nautilus nightfury nipperkin nocturne npcx7_evb
npcx9_evb npcx_evb_arm npcx_evb nuwani palkia pazquel phaser pompom
poppy primus puff quackingstick rammus redrix reef sasuke scout
shuboz soraka stryke taeko treeya trembyle trogdor vilboz voema
volet volteer_npcx797fc voxel voxel_ecmodeentry voxel_npcx797fc
waddledoo2 woomax wormdingler yorp
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Icd3df244e202a50a577f21ffa4f8202eb3f8b8d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169964
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This change forces the LMA and VMA to start immediately after the .data
section; both LMA and VMA are forced to be equal. The change removes the
BYTE(0xFF), since lld will allocate space for this byte and throw off
the alignment.
The ASSERT line verifies that the __image_size is still correctly
aligned when building with both gcc and clang.
BRANCH=none
BUG=b:172020503
TEST=make buildall
TEST=make CC=arm-none-eabi-clang BOARD=dartmonkey
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I00d4e8f346232d1c5b8b04d397459760976a8a8b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169965
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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PANIC_DATA_PTR is defined as
((struct panic_data *)CONFIG_PANIC_DATA_BASE)
which is
CONFIG_RAM_BASE + CONFIG_RAM_SIZE - CONFIG_PANIC_DATA_SIZE
Instead of doing that calculation again, just re-use
PANIC_DATA_PTR, which more clearly shows the relationship between
pdata_ptr and pstack_addr. As indicated by the TEST line, this results
in no change to the generated code.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I52f769b388dd47269b74d70a651868fcd6c339b5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3213285
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The map file generated by lld has a different format than the gnu linker
(ld). (We save this map file into build/<board>/<image>/ec.<image>.map
during the build.)
Instead of trying to parse the different formats in the .map file, use
the .smap file (the output of "nm"), which has the values of the symbols
and has the same format whether using lld or ld. We need to add a new
"__flash_size" symbol so that we can use that symbol to get the size
from the .smap.
This add flash sizes to a few boards that previously didn't have it:
asurada_scp, cherry_scp, and kukui_scp, since the previous logic was
always looking for FLASH and these use IROM.
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
TEST=make CC=arm-none-eabi-clang BOARD=elemi
TEST=bcompare build_before_change build_after_change
=> only difference between space_free_flash.txt and
space_free_ram.txt files in the two builds is that this change adds
the space_free_flash.txt files for asurada_scp, cherry_scp, and
kukui_scp.
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I7c64b6ba9bceeeb4044559188c1c1bebbf60471d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179314
Reviewed-by: Keith Short <keithshort@chromium.org>
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See the description in commit c1cc2d919e9f21adc0f992dcac00f6e8b282616d.
These files copied the same logic.
BRANCH=none
BUG=b:172020503
TEST=make buildall
TEST=CC=arm-none-eabi-clang make BOARD=servo_micro
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I1d59b3a7eb6e71451313d70fe421880a08dad4b0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3183392
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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This function doesn't compile with clang:
core/minute-ia/include/fpu.h:207:10: error: unsupported inline asm:
input with type 'float' matching output with type 'uint16_t' (aka
'unsigned short')
: "0" (v));
^
Change the constraint "v" to match the __isinff function. According to
https://gcc.gnu.org/onlinedocs/gcc/Machine-Constraints.html#Machine-Constraints
"v" is "any EVEX encodable SSE register (%xmm0-%xmm31)"
As indicated by the TEST line, the output is identical before and after
this change.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 70
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ia6db458fe4894d65af173c1e7dae34f3d675a4bc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3194983
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
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CONFIG_RO_HEAD_ROOM and CONFIG_RW_HEAD_ROOM are always defined as 0, so
remove the values and associated code in order to simplify the code and
improve readability.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ie11d23befda674cc15dda9a2d66b9c43ea22d49e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3205489
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Assert that the RW image size padding adding results in correct
alignment. This assertion will make it easier to verify future clang
changes.
BRANCH=none
BUG=b:172020503, b:188117811
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ibdc6feaf31cf271f67594ae1e519272fd9a88cd4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179317
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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clang produces the following warning:
core/minute-ia/panic.c:119:19: error: variable 'eax' is uninitialized when used
here [-Werror,-Wuninitialized]
pdata->x86.eax = eax;
^~~
core/minute-ia/panic.c:109:23: note: initialize the variable 'eax' to silence
this warning
register uint32_t eax asm("eax");
When specifying registers for local variables they need to be specified as
constraints on an asm block:
https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables
In this case we simply use an empty asm block since we're just trying to
extract the values of the registers.
As indicated by the TEST line, the output is identical before and after
this change.
BRANCH=none
BUG=b:172020503
TEST=make CC=clang V=1 BOARD=arcada_ish
TEST=./util/compare_build.sh -b all -j 70
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I6fbd7061d9af734f02ec3dbb1329cdffac5e2a7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193276
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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.func and .endfunc were used to emit STABS debug information (not
DWARF). These only have an effect with -gstabs, which we're not using. I
suspect their inclusion was not intentional.
STABS is not supported when building with clang, so it generates the
following errors:
core/minute-ia/switch.S:27:1: error: unknown directive
.func __task_start
^
core/minute-ia/switch.S:42:1: error: unknown directive
.endfunc
See https://bugs.llvm.org/show_bug.cgi?id=20424 and
https://sourceware.org/gdb/current/onlinedocs/stabs.html.
As indicated by the TEST line, the output is indentical before and after
this change.
BRANCH=none
BUG=b:172020503
TEST=make CC=clang V=1 BOARD=arcada_ish
TEST=./util/compare_build.sh -b all -j 70
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I1e1e5f57fb382797e01dcf797d72de0468150054
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193271
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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clang warns when attribute declarations do not precede definitions:
error: attribute declaration must precede
definition [-Werror,-Wignored-attributes]
The cortex-m/irq_handler.h file uses the "__keep" attribute on
"routine". The declaration with the attribute must come before the
definition or the compiler will ignore it. This results in link errors
when using LTO with lld since it is optimized out. In order to fix this,
the DECLARE_IRQ instances must be moved before the function definitions.
However, if DECLARE_IRQ instances are moved without this change, we will
get an implicit declaration compiler error:
error: implicit declaration of function 'uart_interrupt'
This change does not change the resulting output as verified by the
"compare_builds.sh" script.
BRANCH=none
BUG=b:172020503
TEST=./util/compare_builds.sh -b all -j 70
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Icb282cb0f0a0557d6bc1d184378c5923d0e3a72d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182634
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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When compiling with clang, the following error is reported:
core/cortex-m0/switch.S:107:12: error: unknown token in expression
ldr r0, =#0xe000ed04 @ load 0xe000ed04's address
^
This change fixes the syntax, which generates the identical output
before and after the change:
/opt/coreboot-sdk/bin/arm-eabi-objdump -d
build/servo_micro/RW/core/cortex-m0/switch.o
0000006a <pendsv_handler>:
6a: b508 push {r3, lr}
6c: 4807 ldr r0, [pc, #28] ; (8c <pendsv_handler+0x22>)
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 70
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I379510f7aa00f61ae24ae8463c49d9cd3b832752
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3183391
Reviewed-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The vecttable logic explicitly routes unused IRQs to IRQ_UNUSED_OFFSET,
and then assigns it to "null" at the very end. The result is something
like:
[8] = __attribute__((used, weak, alias("default_handler")))
irq_55_handler(void);
[8] = __attribute__((used, weak, alias("default_handler")))
irq_56_handler(void);
...
[8] = (void*)0
This is intentional so that it works with a varying values for
CONFIG_IRQ_COUNT.
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I3ba4eeaa46cd2c50c65c922f4c0c463ce1bb585e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172038
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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If set, this option will prevent saving General Purpose Registers
during panic. When software panic occurs, R4 and R5 will be saved,
because they contain additional information about panic.
This should be enabled on boards which are processing sensitive data
and panic could cause the leak.
BUG=b:193408648
BRANCH=none
TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo'
to check what was saved. When CPU exception occurred registers
R0-R12 should be set to 0. In case of software panic, R4 and R5 can
contain panic reason and additional information.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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Switching task with disabled interrupts leads to Hard Fault on
Cortex-M0 because:
- SVCall exception have configurable priority (full list can be found
at 2.3.2 Exception types PM0215 p.23)
- We are using 'cpsid i' to disable interrupts. This instruction sets
PRIMASK bit (3.7.2 CPSID CPSIE PM0215 p.62)
- When PRIMASK bit is set, all exceptions with configurable priority
are disabled (PM0215 p.16), so SVCall is masked too
If Hard Fault is inevitable, it will be a good idea to catch this
earlier. It will save time spent debugging why Forced Hard Fault
happens. In functions responsible for enabling, disabling or making
task ready we postpone task switch when interrupts are disabled
BUG=b:190597666
BRANCH=none
TEST=Compile and flash EC on boards with Cortex-M0 and make
sure that it works properly.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: Id3be74e977ae5d5eed79aad78ee378fa413ed4ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953229
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Switching task with disabled interrupts leads to Forced Hard Fault on
Cortex-M3/M4/M7 because:
- SVCall exception have configurable priority (full list can be found
at 2.4.2 Exception types PM0253 Rev 5 p.40)
- We are using 'cpsid i' to disable interrupts. This instruction sets
PRIMASK bit (3.12.2 CPS PM0253 Rev 5 p.176)
- When PRIMASK bit is set, all exceptions with configurable priority
are disabled (PM0253 Rev 5 p.25), so SVCall is masked too
- SVCall is escalated to Forced Hard Fault because "A fault occurs
and the handler for that fault is not enabled" (PM0253 Rev 5 p.48)
If Hard Fault is inevitable, it will be a good idea to catch this
earlier. It will save time spent debugging why Forced Hard Fault
happens. In functions responsible for enabling, disabling or making
task ready we postpone task switch when interrupts are disabled
BUG=b:190597666
BRANCH=none
TEST=Compile and flash EC on boards with Cortex-M3/M4/M7 and make
sure that it works properly.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I50976154b0cf0307c5334f6f03e4b3bc137a4ffc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953228
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add a function that will provide information if interrupts are enabled.
This information will be used to fix shortcomings in common code for
UART buffering and usleep().
BUG=b:190597666
BRANCH=none
TEST=make -j buildall
TEST=make runhosttests
TEST=Note for running tests: this patch only adds function
implementation so, to test this it is necessary to add some code
which uses the function eg. console command which prints
information if interrupt is enabled.
Minute-ia core: It is necessary to compile firmware for
ISH (Intel Sensor Hub) which is available on drallion board
(eg. chromeos6-row1-rack9-host19). Firmware must be placed in
/lib/firmware/intel/drallion_ish.bin (partition must be writeable,
if not use /usr/share/vboot/bin/make_dev_ssd.sh on DUT tu unlock
it, don't forget about reboot). After copying firmware to
/lib/firmware/intel/ it is necessary to reboot DUT. After reboot
use `ectool --name=cros_ish version` to check if correct version
is running.
NDS32 core. This core is used in it8320dx chip which is present in
ampton (octopus family). EC can be compiled using
'make BOARD=ampton' and flashed using
'chromeos-firmwareupdate -e ec.bin', but EC software sync needs to
be disabled using 'set_gbb_flags.sh 0x200'
Riscv-rv32i core, hayato (asurada family) uses it81202 as EC which
is based on risc-v. EC can be compiled using 'make BOARD=hayato'
and flashed using 'chromeos-firmwareupdate -e ec.bin', but EC
software sync needs to be disabled using 'set_gbb_flags.sh 0x200'
Cortex-M, this is the most common core. Just compile EC for
platform which contains Cortex-M core (eg. bloonchipper) and test
if it works.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I502553cd57e6ce897d5845a3aad01a44a9058405
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953227
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add a "math.h" to "builtin" and rename "math.h" in the "core"
directories to "fpu.h". "builtin" is the directory containing headers
that mirror those in the standard library and is used for device builds.
The host builds exclude the "builtin" directory and use the standard
library. Without this change, building host tools such as "ectool" and
attempting to include "math.h" would result in incorrectly picking up
the "math.h" from the device "core" directory, not the standard library
version.
BRANCH=none
BUG=b:144959033
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Id6b2df42cb0ff5ec2cfc07aa8f29861da6804bdf
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130625
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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So compiler won't use these two registers to store any other value
in the function. This fixed software panic info isn't correct issue
when LTO is enabled.
BRANCH=asurada
BUG=b:179206540
TEST=Run "crash assert" on hayato, the software panic info is correct.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I4a94e7ea94ebc0bf4f056de58edb66c2962d669d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3113485
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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This reverts commit 1821e9423af84c7a126a4a15303c6492dd44e94b.
Reason for revert: This change broke the build.
BUG=b:195332627
TEST=None
BRANCH=None
Original change's description:
> make: Compile host tests in 32-bit mode
>
> Compile the host tests in 32-bit mode instead of 64-bit mode as it's
> more likely to match the actual environments our ECs run on. For
> instance, in 32-bit mode the tests might actually have a prayer of
> finding a torn read or write bug, whereas in 64-bit mode 64-bit integers
> are always operated on atomically.
>
> BUG=b:179062230
> BRANCH=none
> TEST=make -j runhosttests BOARD=host on x86_64 and i686
>
> Signed-off-by: Evan Green <evgreen@chromium.org>
> Change-Id: I02517066337ec08c311c1f7daae5d3de84b1f4c2
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059231
> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Bug: b:179062230
Change-Id: I35bcac77deeb1d031a31b32d911781f5fed4ab13
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3067826
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Reviewed-by: Allen Webb <allenwebb@google.com>
Tested-by: Evan Green <evgreen@chromium.org>
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Rather than starting the timestamp at 0 for each test, let's start it
just before the 32-bit rollover. This gives us more of a chance to catch
32-bit rollover issues in the tests.
BUG=b:179062230
BRANCH=none
TEST=make -j runhosttests BOARD=host
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ia0551b4409c4bc63938f319312f6c66acf7c6cd9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059233
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Compile the host tests in 32-bit mode instead of 64-bit mode as it's
more likely to match the actual environments our ECs run on. For
instance, in 32-bit mode the tests might actually have a prayer of
finding a torn read or write bug, whereas in 64-bit mode 64-bit integers
are always operated on atomically.
BUG=b:179062230
BRANCH=none
TEST=make -j runhosttests BOARD=host on x86_64 and i686
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I02517066337ec08c311c1f7daae5d3de84b1f4c2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059231
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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This CL makes the code more readable by adding comment / defines
regarding the meaning of PSP[5] and PSP[6].
BUG=None
TEST=make buildall
BRANCH=None
Change-Id: I0cbe7384e20f0287096624a00b0ec19c0fb7f9bd
Signed-off-by: Ricardo Quesada <ricardoq@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3059814
Tested-by: Ricardo Quesada <ricardoq@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Ricardo Quesada <ricardoq@chromium.org>
Auto-Submit: Ricardo Quesada <ricardoq@chromium.org>
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make the api consistent with other atomic methods
BUG=b:192422592
TEST=make
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I6cae4d521b44706cf7f44c669bf6964a08855b4c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058080
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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For CONFIG_FLASH_WRITE_SIZE > 4 (8 in the case of STM32L431
used in Munna), RW image size is not always 8-byte alignment which
leads to the failure from flash_range_ok and therefore
"EC sync update RW proecess" fails.
Here is the proposal of RW image size alignment with
CONFIG_FLASH_WRITE_SIZE.
1. Add output section .rw_image_size_alignment for padding
2. Expose new __image_size for hash afterward
3. Make output senction .rw_image_size_alignment
!CONFIG_CHIP_INIT_ROM_REGION guarded
BRANCH=main
BUG=b:188117811
TEST=make buildall + checking symbols (execpt __image_size) listed in
ec.R{O,R}.smap for all boards stay the same
Change-Id: Iaa3c91ded178455bde6baddbaf8abbd639d9e416
Signed-off-by: Ethan Huang <ethan.huang@stmicro.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999357
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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Affected boards (only STM32H7):
- nocturne_fp (dartmonkey)
- nucleo-h743zi
This fixes problem with jumping to RW when reboot to RO was requested.
Log from reproduction on dartmonkey (only relevant parts):
--- UART initialized after reboot ---
[Image: RO, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft ap-off]
...
[1.045743 Jumping to image RW]
*** We are in RW. Jump data are initialized and contains correct
*** set of reset flags. Reset flags from backup RAM are cleared.
reset flags from chip: unknown
reset flags from jump data: reset-pin power-on soft sysjump ap-off
[1.056198 UART initialized after sysjump]
[Image: RW, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft sysjump ap-off]
...
>
> reboot ro
reboot ro
Rebooting!
*** Now we are in RO. RW saved reset cause in backup RAM (with
*** stay-in-ro). Please note that RO also finds jump data and
*** report that was sysjump!
reset flags from chip: reset-pin power-on soft ap-off stay-in-ro
reset flags from jump data: reset-pin power-on soft sysjump ap-off
[1.056198 UART initialized after sysjump]
[Image: RO, dartmonkey_v2.0.8961+9a30ce07ee]
[Reset cause: reset-pin power-on soft sysjump ap-off]
When RO is doing sysjump to RW, jump data structure is created in
jump_to_image() function. The structure contains information about
reset flags. When RW finds jump data in system_common_pre_init() magic
field of the structure is set to zero to prevent detecting sysjump
accidentally. Nevertheless, when reboot to RO is requested, RO is able
to find the structure. As a result, correct reset flags from backup RAM
are overwritten by incorrect reset flags from jump data.
This happens because we are not flushing D-cache before reboot.
All changes in RW which lives in cache (not saved in RAM) will be lost
after reboot because cache is always disabled (even if it was
previously enabled and we didn't turned it off). To enable cache we need
to invalidate it first (see cpu_enable_caches()).
Issue reproduces also with debugger connected, except situation when
watchpoint is set on jump data magic field.
BUG=b:170432597 b:188934337
BRANCH=none
TEST=Compile dartmonkey firmware and run it on eg. icetower.
In RW, issue 'reboot ro'. Make sure that jump to RO is not
performed.
TEST=Run flash_write_protect hardware unit test on icetower board
using `./test/run_device_tests.py --board dartmonkey \
--tests flash_write_protect`
Make sure that after reboot to RO, 'stay-in-ro' reset cause is
printed
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145
Reviewed-by: Craig Hesling <hesling@chromium.org>
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