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* cleanup: Fix gcc 5.2.1 compile errorsShawn Nematbakhsh2015-11-112-2/+2
| | | | | | | | | | | | | | | BUG=chromium:552006 BRANCH=None TEST=`make buildall -j` and also verify panic reporting works on glados_pd. Change-Id: Ic9f1ec6b5297389df0d46bb38a67c156901ed956 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311253 Commit-Ready: Shawn N <shawnn@gmail.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: allocate signature headers in both RO and RW imagesVadim Bendebury2015-11-101-0/+3
| | | | | | | | | | | | | | | | With the proper RO in place, RW must be signed in the same manner, as RO. This patch makes sure that there is room in the RW header for the signature. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applies the RO successfully boots up the RW. Change-Id: I1538195e0181c23c874ddd300887cf5da8c5a867 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311421 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* system: Copy the loader lastly before jumping.Aseda Aboagye2015-11-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | The point at which we reloaded the loader was too early. When items are placed into .bss.slow via CONFIG_REPLACE_LOADER_WITH_BSS_SLOW, other tasks could still access their variables that may have been in that region after we had replaced those contents with the loader. This commit moves the reloading of the loader to as late as possible once all tasks have done their HOOK_SYSJUMP work. Also, fixed a bug with the .bss.slow section. If a board is not using the config option but items are placed in that section, that part of RAM would not be cleared out. BUG=chrome-os-partner:46056 BRANCH=None TEST=Enable config option on GLaDOS and add a few variables to the .bss.slow section. 'sysjump' between RO and RW and verify that no data bus error is encountered. TEST=make -j buildall tests Change-Id: I3084700b9d5c144e86e2e408b72d2e3075a67413 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/306173 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: modify hwtimer and LPC wake upDino Li2015-11-051-34/+7
| | | | | | | | | | | | | | | | | | | | | | | | | 1. In combinational mode and clock source is 8MHz, if timer 3 counter register always equals to 7, then timer 4 will be a 32-bit MHz free-running counter. 2. Fix TIMER_32P768K_CNT_TO_US(), each count should be 30.5175 us, not 32.768us. 3. Fix TIMER_CNT_8M_32P768K(). 4. Make sure LPC wake up interrupt is enabled before entering doze / deep doze mode. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Console commands: 'gettime', 'timerinfo', 'waitms', and 'forcetime'. 2. Enabled Hook debug, no warning message received (48hrs). 3. Tested ectool command 'version' x 2000. Change-Id: I796d985361d3c18bc5813c58705b41923e28c5b1 Reviewed-on: https://chromium-review.googlesource.com/310039 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nds32: fix interruptDino Li2015-11-012-0/+22
| | | | | | | | | | | | | | | | | | | | | | 1. To enable INT_PRI (hardware interrupt priority level 0~3) register, bit0@INT_CTRL = 0. 2. GIE need to be enabled before UART is initialized. [symptom] To define CONFIG_RWSIG / CONFIG_RSA / CONFIG_SHA256, then power on: after RW image is verified, firmware stuck in uart_flush_output(). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. bit0@INT_CTRL = 0. 2. The RW image is verified and jump to image RW. Change-Id: I393a3d5f87ea257885b872c91bfce43aecbaea8b Reviewed-on: https://chromium-review.googlesource.com/309400 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: Increase DLM sizeDino Li2015-10-251-0/+12
| | | | | | | | | | | | | | | | 1. Total DLM size is 48KB. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=DLM 0x84000 ~ 0x8BFFF read/write OK. Change-Id: I2340aeefca60ad59062254ddd363c703c30cfd24 Reviewed-on: https://chromium-review.googlesource.com/307006 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix clock moduleDino Li2015-10-251-5/+40
| | | | | | | | | | | | | | | | | | | | 1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=test the following items in deep doze mode. 1. WUI interrupts wake-up OK. (For example, power button, lid, uart rx, keyboard ksi, and so on) 2. LPC access interrupt wake-up OK. 3. Enabled Hook debug, no warning message received (48hrs). Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4 Reviewed-on: https://chromium-review.googlesource.com/307060 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add support to reclaim space from loader.Aseda Aboagye2015-10-131-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain ECs which cannot load both the RO and RW images into memory simultaneously have a little firmware (LFW) loader that is loaded into the beginning of the program memory. This loader is responsible for loading the RO/RW images, however once we begin executing code from main(), the loader has already completed it's purpose. We can reuse this space by allocating portions of the .bss section here. This currently saves us 3k for mec1322. This section is .bss.slow. To use this feature simply define the following config option in board.h. #define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW In some cases, such as the mec1322, this region of RAM is optimized for code and not data. Therefore, ideally infrequently used data should go into this region. BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro; Verify we are back in ro. TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow section. TEST=make -j buildall tests Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305254 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add magnetometer online calibration.Gwendal Grignou2015-10-131-0/+11
| | | | | | | | | | | | | | | | Code for hard iron calibration: Every seconds (or faster if enough samples), find a sphere that fit the compass data. Based on Android code. BRANCH=smaug BUG=chrome-os-partner:39900 TEST=Check hard-iron bias is removed. Works better outside. Change-Id: Iab479d5113b6560b4f01b0fd87373d2eecdb9b54 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299583 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* nds32: fix panicDino Li2015-10-073-5/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support saving panic data for nds32 core. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console commands 'crash' and 'panicinfo'. 2. ectool command 'panicinfo' crash assert ASSERTION FAILURE '0' in command_crash() at common/panic_output.c:162 === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 > crash divzero === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access > crash stack +1+2+3+4+5+6+7+8+9+10+11+12+13+14+15+16+17 Stack overflow in CONSOLE task! === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 > crash watchdog Pre-watchdog warning! IPC: 00009c6c panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=0 === R0 00000000 R1 00000000 R2 00000000 R3 00000000 R4 00000000 R5 00000000 R6 dead6664 R7 00000000 R8 00000000 R9 00000000 R10 00000000 R15 00000000 FP 00000000 GP 00000000 LP 00000000 SP 00000000 IPC 00009c6c IPSW 00000 SWID of ITYPE: 0 Software panic reason PANIC_SW_WATCHDOG Software panic info 0x0 > Change-Id: I3d491ecd0789335db4633f9bf2ca09cf85503ed9 Reviewed-on: https://chromium-review.googlesource.com/303286 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix hw timer and related function.Dino Li2015-10-014-2/+141
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [chip config] 1. No hardware specific udelay(). 2. Enable watchdog. [watchdog] 3. Watchdog period is "CONFIG_WATCHDOG_PERIOD_MS" of config.h. 4. Watchdog auxiliary timer period is "CONFIG_AUX_TIMER_PERIOD_MS". [task and irq] 5. Write 1 to clear interrupt pending status, no |. 6. A global variable for store interrupt number of software interrupt. [uart] 7. Always reset UART module before config it. [hwtimer] 8. Use more external timers for HW timer module. [task] 9. Fix task profiling. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=[watchdog] 1. console "waitms 1100", only pre-watchdog warning message. 2. console "waitms 1600", warning message and watchdog reset. [hwtimer] 3. console commands "gettime", "timerinfo", and "forcetime". 4. enable hook debug and there is no delayed by more than 10% warning message over 48 hours. 5. There is no watchdog reset too. [task] 6. console 'taskinfo' Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000000 32.927724 308/512 1 HOOKS 00000000 0.034267 372/768 2 R CONSOLE 00000000 0.116763 468/768 3 HOSTCMD 00000000 0.000641 372/512 4 KEYPROTO 00000000 0.000042 212/512 5 KEYSCAN 00000000 0.000908 356/512 IRQ counts by type: 38 2932 155 1 158 261 160 67 Service calls: 87 Total exceptions: 3348 Task switches: 167 Task switching started: 0.001999 s Time in tasks: 33.282819 s Time in exceptions: 0.164717 s Change-Id: I234085cec231cd855d2a5e639ea1b0966c61d796 Reviewed-on: https://chromium-review.googlesource.com/296939 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Handle signed RW images a bit cleanerBill Richardson2015-09-252-49/+16
| | | | | | | | | | | | | | | | | | | | | | | | | For signed EC RW images (CONFIG_RWSIG), there's no point in embedding the public key or signature into the image itself since it will just be replaced by the signer (either as the next step in the build process, or after the fact for MP releases). This takes that out and just points to where the pubkey and signature will be placed. BUG=none BRANCH=none TEST=make buildall I also checked the signatures with futility show -t build/*/ec.bin They still look good, and the one signed image I booted (Cr50) works as before. Change-Id: Ib39b7c508914851f81a1bebb2450e08ef0def76c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302630 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CONFIG_FW_IMAGE_SIZEShawn Nematbakhsh2015-09-241-1/+1
| | | | | | | | | | | | | | | | | | Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may theoretically be different sizes), it is no longer useful to globally define the size of an image. BUG=chromium:535027 BRANCH=None TEST=`make buildall -j`. Also, verify glados / glados_pd continue to function as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8 Reviewed-on: https://chromium-review.googlesource.com/301743 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Fix typo when building with CONFIG_SHAREDLIBBill Richardson2015-09-232-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board-specific board.h defines things like this: #define CONFIG_RO_SIZE 1000 #define CONFIG_RW_SIZE 1000 #define CONFIG_SHAREDLIB_SIZE 200 And in the linker scripts we define some preprocessor macros like so: #define FW_SIZE_(section) CONFIG_##section##_SIZE #define FW_SIZE(section) FW_SIZE_(section) So that we can say things like this: FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION) Note that we have to use FW_SIZE, not FW_SIZE_ The difference is only noticeable when SECTION is #defined. If ${CFLAGS} has -DSECTION=RW Then the expansion is this: FW_SIZE_(SECTION) => CONFIG_SECTION_SIZE FW_SIZE_(RW) => 1000 There's no difference in the output for this particular CL, but we should use the correct macro anyway to avoid confusion. BUG=none BRANCH=none TEST=make buildall Change-Id: I61edc76a1aaeb1c675b384371700f37dda39ed47 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302150 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* nuc: Fixed flash layout issue for npcxMulin Chao2015-09-211-1/+5
| | | | | | | | | | | | | | | | | | | | Fixed flash layout issue for npcx Modified drivers: 1. config_flash_layout.h: Fixed layout issue for npcx 2. flash_ec: add flashrom support for boards without JTAG in servo connector BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0b9b679c52b8a8e2a26c278b5024d0350fb77338 Reviewed-on: https://chromium-review.googlesource.com/300392 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add __fls functionGwendal Grignou2015-09-213-9/+9
| | | | | | | | | | | | | | | Returns the most significant bit set. Replace 31 - __builtin_clz(x), so x must be different from 0. Use get_next_bit when not on the performance path, on performance path set the bit field just after reading it. BRANCH=smaug BUG=none TEST=compile, check Ryu still works. Change-Id: Ie1a4cda4188f45b4bf92d0549d5c8fb401a30e5d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301300
* it8380dev: fix idle task and chip idDino Li2015-09-181-1/+23
| | | | | | | | | | | | | | | | | | | | | 1. Fix system_get_chip_name() and system_get_chip_revision(). 2. Fix EC doze mode. 3. Enable LPC cycle wake-up EC from doze / deep doze function. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console "version". Chip: ite it8390 cx 2. EC doze mode is normally. 3. ectool "version" command x 2000. Change-Id: I167dbfb965e557eb86ed83f45a945e4315f5fa9f Reviewed-on: https://chromium-review.googlesource.com/299110 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* host: mock i2c_xferGwendal Grignou2015-09-161-27/+3
| | | | | | | | | | | | | | | Instead of mocking i2c_read8/16/32, mock i2c_xfer. We can now test code that call i2c_xfer directly and test common/i2c.c BRANCH=samus, ryu BUG=chrome-os-partner:45223 TEST=Unit tests pass. Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299768 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-13/+6
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-163-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cleanup: Remove COMPILE_FOR_RAM option from linker scriptsBill Richardson2015-09-085-45/+3
| | | | | | | | | | | | | | | This option was added way back in January 2012 for early EC bringup, and never used since. We can probably remove it. BUG=none BRANCH=none TEST=make buildall Change-Id: Idc8c3099388f2e28d620848a0e78b555b02fba9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297334 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* UART: Remove unused uart.h header includesAnton Staaf2015-09-088-8/+0
| | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ife068807f79f6435292643c49afa1a9a30ae7080 Reviewed-on: https://chromium-review.googlesource.com/296733 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cortex-m: CONFIG_RO_HEAD_ROOM should only affect RO imageBill Richardson2015-08-311-1/+1
| | | | | | | | | | | | | | | | When we add head room to the RO image, it's generally to provide a chip-specific boot header of some sort. That header is only needed for the RO image, not the RW image. The macro name implies this, but this CL makes it so. BRANCH=none BUG=chrome-os-partner:43025, chrome-os-partner:44625 TEST=the cr50 image validates *and jumps to* the RW image at boot. Change-Id: I0e5b2c32e232418970e01c7409ddcbbabd4786d5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296451 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cortex-m: provide ability to insert free space into RO image baseVadim Bendebury2015-08-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | Some platforms might expect the header of the image to be a certain platform specific blob. This patch adds an ability to insert an arbitrary size header in the binary blob, if so desired, the intention is to have the platform specific tools to postprocess the image and replace the header with sensible data. Ideally we should be able to produce an image which is mapped to start at an offset to the FLASH_BASE, but the macros in ec.S.lds files are way too smart for this. BRANCH=none BUG=chrome-os-partner:43025 TEST=with this and other changes the latest cr50 image gets signed and booted properly. Change-Id: Icabf00c6b90657b0ae3370ddad3567ccedf3ff49 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295200 Reviewed-by: Shawn N <shawnn@chromium.org>
* nds32: use INT_MASK instead of GIEDino Li2015-08-203-34/+66
| | | | | | | | | | | | | | | | | | | | | | | | | When there is an interrupt event, N8 CPU will save PSW register to IPSW register and clear GIE then jump to interrupt service routine. N8 will restore PSW from IPSW after "iret" instruction (the above are purely hardware mechanism). Nested interrupt will occur if we set GIE again in interrupt context. symptom: power button pressed while LID open -> exception or unknown reset. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Manually pressed power button x200. 2. Console "eflash" erase and write eflash OK. Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f Reviewed-on: https://chromium-review.googlesource.com/289437 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add __muldi3.SDino Li2015-08-142-1/+41
| | | | | | | | | | | | | | | | | | | | symptom: Enable debugging and profiling statistics for hook functions (#define CONFIG_HOOK_DEBUG), and __muldi3 function is missing while link. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. compile successful and hook_notify starting to print message. 2. console "hookstats" Change-Id: Ia2815bcefd0f9ac06dab9c75ea6ee06312878ca2 Reviewed-on: https://chromium-review.googlesource.com/293432 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* cortex-m0: Constrain target register in atomic readAnton Staaf2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | One more register constaint needed to be added to the cortex-m0 atomic inline assembly. Vincent fixed all the others. The requirement for ARMv6-m includes that the target load register be one of the low registers as well. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie44e824cafcc9b862ade664e3016cc34886cdf6e Reviewed-on: https://chromium-review.googlesource.com/292435 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* cortex-m: catch misconfigured interrupts earlyVadim Bendebury2015-08-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | The code in core/cortex-m/init.S limits the number of installed vectors to CONFIG_IRQ_COUNT. But the DECLARE_IRQ macro installing interrupt servicing routines does not care about this limitation. This results in corrupted interrupt configuration, which is hard to debug. This patch makes sure that there is a compilation error in case DECLARE_IRQ is passed interrupt number which out of bounds. A similar change needs to be introduced for cortex-m0. BRANCH=none BUG=chromium:518898 TEST=tried building cr50 with one of interrupt numbers exceeding CONFIG_IRQ_COUNT, observed a compilation error. Change-Id: Ie7bc623da6bf7371579b2242064f81a83053df17 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/291843 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Atomic: Mark the modified uint32_t volatileAnton Staaf2015-07-274-20/+20
| | | | | | | | | | | | | | | | | | | | | | The atomic_* functions are often used in contexts where the data they will operate on are volatile (due to being shared between tasks or a task and an interrupt handler). Adding volatile here makes using the atomic_* functions a little easier in those cases and removes a cast from the call sites (which could be obscuring a bug, if for instance the variable was modified to be a uint16_t). Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e Reviewed-on: https://chromium-review.googlesource.com/287516 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* nuc:Ian Chao2015-07-251-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* mec1322: heavysleep in idle task and console deepsleepKyoung Kim2015-07-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented mec1322's heavysleep in idle task to reduce further EC power down on S3. MEC1322 needs sleep-enabled for all blocks to acheive max power down including UART. Real heavysleep will be effective only when console/uart is not active. To enable this commit, board-specific commit is required. For example, check commit, "Enabling heavysleep idle task at S3". Test: 1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux shell. 2. wait at least 1 min till EC console sleeps 3. measure EC power. Since idle task is continuously scheduled, EC will enters/exits to/from heavy sleep mode frequently in S3 and power consumption will be changed dynamically. For acurate power measurement, high-sampling-rate measurement system might be required and using DMM might not give accurate number. BUG=None TEST=Tested on evt1p0/evt1p7/DVT BRANCH=None Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283603 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* build-infr: Add support for shared RO library.Aseda Aboagye2015-07-172-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the build infrastructure changes needed for creating a shared RO library. (libsharedobjs). The end goal is for the library to contain various objects that can be shared with both the RO and RW EC images. Now, there are 3 make goals: ro, rw, and libsharedobjs. In order for changes that are only specific to a single image (ie: RW only) to be applied correctly, the object files are now built separately for the RO, RW, shared objects library targets. NOTE: Certain EC targets are incompatible with this model due to the fact that only one image is present within flash at a time. BRANCH=none BUG=None TEST=make -j buildall tests TEST=make -j BOARD=cr50 xrefs TEST=make BOARD=samus dis TEST=Built samus EC image and compared that the final EC image was identical to the upstream version (except for the git SHAs & version strings). CQ-DEPEND=CL:285934 Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/274079 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* emulator: Fix handling of early IRQs.Aseda Aboagye2015-07-173-4/+26
| | | | | | | | | | | | | | | | | | | | Since the interrupt generator is now spawned right after the hooks task and the generator can generate interrupts whenever it wants, it's possible for an interrupt to fire before task switching is enabled. When this happens, the main thread needs to be suspended so that the IRQ can be serviced. BRANCH=None BUG=None TEST="make clobber && make -j buildall tests" several times." Change-Id: I5fb4f17666e3db9c670c4352bb36b84e4606dfa0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/285634 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* hooks: Move HOOK_INIT to after task switching.Aseda Aboagye2015-07-135-22/+102
| | | | | | | | | | | | | | | | | | | | | | | | This commit changes the way in which tasks are started. Instead of having all tasks marked as ready to run upon initialization, only the hooks task is marked as ready to run. HOOK_INITs are now run at the beginning of the hooks task. After the HOOK_INITs, the hooks task calls back to enable the rest of the tasks, reschedules, and proceeds as usual. This also allows the removal of checks for task_start_called(). BUG=chrome-os-partner:27226 BRANCH=None TEST=Built and flash EC image for samus and verified that EC boot was successful as well as AP boot. Additionally, verified that charging, keyboard, tap-for-battery were all still functional. TEST=make -j buildall tests Change-Id: Iea53670222c803c2985e9c86c96974386888a4fe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/283657 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* it8380dev: add flash module and fix system jumpDino Li2015-07-082-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add flash control module for emulation board. 2. Fix system jump for Andes core. 3. Change the physical size of the flash on the chip to 256KB. note: 1. Only IT839x series supports flash write protect by registers. 2. Static DMA method of flash code only for IT839x series and IT838x Dx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command flashwp and flashinfo 1-a. flashwp enable 1-b. WP asserted and reboot 1-c. flashinfo RO protected now 1-d. WP deasserted and reboot 1-e. No protected 1-f. flashwp disable 1-g. WP asserted and reboot 1-h. No protected 2. console sysjump and sysinfo 2-a. sysjump rw 2-b. jumping to image RW 2-c. sysinfo, Copy : RW, Jumped : yes 2-d. sysjump ro 2-e. jumping to image RO 2-f. sysinfo, Copy : RO, Jumped : yes 3. RO/RW firmware image test 3-a. sysjump rw 3-b. use console command "eflash" to erase RO region, erase OK and system still work. 3-c. reflash firmware 3-d. sysjump rw, sysjump ro 3-e. use console command "eflash" to erase RW region, erase OK and system still work. Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8 Reviewed-on: https://chromium-review.googlesource.com/271390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* nds32: remove macro "RO"Dino Li2015-07-011-13/+0
| | | | | | | | | | | | | | | | | | | "RO" is a workaround for GP base instructions. And now we have added "-mno-gp-direct" option in the NDS32 toolchain. So the compiler would not generate GP base instructions directly, and we can remove this "RO". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:24378 TEST=console "version" and "gpioget" Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/281862 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* cleanup: fix all the header guardsBill Richardson2015-06-1813-39/+39
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: add pmc control moduleDino Li2015-06-172-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pmc(LPC ACPI) control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. 62h/66h port. 1-a. out 66h 80h, out 62h 00h, in 62h 02h 1-b. out 66h 81h, out 62h 01h, out 62h 55h 1-c. out 66h 80h, out 62h 01h, in 62h 55h 1-d. out 66h 80h, out 62h 02h, in 62h aah 2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF and host read only. 3. 80h port, console command port80. 4. host command. 4-a. host request (LPC I/O 800h ~ 807h) 03 FD 00 00, 00 00 00 00 out 204h DAh, in 200h 00h host response (LPC I/O 800h ~ 80Bh) 03 F7 00 00, 04 00 00 00, 02 00 00 00 4-b. host request 03 EE 01 00, 00 00 04 00, 01 02 03 04 out 204h DAh, in 200h 00h host response 03 E5 00 00, 04 00 00 00, 05 05 05 05 Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e Reviewed-on: https://chromium-review.googlesource.com/269271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* common: Add i2c 32bit read/writeGwendal Grignou2015-06-171-0/+8
| | | | | | | | | | | | | Add functions and associated test to read/write a 32 bit register BRANCH=smaug TEST=Test on smaug with bm160 driver BUG=chromium:39900 Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* coderam: Don't assume that RO/RW images reside at start of code memoryShawn Nematbakhsh2015-06-131-6/+17
| | | | | | | | | | | | | | | | | | RO/RW images may reside at an offset to the start of code memory, defined at the chip-level by CONFIG_R*_MEM_OFF. BUG=chrome-os-partner:38103 TEST=Manual on Cyan. Verify sysjump works correctly in both directions. BRANCH=None Change-Id: I54c5f20335a5646d49afcc8d3fa2eb90ca9349d0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274434 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com>
* core: Assert if task_get_current() cannot return a valid task IDShawn Nematbakhsh2015-06-123-0/+12
| | | | | | | | | | | | | | | | | | | If task_get_current() is called early during initialization when we have not yet done a context switch, our current_task pointer is invalid. Add an assert to detect this case and put it behind CONFIG_DEBUG_BRINGUP, a new config that's intended to enable possibly-costly pre-production debugging. BUG=chrome-os-partner:40677 TEST=Manual on glados. Define CONFIG_DEBUG_BRINGUP, then call i2c_write from board_init and verify the new assert fails. Remove the i2c_write and verify the new assert passes. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6014ccf739dcc4c8f4f960be2b89f01e423b65b5 Reviewed-on: https://chromium-review.googlesource.com/273541 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* core: add task_wait_event_mask() function to other coresAlec Berg2015-06-113-2/+57
| | | | | | | | | | | | | | | Add task_wait_event_mask() function to core/cortex-m0, core/host and board/zinger/runtime in order to delay a task until a specific event occurs. BUG=none BRANCH=smaug TEST=make -j buildall Change-Id: Ic89487fcae5352eec53b745179c7f0d5893ad3e0 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/276744 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: USB hardware uses 8-bit buffers, not 16-bitBill Richardson2015-05-292-4/+4
| | | | | | | | | | | | | | | Our USB buffers are just arrays of uint8_t in program RAM, so let's treat them that way. The DMA descriptors are in normal RAM, too. BUG=chrome-os-partner:40693 BRANCH=none TEST=make buildall Change-Id: Ibafe1a557a328bbf8cf37ce113675fcd35bad376 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273918 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-199-10/+21
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-123-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* flash: Add option to move pstate inside RO imageRandall Spangler2015-04-172-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, ECs with internal flash store the write protect state for RO in a separate write/erase block of flash. This is wasteful on chips where there are not many blocks of flash. Add a new CONFIG_FLASH_PSTATE_IN_BANK option which is defined by default. This is the old behavior, for compatibility. (And we're calling it 'bank' because that's what the existing code does, even if the terminology is somewhat etymologically... bankrupt.) If that config is #undef'd, then store the write protect flag directly inside the RO image. This uses only 4 bytes of the RO image, instead of an entire erase block. The magic numbers for the pstate values are chosen such that when protecting RO, bits are only transitioned away from their erased state. Unprotecting RO once it's protected requires reflashing RO; it's no longer possible to 'flashwp disable'. But that's ok, because realistically, the only reason to unprotect RO is if you're about to flash the RO firmware anyway. BUG=chromium:476659 BRANCH=none TEST=Without undefining CONFIG_FLASH_PSTATE_IN_BANK, make sure everything still works on samus and samus_pd. This ensures we didn't break the existing functionality: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable flashinfo -> no flags Then recompile with #undef CONFIG_FLASH_PSTATE_IN_BANK and test: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable -> fails with access denied flashinfo -> ro_at_boot Then reflash to verify that clears the ro_at_boot flag: flashinfo -> no flags Change-Id: Ie794b8cfed2a10c50b0e36dcf185884070b04666 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266095 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* usb: Remove unnecessary alignment for descriptorsBill Richardson2015-04-151-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was causing the amount of data sent to be larger than the total size of the descriptors. Before this CL, connecting the Cr50 through USB gave this kernel message: usb 2-1.4.7: config 1 descriptor has 1 excess byte, ignoring When the host requests the descriptor, the code in chip/*/usb.c that handles it looks like this: case USB_DT_CONFIGURATION: /* Setup : Get configuration desc */ desc = __usb_desc; len = USB_DESC_SIZE; break; But include/usb.h has this: #define USB_DESC_SIZE (__usb_desc_end - __usb_desc) And both __usb_desc and __usb_desc_end come from the linker script. BUG=none BRANCH=none TEST=manual Before this change, I built the Cr50 firmware from m/master, tried it, and got the dmesg complaint on the host. After this change, the dmesg complaint doesn't show up anymore. Change-Id: I83ae2333a9e76af7acb18bd2f0e4cef5c095862a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/265765 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it8380dev: add KBC/KMSC moduleDino Li2015-03-221-0/+6
| | | | | | | | | | | | | | | | | 1. DLM 16KB. 2. Add KBC/KMSC module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + x86 MB can boot into DOS and keyboard works. Change-Id: Ia5cc2d4f1733ce07879d410b0447b2d48e50cd95 Reviewed-on: https://chromium-review.googlesource.com/259923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* lm4: stm32: Store panic data in backup registers on hard resetShawn Nematbakhsh2015-03-144-10/+52
| | | | | | | | | | | | | | | | | | On hard reset / hibernate, RAM will be erased and panic data will normally be lost. When software panic data saving is enabled, try to save this data just before hard reset and restore it when we come back up. BUG=chrome-os-partner:37380 TEST=Manual on Samus with WP + SW sync enabled. Boot AP, then run "crash divzero" on console. After hard reset, verify that "panicinfo" dumps data and shows divzero exception code. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9516dd4b6db12ef35e512cc4710f9b97d7e663cb Reviewed-on: https://chromium-review.googlesource.com/255912 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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