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* ISH: Fix FPU flagKyoung Kim2018-11-151-1/+1
| | | | | | | | | | | | | | | | | Fix bug in following CL. https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1154187 BUG=b:118628615 TEST=check if FPU-utilzing tasks can operate properly. Change-Id: Id7f6a5f7827a9ffc81684b7f91705b4c72f03eab Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1304893 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* ish gpio: added GPIO interrupt to IOAPICli feng2018-11-131-0/+1
| | | | | | | | | | | | | | BUG=b:116451255 BRANCH=none TEST=none Change-Id: I3d6883554393c1733a902eff8ea3680ec9de33e1 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/884604 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* core/host: Fix __prog_name and make task struct const.Allen Webb2018-11-092-3/+3
| | | | | | | | | | | | | | | | This fixes the error: "addr2line: 'ec-fuzz': No such file" when executing a fuzzing target within the $PWD. Note that a similar error will still appear when executing from another path. BRANCH=None BUG=None TEST=make -j buildfuzztests Change-Id: Id0257e05a937374c3340c7b276ca7dea1981704a Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1325169 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/minute-ia: Add FLASH memory configurationPatrick Georgi2018-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | Even though it's not flash (and therefore rwx), the section layout indicates these parameters. Add them as Memory Configuration to meet the expectations of the "bytes free" report. BUG=none BRANCH=none TEST=no more atlas_ish board with -63k bytes free in flash after make buildall Change-Id: Ic476496d66bfc9c4e69a808542c778379d76c4b5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1318229 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nds32: Add 64-bit divide library routines for N8 CPUDino Li2018-10-313-0/+388
| | | | | | | | | | | | | | | | | Taken from NDS32 CPU's library routines. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=b:115501243 TEST=Add a debug console command to see if 64-bit division works as expected. Change-Id: I3ba47a24a1bb60fd7fb57321b177e603a0e7712b Reviewed-on: https://chromium-review.googlesource.com/1296430 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* atlas_ish: implement __shared_mem_bufCaveh Jalali2018-10-261-0/+11
| | | | | | | | | | | | | | | | | | | | when building the atlas_ish using emerge, additional components are built that we weren't building previously. in particular test/utils was falling over due to a missing symbol. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches, emerge-${BOARD} chromeos-base/chromeos-ec succeeds at building atlas_ish Change-Id: Icf588afae8ed5410e21db733a9132bbc23ed2310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1297042 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* ISH: add FPU context save/restoreKyoung Kim2018-10-251-1/+10
| | | | | | | | | | | | | | | | | | Add FPU context save for current task and restore for next scheduled task. BUG=none TEST=check if FPU-utilizing tasks can resume without FPU operation issues. Change-Id: Id3c5ff1c9a6b3702a27b8ffc5f6a825877671ce4 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1154187 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* core/minute-ia: default to coreboot toolchainCaveh Jalali2018-10-251-1/+2
| | | | | | | | | | | | | | | | | | this sets the default toolchain for minute-ia to be the coreboot toolchain. BUG=b:118355015 BRANCH=none TEST=built using make from platform/ec, verified coreboot toolchain is used. Change-Id: I4078be8c1fafeee1e64c2ed008bb9f946f637077 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1297041 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* core/minute-ia: update linker script for coreboot toolchainCaveh Jalali2018-10-251-5/+7
| | | | | | | | | | | | | | | | | | when using the coreboot toolchain, only C-line commends are allowed in linker scripts, so just fix the syntax. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: I75094909d92eefade6d1756a06094dd537c5ce09 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1297040 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* core/minute-ia: fix code for coreboot toolchainCaveh Jalali2018-10-252-9/+2
| | | | | | | | | | | | | | | | | this fixes some compilation issues when using the coreboot toolchain. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: Id93822fa0a8112da45529b0ba4ab327b773a31d7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1297039 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* core/minute-ia: clean up atomicsCaveh Jalali2018-10-253-82/+65
| | | | | | | | | | | | | | | | | | | | | this cleans up the definitions in atomic.h. the coreboot toolchain wasn't very happy with the original declarations and definitions, and sure enough inline global functions don't make a lot of sense. so, i'm just going to apply the same definition style used for other architectuers here. BUG=b:118355015 BRANCH=none TEST=tested in combination of a bunch of other patches to get atlas_ish to build with the coreboot toolchain Change-Id: I654d1dd059b07484f724727d8546d8e7665d1b6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1297038 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* core/minute-ia/panic: noreturn function should not returnli feng2018-10-241-0/+3
| | | | | | | | | | | | | BUG=b:118296923 BRANCH=none TEST=build atlas_ish which use minute-ia and pass Change-Id: I7bd5ea67008e2f82c19390cee2d3a219bf376a30 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1287150 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* chip/g: Convert usb_endpoints to C so gcc's LTO knows about itPatrick Georgi2018-10-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | If we keep it assembly-only, the link time optimizer gets confused and eliminates seemingly unused functions, to then replace references to them with the "no handler" defaults in a later step. Similar approach as with vecttable: Implement the table in C so LTO knows the entire story. BUG=b:65441143 BRANCH=none TEST=usb_ep_{rx,tx,reset} and usb_iface_request look more reasonable in disassembly on cr50. Change-Id: I72103af742164c29aac38e9929d1a83d8c154b53 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177711 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* chip/stm32: Convert usb_endpoints to C so gcc's LTO knows about itPatrick Georgi2018-10-161-0/+4
| | | | | | | | | | | | | | | | | | | | | | If we keep it assembly-only, the link time optimizer gets confused and eliminates seemingly unused functions, to then replace references to them with the "no handler" defaults in a later step. Similar approach as with vecttable: Implement the table in C so LTO knows the entire story. BUG=b:65441143 BRANCH=none TEST=usb_ep_{rx,tx,event} and usb_iface_request look more reasonable in disassembly on whiskers. Change-Id: I35ccfd68cda2d0022aa464ecf622f4eef71c3398 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177710 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* cortex-m0: Generate vector table in CPatrick Georgi2018-10-169-69/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different versions of the linker behave differently when mixing object built with lto enabled (desirable for code size reduction) and disabled (assembler code), especially when they refer to each other symbols: The file evaluation order of the linker becomes important as it eliminates dead code at various points in time, and LTO code referring to non-LTO code or vice versa, is not visible at early runs. Sadly, just changing the order on the command line isn't sufficient: What works for gcc8 breaks gcc6 (and may behave different in even more ways on gcc4 or other versions). Therefore, implement the vector table in C, so it's compiled in LTO mode, just like the code it refers to. This is a port of Change-Id: I9b75f6558f0357e18000ff1161096c8f9c94a8ac BUG=b:65441143 BRANCH=none TEST=with this change the vector table for whiskers looks much more reasonable (ie. not mostly empty) Change-Id: Ifd39289ecb16b81cdf41427ce190984510d3fd3c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1120333 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1177382 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* aes-gcm: Adapt AES-GCM to build for ECNicolas Boichat2018-09-211-0/+1
| | | | | | | | | | | | | | | | | | | | | Update header, C code, trim unnecessary bits. Also add a test with vectors taken from BoringSSL tests. BRANCH=none BUG=b:111160949 TEST=make run-aes -j TEST=make BOARD=nocturne_fp test-aes -j flash_fp_mcu aes.bin runtest => pass (C implementation speed: 909555 us for 1000 iterations) (ASM implementation speed: 596690 us for 1000 iterations) Change-Id: Ief54a8441d26ba44de4c3ac81e203cab7472269f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1141446 Commit-Ready: Nicolas Norvez <norvez@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* aes-gcm: Baseline implementation from BoringSSLNicolas Boichat2018-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | Copied over from upstream BoringSSL at commit 859679518d3433cdd0dd6cf534bd7bdb2a32dd60 . cp boringssl/crypto/fipsmodule/modes/gcm.c \ third_party/boringssl/common/gcm.c cp crypto/fipsmodule/modes/internal.h \ third_party/boringssl/include/aes-gcm.h => Remove non-GCM definitions perl boringssl/crypto/fipsmodule/modes/asm/ghash-armv4.pl \ > third_party/boringssl/core/cortex-m/ghash.S BRANCH=none BUG=b:111160949 TEST=none Change-Id: I34702ff315c8c44e6f4868243058700aaf026099 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1141445 Reviewed-by: Adam Langley <agl@chromium.org>
* aes: Adapt AES code to build for ECNicolas Boichat2018-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update header, C code, and tweak the assembly for ARMv7-M. Rename aes_now_* functions to AES_* to avoid the need for a separate wrapper. Also add a test with FIPS-197 test vectors, and speed test. BRANCH=none BUG=b:111160949 TEST=make run-aes -j TEST=make BOARD=nocturne_fp test-aes -j flash_fp_mcu aes.bin runtest => pass (C implementation speed: 11977 us for 1000 iterations) (ASM implementation speed: 5815 us for 1000 iterations) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I2048aae73decccb893bc1724b2617b0b902dd992 Reviewed-on: https://chromium-review.googlesource.com/1120340 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Adam Langley <agl@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* aes: Baseline implementation from BoringSSLNicolas Boichat2018-09-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Copied over from upstream BoringSSL at commit 859679518d3433cdd0dd6cf534bd7bdb2a32dd60 . cp boringssl/LICENSE third_party/boringssl/LICENSE cp boringssl/src/crypto/fipsmodule/aes/aes.c \ third_party/boringssl/common/aes.c cp boringssl/include/openssl/aes.h \ third_party/boringssl/include/aes.h perl boringssl/crypto/fipsmodule/aes/asm/aes-armv4.pl \ > third_party/boringssl/core/cortex-m/aes.S BRANCH=none BUG=b:111160949 TEST=none Change-Id: Ia1fbb57b23e039ca5dec3d56984c83c19b7d6cd6 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1120339 Reviewed-by: Adam Langley <agl@chromium.org>
* it83xx/fpu: restore ALU at the beginning of exception handlerDino Li2018-09-101-11/+11
| | | | | | | | | | | | | | | | | | | This change prevents CPU might execute a arithmetic instruction before ALU is restored in the exception handler (Apply to floating point division by zero). We also make the change to use GP register to set system DLMB register, so we can save R4 properly and print the correct panic information. BUG=b:112452221 BRANCH=none TEST=get a panic information if we do a floating point division and divide by zero. Change-Id: I20cb20500569c004af0336d1358ab0dd4b9452b9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1201641 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm:it83xx: GRL-USB-PD TDA2.1.2.2 BIST testRuibin Chang2018-09-075-0/+20
| | | | | | | | | | | | | | | | | | | | In our design once enter BIST test data mode, Hw don't interrupt Fw due to any Rx received packet. But when port partner re-connect in this mode, it will cause that our pd port doesn't respond packet which port partner transmits. When port partner disconnects, so we need to reset our pd port protocol layer and PHY to leave BIST test data mode and let Hw can interrupt Fw. With this modify it can pass GRL-USB-PD compliance TDA2.1.2.2 test item. BUG=b:112602596 BRANCH=none TEST=GRL-USB-PD compliance test. Change-Id: I30526b5d796e3eabc9af2f524071c98bb0ef5abf Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1170718 Reviewed-by: Jett Rink <jettrink@chromium.org>
* build: print out remaining RAM spaceJett Rink2018-08-293-0/+6
| | | | | | | | | | | | | | Some boards are pretty tight on RAM space. Print out remain RAM bytes for each board along with the tightest 3 boards during buildall. BRANCH=none BUG=none TEST=buildall now outputs the tightest boards on RAM. Change-Id: I819e554400e88937bb937f2ca51daf737588a9a5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194342 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* common: add BASE_CHANGE hookDmitry Torokhov2018-08-215-0/+20
| | | | | | | | | | | | | | | Add a hook to act when a detachable device is connected/disconnected from a base. BUG=b:73133611 BRANCH=nocturne TEST=Test with evtest that an event is sent to the AP. Change-Id: I21103fff88f19a197124095ee229eebb178dcf3d Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1180538 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "**/build.mk: Set CROSS_COMPILE* to point to coreboot-sdk"Wei-Han Chen2018-08-173-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit bcd6842fb861b99588039b0bb72fafd92853525e. Reason for revert: This breaks whiskers. Original change's description: > **/build.mk: Set CROSS_COMPILE* to point to coreboot-sdk > > board/servo_v4 used it already but doesn't need the override anymore, > nds32 also used it, therefore no change. > > BUG=chromium:851727,b:65441143 > BRANCH=none > TEST=builds with the new compiler > > Change-Id: I59a7181b87293da2a8515b158c17417b5ba05404 > Signed-off-by: Patrick Georgi <pgeorgi@google.com> > Reviewed-on: https://chromium-review.googlesource.com/1172974 > Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> > Tested-by: Patrick Georgi <pgeorgi@chromium.org> > Reviewed-by: Stefan Reinauer <reinauer@google.com> Bug: chromium:851727, b:65441143 Change-Id: If09eca04efc6461b951879ad528832bc50ca50d2 Reviewed-on: https://chromium-review.googlesource.com/1177221 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Wei-Han Chen <stimim@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* test: host_command_fuzz: fuzzing testNicolas Boichat2018-08-162-5/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | Writing fuzzing tests is a little tricky, as clang takes over the main function. Instead, we start the test main function in a thread, and have LLVMFuzzerTestOneInput prepare the host command buffer, and wake the TEST_RUNNER task. To make fuzzing faster, we only send somehow correctly formed requests, with a valid checksum and length (this can be disabled with an option). We also make sure that the emulator does not hibernate, reboot or jump to a different image when fuzzing is enabled. BRANCH=none BUG=chromium:854975 TEST=make buildfuzztests -j ASAN_OPTIONS="log_path=stderr" \ build/host/host_command_fuzz/host_command_fuzz.exe -timeout=5 Change-Id: I27b25e44c405f118dfc1296247479245e15e54b4 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1107523 Reviewed-by: Manoj Gupta <manojgupta@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jonathan Metzman <metzman@chromium.org>
* **/build.mk: Set CROSS_COMPILE* to point to coreboot-sdkPatrick Georgi2018-08-153-3/+6
| | | | | | | | | | | | | | | | board/servo_v4 used it already but doesn't need the override anymore, nds32 also used it, therefore no change. BUG=chromium:851727,b:65441143 BRANCH=none TEST=builds with the new compiler Change-Id: I59a7181b87293da2a8515b158c17417b5ba05404 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1172974 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* rollback: Prevent rollback region readback using MPUNicolas Boichat2018-08-152-0/+21
| | | | | | | | | | | | | | | | | | | | We want to prevent easy readout of the rollback region, so we protect it using the MPU. There is a short duration of time where the region is unprotected (when we actually need to read the information back), but we shorten it by disabling interrupts. BRANCH=none BUG=b:111330723 TEST=flashread 0xe0000, rw 0x80e0020, md 0x80e0020, ectool flashread 0xc0000 0x1000 x => All cause EC to crash and reboot TEST=rollbackinfo still works Change-Id: I85ee757b3e261de392af03bd958b36d140a1080a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1143106 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Norvez <norvez@chromium.org>
* cortex-m/vecttable: -Wattribute-alias is supported starting GCC8Patrick Georgi2018-08-061-1/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=no more build error with gcc6 Change-Id: Ia575effe884a4816f106666dea815b48c636a858 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1138318 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>
* it83xx: clear BRAM if it is not validDino Li2018-08-031-0/+2
| | | | | | | | | | | | | | | | | IT8320 do not have indicator for VBAT power to indicate if BRAM is valid or not, so we create a magic number to do the job. And BRAM will get cleared if it is not valid. BUG=none BRANCH=none TEST=BRAM will be cleared if valid field of BRAM doesn't match the magic number. Change-Id: I6f3b166830f6c2f33f663ec0e5da9178d81d397b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1158453 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* core/nds32: Instruct linker to use fp registers for storing gp valuesPatrick Georgi2018-07-161-0/+1
| | | | | | | | | | | | | | | This significantly decreases the code size. BUG=b:65441143 BRANCH=none TEST=building reef_it8320 with gcc 8.1 works Change-Id: I4787e33a80363fa8b0f3c184167c4067ff03bffa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126317 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: Generate vector table in CPatrick Georgi2018-07-134-319/+384
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different versions of the linker behave differently when mixing object built with lto enabled (desirable for code size reduction) and disabled (assembler code), especially when they refer to each other symbols: The file evaluation order of the linker becomes important as it eliminates dead code at various points in time, and LTO code referring to non-LTO code or vice versa, is not visible at early runs. Sadly, just changing the order on the command line isn't sufficient: What works for gcc8 breaks gcc6 (and may behave different in even more ways on gcc4 or other versions). Therefore, implement the vector table in C, so it's compiled in LTO mode, just like the code it refers to. BUG=b:65441143 BRANCH=none TEST=with this change coral EC is functional when built with the gcc 8.1 based coreboot toolchain. Change-Id: I9b75f6558f0357e18000ff1161096c8f9c94a8ac Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1120333 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* assert/panic: mark noreturn to inform the compilerPatrick Georgi2018-07-123-0/+3
| | | | | | | | | | | | | BUG=b:65441143 BRANCH=none TEST=buildall with gcc8.1 stops failing on this family of functions Change-Id: I44f9d643e46f955ea0cd0b5893c2806a4e3f52b0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1126315 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* it83xx: disable ROM codestabilize-10866.BDino Li2018-07-101-0/+5
| | | | | | | | | | | | | | | | | | We dont need to use ROM code in the codebase. DX with 512KB flash space has an overlapping issue with the ROM code (0x70000 ~ 0x7ffff). This patch is to disable ROM code so we can properly use the 512KB flash space. BUG=none BRANCH=none TEST=Run console command "md .b 0x70000 256" on 512KB part, and the result is from flash instead of ROM code. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I9ad5cec44ec36b0f545324655c964bfe31f5a43f Reviewed-on: https://chromium-review.googlesource.com/1131014 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/host/task: Fix task_set_eventNicolas Boichat2018-06-271-4/+4
| | | | | | | | | | | | | | | | task_set_event is expected to _add_ the event bit to the current mask, not reset the whole mask. Also, fix all operations to use atomics. BRANCH=none BUG=chromium:854975 TEST=No more timeouts when running usb_pd fuzzing tests. Change-Id: Id17428e15f6fb8b52891bed33281f866fbc2be8f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1116624 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* core/host: Fall back to udelay when task is invalidNicolas Boichat2018-06-272-2/+3
| | | | | | | | | | | | | | | | | | | When running fuzzing tests, the sanitizer library may call usleep from the main thread, and our implementation thinks that usleep is called from idle task (task_id == 0), and just waits for an event that will never arrive. Make sure the default task id is invalid, and fall back to udelay if we are in an invalid task. BRANCH=none BUG=chromium:854975 TEST=Fuzzing tests do not fail with strange errors. Change-Id: Icc3fdce30b54dfb06913a3d6cbabaa07e1266ba6 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1116623 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Revert "nds32: make code build with gcc 8.1"Justin TerAvest2018-06-142-29/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 194c7a7e0ad27ee80abc66d211a3f7e8e4e2f4d1. Reason for revert: Breaks build for octopus-release. Original change's description: > nds32: make code build with gcc 8.1 > > *** 21744 bytes still available in flash on reef_it8320 **** > > BUG=b:65441143 > BRANCH=none > TEST=make BOARD=reef_it8320 builds with gcc 8.1. not tested at all > > Change-Id: Ie79ee23452574fd883c7f9425b8614346e46fdd7 > Signed-off-by: Patrick Georgi <pgeorgi@google.com> > Reviewed-on: https://chromium-review.googlesource.com/1077207 > Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> > Tested-by: Patrick Georgi <pgeorgi@chromium.org> > Reviewed-by: Stefan Reinauer <reinauer@google.com> Bug: b:65441143 Change-Id: I1c37701be9c40d3a4b5a77e2e04e96c37150ca30 Reviewed-on: https://chromium-review.googlesource.com/1098717 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* nds32: make code build with gcc 8.1Patrick Georgi2018-06-112-0/+29
| | | | | | | | | | | | | | | *** 21744 bytes still available in flash on reef_it8320 **** BUG=b:65441143 BRANCH=none TEST=make BOARD=reef_it8320 builds with gcc 8.1. not tested at all Change-Id: Ie79ee23452574fd883c7f9425b8614346e46fdd7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1077207 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* cortex-m: add D-cache supportVincent Palatin2018-06-046-10/+146
| | | | | | | | | | | | | | | | | | | | Add support to enable the architectural D-cache on ARMv7-M CPU supporting it. Update the MPU code in order to be able to declare an 'uncached' RAM region (e.g. to store the DMA buffer). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=with the following CL, on ZerbleBarn, boot and capture a finger image. Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285 Reviewed-on: https://chromium-review.googlesource.com/1032776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rsa: Further optimization of multiplications for Cortex-M0Nicolas Boichat2018-05-291-1/+36
| | | | | | | | | | | | | | | | | | | | In RSA, we often need to actually compute (a*b)+c+d: provide some assembly optimized functions for that. With -O3, 3072-bit exponent, lower verification time from 104 ms to 88 ms on STM32F072 @48Mhz. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=make BOARD=hammer test-utils test-rsa3, test on board Change-Id: I80e8a7258d091e4f6adea11797729ac657dfd85d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1071411 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rsa: Optimization of multiplications for Cortex-M0Nicolas Boichat2018-05-283-1/+49
| | | | | | | | | | | | | | | | | | | | | | | We multiply 2 32-bit numbers (and not 64-bit numbers), and then add another 32-bit number, which makes it possible to optimize the assembly and save a few instructions. With -O3, 3072-bit exponent, lower verification time from 122 ms to 104 ms on STM32F072 @48Mhz. Optimized mac function from Dmitry Grinberg <dmitrygr@google.com>. BRANCH=poppy BUG=b:35647963 BUG=b:77608104 TEST=On staff, flash, verification successful TEST=make test-rsa, make test-rsa3 TEST=Flash test-utils and test-rsa to hammer => pass Change-Id: I584c54c631a3f59f691849a279b308e8d4b4b22d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/449024 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: system: print out message if reset cause is unknownDino Li2018-05-283-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The message will indicate the reset is caused by which program address of jump and link instruction. BRANCH=None BUG=b:79706847 TEST=No error message under these tests: cold reset, soft reset, and sysjump. On bip, declare ".get_cc = NULL" for it83xx tcpm driver. And get the following message. log: --- UART initialized after reboot --- [Reset cause: unknown] ... ===Unknown reset! jump from f824 or f826=== [0.004504 low power idle task started] ... Disassembly: 0000f814 <tcpm_get_cc>: f814: fc 00 push25 $r6, #0 ! {$r6, $fp, $gp, $lp} f816: 46 30 00 17 sethi $r3, #0x17 f81a: 58 31 8a cc ori $r3, $r3, #0xacc f81e: 95 04 slli333 $r4, $r0, #4 f820: 88 64 add45 $r3, $r4 f822: a0 da lwi333 $r3, [$r3 + #8] f824: a0 da lwi333 $r3, [$r3 + #8] f826: dd 23 jral5 $r3 f828: fc 80 pop25 $r6, #0 ! {$r6, $fp, $gp, $lp} Change-Id: I2eaf2ad95eb92c68ce6f8240ea6ec90ac2b4a5c9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1070387 Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-221-2/+2
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-222-2/+2
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: watchdog: print LP on watchdog warningDino Li2018-05-223-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's difficult to debug problems with single watchdog warning. This patch will print IPC and LP registers continually if watchdog warning is fired. BRANCH=None BUG=b:79733639 TEST=waitms 1000, EC print warning message but no reset. waitms 3000, EC print warning message and then reset. On bip, EC is powered by servo only. And we got the following watchdog warning message: And we refer to assembly code, the IPC indicates CPU is executing instructions in "gpio_get_level()" (IPC:00002408, IPC:00002404, IPC:000023fc, IPC:0000240e), and calling from "chipset_pre_init_callback()" (LP:0000101e). Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Pre-WDT warning! IPC:00002404 LP:0000101e Pre-WDT warning! IPC:000023fc LP:0000101e Pre-WDT warning! IPC:0000240e LP:0000101e Pre-WDT warning! IPC:00002408 LP:0000101e Change-Id: I9e9429806db448624a10c348bee9c6e3d0a7765b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1060937 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Shuffle const aroundPatrick Georgi2018-05-183-3/+3
| | | | | | | | | | | | | | | | | | | | gcc 8.1 complains about duplicate const, and while some of these really are duplicate, others look like they were supposed to tighten the API contract so that variables are "const pointer to const data", but didn't have that effect. BUG=b:65441143 BRANCH=none TEST=building Chrome EC as part of upstream coreboot's build with a gcc 8.1 compiler now works (better. there are other issues left) Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1039812 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* make local functions static inlinePatrick Georgi2018-05-172-2/+2
| | | | | | | | | | | | | | | | | | | They're only used within the same file and should always be inlined. It also helps gcc 8.1's lto linking which seems to not inline it (since inline is just a hint) but then drops the function (presumably because it's small, marked inline, and comes with no prototype). BUG=b:65441143 BRANCH=none TEST=builds with gcc 8.1 Change-Id: I881a5b9f13192dd11748d8a3060788f95a84dec0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1061075 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* host: add __hw_clock_source_readAlexandru M Stan2018-05-141-0/+5
| | | | | | | | | | | | | | | | Sometimes common code needs __hw_clock_source_read, add it. The implementation is similar of what common/timer.c does to create a ts for get_time(), but in reverse. TEST=Unit tests pass again for the next CL BRANCH=master BUG=None Change-Id: I10564abedabe88e4789723bc97bac170ae020c69 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1055191 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* shared_mem: Assert that shared memory size is large enoughNicolas Boichat2018-05-073-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We add a configuration option to set the minimum shared memory size (CONFIG_SHAREDMEM_MINIMUM_SIZE), so that the link will fail if there is not enough IRAM left. Also, we add 2 macros around shared_mem_acquire, that check, at build time, that the shared memory size is sufficient for the allocation: - SHARED_MEM_ACQUIRE_CHECK should be used instead of shared_mem_acquire, when size is known in advance. - SHARED_MEM_CHECK_SIZE should be used when only a maximum size is known. This does not account for "jump tags" that boards often add on jump from RO to RW. Luckily, RW usually does not do verification, and does not need as much shared memory. BRANCH=none BUG=chromium:739771 TEST=make buildall -j, no error Change-Id: Ic4c72938affe65fe8f8bc17ee5111c1798fc536f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1002713 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* nds32: task: allow context switching if task_start() is calledDino Li2018-03-132-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | We got a symptom that keyboard didn't work without connecting servo board after this change (CL:897315) was merged. This is because our uart RX will receive a data (0) with framing error if RX level is low and trigger a re-scheduling request in uart ISR (HOOKS task will be wake at later and then start the task scheduling). And that will cause we don't return to main() function to finish all operations of initialization after uart_init() is called. I think we will get the same symptom if GPIO/peripheral interrupts are enabled and wake some task at initialization. This change makes sure we will start the task scheduling if task_start() is called. BUG=none BRANCH=none TEST=With this change, keyboard works after EC reboot without servo board connected. Change-Id: I0bda84b1cb56ced6aad2a38b0786d1b336e77211 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/956794 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: convert to CONFIG_CHIP_MEMORY_REGIONSVincent Palatin2018-03-052-26/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the former special case for USB RAM Add additional RAM regions for STM32H7. For USB RAM, add an explicit alignment directive to ensure we always meet the 8-byte boundary hardware constraint for the BTABLE. This was already true because we put the .usb_ram.btable section first. I keep this property by alpha-sorting the sections but makes it more explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection, 99_lastsection. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. TEST=build all targets with and without the patch and verify that all smap files are identical. Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175 Reviewed-on: https://chromium-review.googlesource.com/946369 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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