summaryrefslogtreecommitdiff
path: root/core
Commit message (Collapse)AuthorAgeFilesLines
* ish: add missing EOI in LAPIC error irq handlerLeifu Zhao2019-04-171-6/+16
| | | | | | | | | | | | | | | | | The LAPIC LVT error irq handler missed EOI to LAPIC at the end of the handler. BUG=b:129937881 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I890271729c5ab1d622016c32e83a8068914f69de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1567105 Tested-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* ish: add temporary workaround for lost interruptJett Rink2019-04-121-7/+12
| | | | | | | | | | | | | | | | | While we figure out how to fix the root cause for missing interrupts, we can at least get ourselves out of the back scenario by proactively checking if there is a pending IOAPIC interrupt that the LAPIC does not know about. BRANCH=none BUG=b:129937881 TEST=ISH communication does not permanently lock up Change-Id: I766b2764748ae85b17992b3c0020ba7fb4e11693 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1566472 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish/ish5: implement reset, reset_prep and D3 flowHu, Hebo2019-04-081-0/+8
| | | | | | | | | | | | | | | | | 1: reset and reset_prep implemented 2: D3 flow implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Ie6bacd89e2363578d85157dfb1dd8b56e2828d05 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1536486 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power mode (D0i1-3)Hu, Hebo2019-04-082-1/+14
| | | | | | | | | | | | | | | | | 1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented 2: D0i3 (TCG + SRAM power off) implemented BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531772 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* ish/ish5: implement AON low power management frameworkHu, Hebo2019-04-083-0/+72
| | | | | | | | | | | | | | | | | | | | | AON PM framework including: 1: AON task skeleton 2: task switching between main FW and AON task 3: 'idlestats' console command for D0ix statistic information 4: D0ix entrance in idle task BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1510518 Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* minute-ia: clean up comments about ISR=0 bugJack Rosenthal2019-04-042-10/+8
| | | | | | | | | | | | | | According to Intel, ISR=0 is actually the intended behavior, so these scary comments linking to buganizer can be cleaned up. BUG=b:28444630 BRANCH=none TEST=make buildall -j Change-Id: I877556f1719826cb72eee39e4d14e2c10412c7a9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1550706 Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* arcada_ish: ensure tests target buildsJett Rink2019-04-031-0/+7
| | | | | | | | | | | | | | | | Fix the test target for ish which is run during the test phase of chromeos-ish which is not run under buildall in EC codebase. BRANCH=none BUG=b:12237171 TEST=make BOARD=arcada_ish tests builds successfully. FEATURES=test emerge-sarien chromeos-ish now works Change-Id: I6eeaa7a15a5a026b189b67d54f28d994e6a56bb7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1548503 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/minute-ia: add IA32/x86 arch related data structure definitionsHu, Hebo2019-04-024-68/+204
| | | | | | | | | | | | | | | | | includes GDT, LDT, IDT, and TSS tables data structures definitions BUG=b:122364080 BRANCH=none TEST=tested on arcada Change-Id: I2e9fea21501a16485fbc4e05163c1f2ffbbc17f4 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1531275 Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* it83xx/i2cs: add i2c slave functiontim2019-03-301-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | The I2C function of IT8320 is used as the slave. The slave channel A can support 16-byte FIFO for read and write data. The enhanced I2C channel D, E and F can support read and write 256-byte data by DMA mode. When master transmits data to slave, the interrupt signal will generate, and the data will be saved to buffer. BUG=none BRANCH=none TEST=none Change-Id: I167215352119ec11dfd96eb1f33abc1e2111dead Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1488273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* mt_scp: Support ROM section on internal SRAM.Yilun Lin2019-03-271-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, kukui_scp's memory layout interleaves with RO and RW sections. This complicates the MPU region configuration, and it even unconfigurable. This CL propose to simplify the layout and configuration by introducing an IROM region, and re-layout the memory. New layout would be: ---------------------------- 0x0 RO| .stepping_stone | .text .rodata .data LMA ---------------------------- 0x100000 RW| .bss .data stack | ipi shared buffer ---------------------------- 0x7C0000 BRANCH=None BUG=b:123269246 TEST=1. w/o this CL: make buildall -j; mv build build.old 2. w/ this CL: make buildall -j; 3. compare smap by: ls build/*/*/ec.*.smap | \ sed -e 's|build/||' | \ xargs -I{} diff build/{} build.old/{} and sees that only kukui_scp's smap changed. Change-Id: I875a28c6b325ba66afe0387d3ea244190ddccde8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530263 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: Add watchdog timerJack Rosenthal2019-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | This adds support for the watchdog timer (WDT) available on Intel Sensor Hub (ISH). The ISH will reset after T1 expires; see the comments at the top of watchdog.c for further information on this design decision. Originally, we had planned to implement a counter that would disable the WDT after N failures. This was abandoned, since the register used to store the counter was not able to maintain a value across reset on a reliable basis (see b:128679825). BUG=b:127980538,b:128679825 BRANCH=none TEST=Used waitms command on arcada to verify WDT triggered a warning IRQ after T1 and reset the system. Change-Id: I4bd16c253110d60c57eb24cda2abc0facee20748 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1526316 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-267-21/+21
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-269-30/+32
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cortex-m/ec.ld.S: Remove explicitly allocated .data LMA sections.Yilun Lin2019-03-181-20/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Overlapping LMA section with other VMA section will fail lld. This CL makes the linker script to be compatible with both ld and lld. BRANCH=None BUG=b:128269393 TEST=On m/master; make buildall -j; mv build build.old After this CL: make buildall -j ls build/*/*/ec.*.smap | sed -e 's|build/||' | \ xargs -I{} diff build/{} build.old/{} => no difference except that __data_lma_start's attribute changes from D to R. e.g., 0011a4a0 D __data_lma_start becomse 0011a4a0 R __data_lma_start TEST=diff build/kukui_scp/RW/ec.RW.flat build.old/kukui_scp/RW/ec.RW.flat are the same, except the version strings. TEST=CC=clang make BOARD=kukui_scp and see that __bss_start and __data_lma_start not overlapping in kukui_scp/RW/ec.RW.smap TEST=CC=clang make BOARD=nocturne_fp -j and build pass. Change-Id: I4a6ece8d2279124e2797e0dc71b228a470f029d9 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1514436 Commit-Ready: Tom Hughes <tomhughes@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* minute-ia: Print panic info on processor exceptionJack Rosenthal2019-03-133-21/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds appropriate x86 exception handlers to print helpful panic info when a processor exception occurs. An example is shown below: > rw 0xFFFFFFFF 0xDEADBEEF write 0xffffffff = 0xdeadbeef ========== PANIC ========== General Protection Fault Error Code = 0xFF010000 EIP = 0xFF006363 CS = 0x00000008 EFLAGS = 0x00010202 EAX = 0x00000060 EBX = 0xDEADBEEF ECX = 0xFF01519F EDX = 0x00103085 ESI = 0xFF015280 EDI = 0xFFFFFFFF Resetting system... =========================== In addition, this fixes a bug with get_current_vector_number, causing it to return 0x100 when ISR=0. BUG=b:126691187,b:128444630 BRANCH=none TEST=loaded onto arcada using ISH shim loader, used memory access and divide by zero instructions to trigger a processor exception Change-Id: Ibd58e6cb3a28b4d9cf3aa7bfb0f13d4f6fdbb77e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1515949 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: fix vecttable.c when compiling with clangTom Hughes2019-03-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Text section name is adding ",\"a\" @" to the section name. arm-none-eabi-objdump --disassemble-all \ ./build/nocturne_fp/RO/core/cortex-m/vecttable.o Before: Disassembly of section .text.vecttable,"a" @: 00000000 <vectors>: ... After: Disassembly of section .text.vecttable: 00000000 <vectors>: ... Comparing the text.vecttable elf section headers for gcc before and after this change, there is no difference to flags: arm-none-eabi-objdump -h \ ./build/nocturne_fp/RO/core/cortex-m/vecttable.o .text.vecttable 00000298 00000000 00000000 00000050 2**2 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE One difference when compiling with clang is that it sets the DATA attribute in the header, while gcc sets CODE. Since this is an array of addresses, not executable code, I think clang is actually correct: .text.vecttable 00000298 00000000 00000000 00000060 2**2 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA BRANCH=nocturne,nami BUG=chromium:931797 TEST=make buildall -j Change-Id: I16e57ccd988a8644ed179bed057647c16e96e134 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1470779 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* core/minute-ia: Add __ram_free to link scriptNicolas Boichat2019-03-051-4/+2
| | | | | | | | | | | | | | | | | | Use __ram_free instead of defining a fake FLASH region in the linker script. This reverts commit 6fd1d521e48 ("core/minute-ia: Add FLASH memory configuration"). BRANCH=none BUG=b:123327630 TEST=make BOARD=atlas_ish -j shows *** 592328 bytes in RAM still available on atlas_ish **** Change-Id: Iacce7924dd867024e5381e31f1afb12d13305f3a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1496686 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* ish: fix LAPIC error by sending EOI to IOAPIC RTERong Chang2019-02-271-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | ISH APIC has a bug when sending multiple IOAPIC interrupts to LAPIC at the same time, there's a small chance that the IRR (interrupt request register) states are not sync between LAPIC and IOAPIC REDTBL (redirection table). LAPIC raises internal error with error code 'receive illegal vector' in ESR. This CL handles above LAPIC local vector table error condition by comparing LAPIC IRR bits with IOAPIC REDTBL entries. And sends EOI (end of interrupt) to IOAPIC RTE if corresponding vector in LAPIC IRR was not set. BRANCH=none BUG=b:112750896,b:124128140 TEST=manual Cherry pick stress test program CL:1372875 and load on Atlas. Place a touch tester on TP and connect to ground. Chech console LAPIC error count and IOAPIC pending count. Change-Id: I1cddc91b2eca35719a83415f1548379574219a58 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1411953 Reviewed-by: Jett Rink <jettrink@chromium.org>
* uldivmod.S: fix assembly so that it compiles with clangTom Hughes2019-02-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Compared the disassembly between compiling with gcc before this change and compiling with clang after the change: arm-none-eabi-objdump --disassemble build/nocturne_fp/RW/core/cortex-m/uldivmod.o --- gcc-uldivmod.txt 2019-02-12 14:54:47.283162092 -0800 +++ clang-uldivmod.txt 2019-02-12 14:52:50.098690222 -0800 @@ -103,5 +103,5 @@ 000000b8 <__aeabi_ldiv0>: b8: 4c01 ldr r4, [pc, #4] ; (c0 <__aeabi_ldiv0+0x8>) ba: f7ff fffe bl 0 <exception_panic> - be: 0000 .short 0x0000 + be: bf00 nop c0: dead6660 .word 0xdead6660 BRANCH=nocturne,nami BUG=chromium:931797 TEST=compare disassembly (see above) Change-Id: I9ab7eb18ffa9bf3e319cdd1f81047577218a0dad Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1470777 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ish: add reset prep interrupt handleyangcao2019-02-261-0/+1
| | | | | | | | | | | | | | | | | Upon reset prep interrupt from PMC, ISH HW will do warm reset. Before full stack of power management in place, this workaround will help fix S5 issue. BRANCH=none BUG=b:123528909 TEST=run "reboot" from host, ISH reboots too. Change-Id: I421ec25a198eb91672ffe770566a4edbe4855fee Signed-off-by: yangcao <yang.a.cao@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/1476299 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* ish: save/restore FPU context only for the task uses FPUHyungwoo Yang2019-02-265-14/+73
| | | | | | | | | | | | | | | | | | | Currently we save/retore FPU H/W context for every task on every contxt switch. This hurts overall performance of ISH. This patch allows save and restore FPU H/W context only for a task that declares it uses FPU. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: Ic2f0bbf59f655661e2dd788c688edc4e83068c1c Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1448818 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* mt_scp: Add functions to clean/invalidated selected ranges of D-cacheNicolas Boichat2019-02-201-4/+4
| | | | | | | | | | | | | | | | | | | | | The previous version could only work on single lines, let's add functions to work on ranges. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content TEST=flush 0x10000000 16 c => clean a single line flush 0x10000020 32 c => clean a single line flush 0x10000040 64 c => clean 2 lines TEST=flush 0x10000080 16 i => invalidate 1 line flush 0x100000a0 32 i => invalidate 1 line flush 0x100000c0 64 i => invalidate 2 lines Change-Id: Ib386eeb4ce5d2f64a23e558c7f562eba234e6b0d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475105 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Add functions to clean/invalidated selected lines of D-cacheNicolas Boichat2019-02-191-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For performance reasons, we want to be able to flush/invalidate only specific cache lines/addresses. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content: cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 3848c300 3848c301 3848c302 3848c303 3848c304 3848c305 3848c306 3848c307 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => Then clean a cache line > flush 0x10000000 c Clean cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => memory is updated => Then invalidate a cache line > flush 0x10000020 i Inval 10000020 cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => cache content is thrown away, and matches memory Change-Id: I5dbcc366236fef56f7cb048ce313247cf3d51276 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475092 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* core/cortex-m*: always use coreboot-sdkPatrick Georgi2019-02-192-4/+8
| | | | | | | | | | | | | | | It creates smaller code. BUG=chromium:851727,b:65441143 BRANCH=none TEST=builds with the new compiler Change-Id: I569c6f75a595331fb489323d8b3f02d5dd2d5050 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1450713 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* core: Allow .bss and .data sections in DRAMNicolas Boichat2019-02-181-0/+27
| | | | | | | | | | | | | | | | | We manually copy other .data from the original section on boot, and clear DRAM .bss. This way, a single object file (or archive) can be moved fully to DRAM. BRANCH=none BUG=b:122058243 TEST=With next CL, dram_test works Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1445652 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: no need to keep a special term for Tpm2_ modulesVadim Bendebury2019-02-101-1/+0
| | | | | | | | | | | | | | | | | With tpm2 makefile now re-naming .bss section in the produced objects, there is need to try grouping files by module name, especially since this does not even work when linking object modules directly instead of the library. BRANCH=cr50, cr50-mp BUG=b:65253310 TEST=make BOARD=cr50 -j produces an image with the same _bss_libtpm2 section. Change-Id: I38f8ec3efa0364a0ad58781b7822a0eb52b636bb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1457602 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* core/cortex-m: mark gcc helper function "used"Patrick Georgi2019-02-071-1/+1
| | | | | | | | | | | | | | gcc injects calls to that function without notifying LTO. BRANCH=cr50, cr50-mp BUG=b:65253310 TEST=after the entire stack was applied Cr50 builds successfully with CONFIG_LTO enabled, and passes TCG test suite. Change-Id: Ie116423a2e8a394dae9d6c7c373786615d9fba4c Signed-off-by: Patrick Georgi <pgeorgi@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1411540
* ish: allow IRQ only after scheduler is readyHyungwoo Yang2019-02-041-0/+5
| | | | | | | | | | | | | | | | | | Interrupt should be enabled after scheduler is ready to handle context switch. This patch makes sure interrupt can be enabled only after the scheduler is ready. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: Idddfcb333b1d66b7b15e3f65042dd62331f6f282 Reviewed-on: https://chromium-review.googlesource.com/1446991 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: use system stack for exceptions and irqsHyungwoo Yang2019-02-042-0/+15
| | | | | | | | | | | | | | | | | | | currently exceptions are using current preempted task stack. It means the size of each task stack should be more than it needs while considering maximum stack usage of exceptions. It waste memory and engineering efforts. this patch uses system stack for handling exceptions. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: I1c8fdc16e9f7a3834638b5ce0916f00b3d440798 Reviewed-on: https://chromium-review.googlesource.com/1440022 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: move setting start_called to proper placeHyungwoo Yang2019-01-313-5/+4
| | | | | | | | | | | | | | | | | | | | | | | Some functions(like enabling interrupt) should start after scheduler is ready and they use start_called which indicates if scheduler is ready or not. Currently start_called is set by the first task but it is away after the task did many things. So this patch moves the setting start_called to the place where the scheduler is ready. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: I24d9cec411e91b7365f46fa8daf4a02fe43287dd Reviewed-on: https://chromium-review.googlesource.com/1444792 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: remove unnecessary interrupt_enable() callHyungwoo Yang2019-01-311-1/+0
| | | | | | | | | | | | | | | | interrupt is already enabled when the first task(hook_task) scheduled. this patch removes unnecessary interrupt_enable(). BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: I4b1458a6ad2d72347720630181ef7e35bc7fc66b Reviewed-on: https://chromium-review.googlesource.com/1444538 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: support task argumentHyungwoo Yang2019-01-301-1/+1
| | | | | | | | | | | | | | | | This patch supports the opaque parameter for task. the parameter is specified in ec.tasklist. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: I7451c27784b9e889823f62d7f3de41dd7e2d2b43 Reviewed-on: https://chromium-review.googlesource.com/1442113 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: apply FPU context of the first taskHyungwoo Yang2019-01-301-0/+3
| | | | | | | | | | | | | | | | | | | FPU H/W configuration is available per task and it is initialized in task_pre_init() but currently the configuration for the first task is ignored due to lack of restoring(to H/W) in __task_start() function. This patch makes sure that the configuration restored to H/W. BRANCH=none BUG=none TEST=verified in Atlas platform Change-Id: I974fec779b3683fa7e9413dc73a4b8dcfb291596 Reviewed-on: https://chromium-review.googlesource.com/1435484 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: fix task profilingJett Rink2019-01-305-50/+78
| | | | | | | | | | | | | | | | | | | | | | | | Previously when performing 'taskinfo' command on ISH5, the time spend in exception was very high. The time spent in each task was also negative. The task profiling was broken in many ways. This CL fixes the following: - Added correct exception start and end times through out - Updated exception (isr) start and end time to 32-bit so we don't have issues with 32-bit time rollover - Fixed time spending in task, exception, and IRQ distribution - Fixed code that determines which vector is being serviced. Calculation before was backwards previously. - The IRQ_COUNT for ish was too small so we couldn't correctly profile the IRQ distribution BRANCH=none BUG=b:121343650,b:112750896 TEST='taskinfo' behaves correctly on aracada (ISH5) Change-Id: I643d3133a608865a1862a70585cfeced4d24649d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389058 Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com>
* cortex/cortex-m/ec.lds.S: Preserve space for .data section's LMA.Yilun Lin2019-01-291-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If .text, .rodata and .bss section are all puts in the same memory space, e.g. RAM (.data section's LMA is usually located right after .rodata section, and right before .bss section.). .data section's LMA might be overlapped with .bss section so that it would get cleared to zero on program startup. TEST=Remove ". = ALIGN(512);" in .bss section in linker script, and check build/kukui_scp/RW/ec.RW.smap, and we have __data_lma_start = 0x74b4 __bss_start = 0x74f8 __data_start = 0x8ae0 __data_end = 0x8b20 __data_end - __data_start = 64 __bss_start - __data_lma_start = 68 # .data is able to fit in. check .data section LMA won't be overlapped with .bss section VMA. BUG=b:122084384 BRANCH=None Change-Id: Ic6ae7ad7c6a080ce7aa6375c4f0e01ac9474cdc7 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1404640 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* link_defs.h: Renames __ro_end to __data_lma_start.Yilun Lin2019-01-286-12/+12
| | | | | | | | | | | | | | | | | | The name of __ro_end is confusing. The variable is actually used as a label tagging that it is the starting address of .data LMA. Renames to __data_lma_start to be more decriptive. BRANCH=None TEST=make buildall -j BUG=b:122084384 Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1433160 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ec: Add a task_reset function.Louis Collard2019-01-261-25/+343
| | | | | | | | | | | | | | | | | | | | | | | | | This adds a generic task_reset function that can reset any task that declares it supports being reset. Tasks that support reset must call task_reset_cleanup() on startup, and be prepared to perform any cleanup / re-initialisation necessary. The task can control when it can be reset using task_enable_resets() and task_disable_resets(). A task can request another task be reset at any point; if the reset cannot happen immediately, it will be queued and will happen at the earliest point allowed by the task to be reset. Task resets can be blocking or non-blocking, as specified by the requestor. BUG=b:73771117 BRANCH=none TEST=manual testing on local device Change-Id: I972184381b005c342374fa16c4dce2ac83e89854 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1230394 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* mt_scp: Add support to store some code in DRAMNicolas Boichat2019-01-241-0/+11
| | | | | | | | | | | | | | | | | This allows to store specific code/data in a .dram region. This is used by mt_scp to run code off DRAM, as we plan to have more code than what can fit in SRAM. BRANCH=none BUG=b:122058243 TEST=make BOARD=kukui_scp -j objdump -x build/kukui_scp/ec.obj => Some code is loaded in DRAM TEST=Load kukui_scp, icachetest works Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391542
* ish: balance all __in_isr callsJett Rink2019-01-172-8/+9
| | | | | | | | | | | | | | | | If we encountered an unregistered IRQ vector we would not decrement the __in_isr global properly which would cause the ISH to lock up. BRANCH=none BUG=b:121343650,b:112750896 TEST=With patch stack on arcada (ISH5) 'taskinfo' command works as expected. Change-Id: I3975356226d92a81bfd207d77bba42f3f8b30bb8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1392416 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ish: add inline math functionsRong Chang2019-01-171-1/+203
| | | | | | | | | | | | | | | | | This change adds inline math functions: logf(), expf(), powf(), ceilf(), atan2f(), atanf(), sinf(), cosf(), acosf() BUG=b:120961468 BRANCH=none TEST=none Change-Id: I92460b332b24b6d9971ce989c0cd799111cdd239 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1077709 Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: update copyright header to match styleJett Rink2019-01-1713-13/+13
| | | | | | | | | | | | | Without this fix presubmit checks complain when touching files BRANCH=none BUG=none TEST=no presumbit complains Change-Id: I2c30865d2782642d4030bc3d922ff92212ff97e8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1415830 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* minute-ia: set -O2 and omit frame ptrJett Rink2019-01-161-1/+1
| | | | | | | | | | | | | | | | | | | There is a lot of unnecessary stack frame assembly being generated in the final image. Turn up optimization to -O2 and omit the frame pointer. BRANCH=none BUG=b:122526004 TEST=verified the disassembly is much smaller and does not write register to the stack all the time. Also loaded Arcada ISH5 with optimized image and it boots fine. Change-Id: I2a6db49d75964fa8bd6c0f58166c1e76c04a15c9 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1405770 Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* core/minute-ia: set single precision for FPUKyoung Kim2019-01-101-2/+6
| | | | | | | | | | | | | | | | Set FPU single precision to improve trackpad processing time at default fpu context. BUG=b:120885570 TEST=check improvment of TP frame processing. Change-Id: Id78e878b4b38043c9c15b75d90dfd108e7de02a2 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1383551 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* ish: remove lock; prefix from inline ASMJett Rink2019-01-083-5/+19
| | | | | | | | | | | | | | | | | | Since all instances of minute-ia core are a single core, the lock; prefix on statements does not have any meaningful affect other than a potential performance hit. We still want to mark inline asm where it would matter, so we introduce a new define that evaluates to empty today. BRANCH=atlas_ish BUG=none TEST=builds Change-Id: I47506951dfdabfdbd16ae825fe742b01b44205d1 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1401014 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ish: remove unused codeJett Rink2019-01-042-45/+2
| | | | | | | | | | | | | | | | The variable need_resched_or_profiling wasn't being used in a way that was meaningful and added unnecessary complexity. Removing. BRANCH=none BUG=b:121343650 TEST=build with profiling disabled and task switching on aracarda still works Change-Id: Ic54bcb0f3c6b66aecbb8cf806ead5dd3695bdb35 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389057 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Caveh Jalali <caveh@google.com>
* stdlib cleanup.Allen Webb2019-01-031-4/+0
| | | | | | | | | | | | | | | | This cleanups some header includes to avoid conflicts between the ec headers and the standard c headers. BRANCH=None BUG=None TEST=make -j buildall && ./build_packages --board=veyron_minnie \ chromeos-ec && FEATURES=test emerge-veyron_minnie chromeos-ec Change-Id: Icf9022d688fd9c749f7a5f8673755188741b40e1 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1378906 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/minute-ia: fix atomicsHyungwoo Yang2018-12-231-16/+13
| | | | | | | | | | | | | | | | | | | | | | this fixes a few wrong implementation on atomic. atomic_read_clear() and atomic_clear() were functinally broken. Due to this, key control flow which rely on these functions were out of order. Also modified ATOMIC_OP() and bool_compare_and_swap_u32() to give more accurate directives to compiler. BUG=b:119628522 BRANCH=none TEST=tested on atlas Change-Id: Ide8397e4f7b754a7094c66326ecc2450ef2f0cc9 Reviewed-on: https://chromium-review.googlesource.com/1305118 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/cortex-m: Support prevent chip memory region from GC.Yilun Lin2018-12-231-0/+10
| | | | | | | | | | | | | | | | | | | We would like to keep a symbol in a chip memory region from GC in link time. However __attribute__((used)) cannot fulfill the requirement in such situation. This CL adds a "name.keep" section to prevent all the symbols in this section in a chip memory region from GC. Also, we would like to support a non-NOLOAD section, which can load default value on runtime. BUG=b:120825336 TEST=make buildall -j BRANCH=none Change-Id: I76cf445f6b4c0b61c20182a1aaf5a44f962049ae Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373949 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/minute-ia: enable cacheKyoung Kim2018-12-201-0/+9
| | | | | | | | | | | | | | | | Enable cache CR0.CD and CR0.NW Trackpad frame processing improved with cache on. BUG=b:120885570 TEST=check overall performance improvement including TP frame processing. Change-Id: I18d27b28255d5775c71b7562e18a1d102ee35feb Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1378659 Commit-Ready: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* core/minute-ia: default_fp_ctx[] should be staticRushikesh S Kadam2018-12-191-1/+1
| | | | | | | | | | | | | | | | Define the default_fp_ctx[] for initial FP state as static variable. BRANCH=none BUG=b:120582727 TEST=Succesfully compile for ISH target Change-Id: Iac60a814ab7a9c3090b47472adebf05b1341c5fb Reported-by: Caveh Jalali <caveh@google.com> Signed-off-by: Rushikesh S Kadam <rushikesh.s.kadam@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1365155 Commit-Ready: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
View Lorry Controller Status