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* ec: change usage of "sane" per inclusive languagePaul Fagerburg2020-07-227-7/+7
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the terms "sane", "sanity check", and similar with inclusive/non-stigmatizing alternatives. BUG=b:161832469 BRANCH=None TEST=`make buildall -j` succeeds. `grep -Eir "sane|sanity" .` shows results only in third-party code or documentation. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I29e78ab27f84f17b1ded75cfa10868fa4e5ae88c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311169 Reviewed-by: Jett Rink <jettrink@chromium.org>
* riscv-rv32i: correct printf formatEric Yilun Lin2020-07-221-7/+7
| | | | | | | | | | | | | | unsigned integer should use '%u' rather than '%d' BUG=b:161768286 TEST=make BOARD=asurada BRANCH=none Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Change-Id: I84a5419ce813a4378657c4fbfeba967262faef3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2310220 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* host: Fix task_wait_event() to return TASK_EVENT_TIMEREdward Hill2020-07-131-0/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make -j runhosttests Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ibd753b2eec5d81438dc0884b1a0c12c4c319afe2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294164 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* core/riscv-rv32i: add atomic_inc and atomic_decTzung-Bi Shih2020-07-031-6/+11
| | | | | | | | | | | | BRANCH=none BUG=b:146213943 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3d87c9906df1b631fa3733eeae92d356ec287611 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2275710 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: set volatile for in_interruptTzung-Bi Shih2020-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | Given that: - in_interrupt is modified in interrupt context. - Some normal task context call in_interrupt_context() and in_soft_interrupt_context(). To safely share the variable, sets it to volatile. BRANCH=none BUG=b:146213943 BUG=b:157521370 BUG=b:156223049 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ibd1bf9556d8376f6f6389a17cc792a6f21227d4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2237495 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-066-0/+24
| | | | | | | | | | | | | | | | | | | A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are called from the chipset task, while the system has already shut down and all the suspend rails are already off. It will be used for executing pending EC reboot at the chipset shutdown. The EC reboot should be executed when the chipset is completely off. BRANCH=None BUG=b:156981868 TEST=Built all boards. Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-042-12/+6
| | | | | | | | | | | | | | | | | | Return values of chip_enable_irq(), chip_disable_irq(), and chip_clear_pending_irq() are not using. Removes them. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic7e3e80483f76f35bfe7781ddea48515ab8e3361 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227778 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-042-10/+21
| | | | | | | | | | | | | | | | | | chip_get_ec_int() returns -1 if it cannot find the corresponding interrupt source. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I5021ed80f50a99b15d9b9a90a9181077f63bd4be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227777 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-031-0/+6
| | | | | | | | | | | | | | BRANCH=none BUG=b:146213943 BUG=b:156218912 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Change-Id: If8df1fb768ea9c83f025d8bd17010481389d7aa1 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217596 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* test: Pass commandline arguments to run_testTom Hughes2020-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | run_test is called by the "runtest" console command. Console commands can take arguments, so pass along the arguments to run_test to allow parameters to be passed to run_test. The following command was used for automatic replacement: git grep --name-only 'void run_test(void)' |\ xargs sed -i 's#void run_test(void)#void run_test(int argc, char **argv)##' BRANCH=none BUG=b:155897971 TEST=make buildall -j TEST=Build and flash flash_write_protect test > runtest 1 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib20b955d5ec6b98f525c94c24aadefd7a6a320a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2209418 Reviewed-by: Yicheng Li <yichengli@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* test: Add on-device test for calculating MPU regions for RWYicheng Li2020-05-303-18/+36
| | | | | | | | | | | | | | | | MPU logic needs to represent RW with no more than 2 MPU regions when locking RW. Add on-device unit test for this calculation. BRANCH=none BUG=b:155410753 TEST=make -j BOARD=bloonchipper TEST=make -j BOARD=nucleo-f412zg test-mpu Then flash the test binary to nucleo board runtest on device ==> Pass Change-Id: Idc746efa9419d31cdae9c6fccc499c92160ac593 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2218595
* cortex-m: Use MPU REGION_CODE_RAM to lock rollback if neededYicheng Li2020-05-291-1/+1
| | | | | | | | | | | | | | | On chips with only 8 MPUs, we need to lock the rollback with unused MPU regions. Since REGION_STORAGE2 may be used to lock RW, use REGION_CODE_RAM instead. BRANCH=none BUG=b:155410753 TEST=make -j buildall Change-Id: Iec0f33b668474ed539809a319bf94d11cb52f64a Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219578 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m: Lock RW flash using aligned MPU regionsYicheng Li2020-05-291-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | On Cortex-M3, Cortex-M4, and Cortex-M7, the base address used for an MPU region must be aligned to the size of the region: https://developer.arm.com/docs/dui0553/a/cortex-m4-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0646/a/cortex-m7-peripherals/optional-memory-protection-unit/mpu-region-base-address-register#BABDAHJG Try to represent RW flash using aligned MPU regions before configuring MPU. Otherwise configuring MPU will fail. BRANCH=none BUG=b:155410753 TEST=triggered mpu_lock_rw_flash() on bloonchipper and dartmonkey and checked that configuring MPU succeeded. TEST=on bloonchipper and dartmonkey, verified that the MPU configurations make sense by adding logging. Change-Id: Ib460354ea60e96d7b6ac4a4c12730b0db7c6aaac Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: remove get_sw_int()Tzung-Bi Shih2020-05-292-18/+2
| | | | | | | | | | | | | | | | Inline the function definition. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Icfde6399b2dd560924128f9e7fbeb54efaa9c14c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217595 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: Init the MPU to check for correct operationAndrew McRae2020-05-272-2/+25
| | | | | | | | | | | | | | | | Disable all a MPU regions using the smallest supported size. BUG=chromium:1085868 TEST=Boot successfully on Puff TEST=Boot successfully on Volteer BRANCH=none Change-Id: Ie6924c3d9691ba6f4b218c9897b4e42b35b12bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212010 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* test: Add on-device MPU unit testTom Hughes2020-05-221-0/+3
| | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:151105339, b:155229277 TEST=make BOARD=bloonchipper test-mpu -j && \ ./util/flash_jlink.py --board bloonchipper \ --image ./build/bloonchipper/mpu/mpu.bin => On console: "runtest" => All tests pass, except last which correctly panics: Data access violation, mfar = 20000000 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1c759f50da5075b1e9027cdba253d8c06843be5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202852 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* core/cortex-m: create private MPU header for use by unit testsTom Hughes2020-05-222-5/+29
| | | | | | | | | | | | | | | | | Expose definitions that we want to use in unit tests, but are internal details that should not be used by other EC code using the rollback functionality. BRANCH=none BUG=b:155229277, b:156501835 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iab14a0cf17d4a986f1a1d9b77d27957976962078 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202851 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* cortex-m/mpu: Check alignment when applying MPU configTom Hughes2020-05-221-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibba15e5319832ba0e0efde913275d618e249bc44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202850 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m: Always enable MPU in mpu_pre_initTom Hughes2020-05-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPU was only being enabled when CONFIG_ARMV7_CACHE and CONFIG_CHIP_UNCACHED_REGION were enabled; these are enabled for the STM32H743 (dartmonkey), but not the STM32F412 (bloonchipper). BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I7bca3864205bd1dd6797732aa903bc3bc325ac6f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200201 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cortex-m: Configure rollback MPU based on number of regionsTom Hughes2020-05-221-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rollback MPU support was initially added for the Cortex-M7, which can support 16 MPU regions. REGION_ROLLBACK was defined as MPU region 10. For the Cortex-M4, there are at most 8 regions, so we have to repurpose some of the existing (unused) regions. BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748b7ea0654dee01d27bb560e82491665025d1ef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200200 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* cortex-m: Clean up MPU logicTom Hughes2020-05-222-18/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add error checking for failures and use IS_ENABLED combined with helper functions for readability. BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Memory is successfully read => FAIL TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0f8d149c8c5c568241457a6779079c65eb38ce32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200199 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: define dummy implementation for CPU_INTTzung-Bi Shih2020-05-191-0/+5
| | | | | | | | | | | | | | | Defines dummy implementation for CPU_INT for non-IT8XXX2 chips. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3c9587133d110fed95042da6c75f1e64e1f87fda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2124436 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: add default __idle()Tzung-Bi Shih2020-05-191-0/+4
| | | | | | | | | | | | | | | Adds default __idle() implementation. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ie4711b568f8d1880eb933027c10fc43672871d23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178701 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: clean up header inclusionsTzung-Bi Shih2020-05-193-10/+4
| | | | | | | | | | | | | | | | | | | | Removes unneeded header inclusions. Especially chip-specific ones: - hwtimer_chip.h - intc.h - registers.h Other rv32i-based boards do not need to provide the headers. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6d158568fb6b626d96215bbd263b66cd8b7ebd57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178700 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: do not expose get_sw_int()Tzung-Bi Shih2020-05-194-12/+2
| | | | | | | | | | | | | | | Do not expose get_sw_int(). BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I9a5bbeec152780b54b4dd6ce07f2390633c64366 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178699 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-194-40/+26
| | | | | | | | | | | | | | | | Getting source interrupt number is chip specific. Moves the details to chip implementation. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ia72acf8ec9c09cb329f8d7c92d22476512ffa669 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114951 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: guard more IT83XX chip specific itemsTzung-Bi Shih2020-05-191-10/+7
| | | | | | | | | | | | | | | | | | | | Guards IT83XX chip specific: - E-flash signature. - BRAM (Battery-backed SRAM). Moves IT83XX_GCTRL_EIDSR to IT83XX chip specific. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I05ea628c6b745136043b9505c98204381bd7a0ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114950 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
* core/riscv-rv32i: separate CHIP_FAMILY_IT8XXX2 specific memory regionsTzung-Bi Shih2020-05-191-9/+55
| | | | | | | | | | | | | | | Separates CHIP_FAMILY_IT8XXX2 specific memory regions. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I0b337b366e428667ef56cf0a0060c22fe6d2046f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109443 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* cortex-m: provide a function to set IRQ priorityPeter Marheine2020-05-194-18/+32
| | | | | | | | | | | | | | | | On Puff we need to increase some IRQ priorities to meet strict timing requirements. To support that, provide a function encapsulating the bit manipulations to adjust the priority of a single IRQ and update task.c to take advantage of it. BUG=None BRANCH=None TEST=Still builds. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* ish: enable IPAPG for ish 5.4 on tgl rvp platformLeifu Zhao2020-05-151-0/+7
| | | | | | | | | | | | | | | | | Enable ip accessible power gating for ish 5.4 on tgl rvp platform. BUG=b:154891699 BRANCH=none TEST=ISH can successfully enter into IPAPG on tgl rvp. Change-Id: Iee30124a0928389f4c75dffff065fab7a5a2d970 Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2164091 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* risc-v: add comments about not needing 16-byte stack frame alignmentDino Li2020-05-133-7/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we are not actually executing on a stack frame that is not 16-byte aligned, we are following the guidance (linked below). Add comments for future developers to explain why. Also, saving system stack pointer in the switch to function since the isr function takes special care to not over write the stack pointer when we are already using the system stack. According to documentation, the stack frame should be 128-bit aligned upon entering function boundaries. "In the standard RISC-V calling convention, the stack pointer sp is always 16-byte aligned" from https://riscv.org/specifications/isa-spec-pdf/ "The stack grows downwards (towards lower addresses) and the stack pointer shall be aligned to a 128-bit boundary upon procedure entry" from https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md See also documentation issues discussing this https://github.com/riscv/riscv-elf-psabi-doc/issues/21 BRANCH=none BUG=none TEST=ITE RISC-V FPU implementation still works Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I3460e6ee2b68c7793c72517e7d2d9bc645aaea65 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2173119 Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/cortex-m[0]: Move core functions assembly files to third_partyNicolas Boichat2020-03-256-765/+6
| | | | | | | | | | | | | | | | The code originally comes from libaeabi-cortexm0. It is unclear which exact git commit the code comes from, but since we have used it without issue for 5 years, it is reliable, and a refresh is probably not required at this stage. BRANCH=none BUG=chromium:884905 TEST=make buildall -j, which also include basic tests. Change-Id: I910c1c4e6a46b2f0fe8b7a429f1b6f0f50c2dc21 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1599762 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/cortex-m0/curve25519: Move code to third_party folderNicolas Boichat2020-03-257-3240/+1
| | | | | | | | | | | | | | Also, add LICENSE file (some files are under CC0, some are public domain), and METADATA file. BRANCH=none BUG=chromium:884905 TEST=make buildall -j, which also include basic tests. Change-Id: Ib3a7eb9245a0634c4052064c3e36cbe2ddafbcb9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1599761 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-211-0/+15
| | | | | | | | | | | | | | | | | | | | | | | IT81302 (144-pins package) and IT81202 (128-pins package) chips belong to it8xxx2 family. So we apply the same chip options of it83202bx (except ADC pin order config option) and setup the correct flash size, ram size, and ram base. With this change, we are able to build FW image with IT81202 or IT81302 chip variant. BUG=none BRANCH=none TEST=EC boots and test console commands (version, sysinfo, sysjump, flasherase, flashwrite, and flashread) on IT81202 EVB. Hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-192-50/+34
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
* remove cr50 related filesNamyoon Woo2020-03-091-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:149350081 BRANCH=none TEST=build all, and emerged ec related packages for host and octopus. $ make buildall -j $ cros_workon --host list chromeos-base/chromeos-cr50-dev chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge chromeos-cr50-dev -j $ sudo emerge chromeos-ec -j $ sudo emerge chromeos-ec-headers -j $ sudo emerge ec-devutils -j $ sudo emerge ec-utils -j $ sudo emerge ec-utils-test -j $ sudo emerge hdctools -j $ cros_workon-octopus list chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge-octopus chromeos-ec -j $ sudo emerge-octopus chromeos-ec-headers -j $ sudo emerge-octopus ec-devutils -j $ sudo emerge-octopus ec-utils -j $ sudo emerge-octopus ec-utils-test -j $ sudo emerge-octopus hdctools -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: If751b26b0635b0021c077338e96eaa8e8dcf17a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080631 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ish: infrastructure changes to support ish5.4 PMLeifu Zhao2020-02-271-1/+3
| | | | | | | | | | | | | | | | | | Infrastructure related changes to support enabling power management for ish5.4 on tgl rvp platform. BUG=b:149238813 BRANCH=none TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* core/riscv-rv32: link libgcc for 64-bit divisionDino Li2020-02-251-0/+1
| | | | | | | | | | | | | | | | We made this change to fix the issue of __udivdi3 routine is missing in host_command_get_uptime_info() function. BUG=none BRANCH=none TEST=There is no error on building it83xx_evb with selecting riscv core. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ib745114e7be2a371b18b9268423e9ddd34bfde61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866214 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* host: Add basic taskinfo console commandCraig Hesling2020-02-051-0/+22
| | | | | | | | | | | | BRANCH=none BUG=none TEST=./build/host/aes/aes.exe > taskinfo Change-Id: I91bb17b8c65564fd91510755510974de9357731c Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2034998 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* riscv-rv32i: Add sqrtf functionDino Li2020-01-223-1/+33
| | | | | | | | | | | | | | | | | | The int_sqrtf() requires this function if we enable FPU. BRANCH=none BUG=none TEST=manual testing on console command: sqrtf(1.23) = 1.10 sqrtf(0.45) = 0.67 sqrtf(0) = 0 Change-Id: I354453674559ff2e1b956c9dba47baa493332871 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982298 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw>
* core/riscv-rv32i: enable software ctzDino Li2020-01-221-0/+5
| | | | | | | | | | | | | | | Because we don't support risc-v bit manipulation extension (CLZ/CTZ instructions) yet, so we enable the software implementation to fix build error while __ctzsi2 is called. BUG=none BRANCH=none TEST=no build error. Change-Id: If916010b9004f95aa4ccfd533be9539aff4c3f50 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982295 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/system: Extract and doc cortex constCraig Hesling2020-01-132-1/+12
| | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=make buildall -j TEST=make BOARD=nucleo-h743zi # Reboot H743 into bootloader using boot0 pin and reset # Flash nucleo over FTDI and STM32 bootloader stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200 # Reset without boot0 # Open console minicom -D/dev/ttyACM0 reboot soft # Verify soft reset was used reboot hard # Verify hard reboot was used Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: Format linker scriptCraig Hesling2019-12-161-221/+228
| | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: I8dd252f6b53c510dbeedee1f33d4de35ce0d8922 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1970430 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/nds32: Format linker scriptCraig Hesling2019-12-161-213/+217
| | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: Id87f33d3a69f3c2ff5dffc761932eee823f301c7 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1966290 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/minute-ia: Format linker scriptCraig Hesling2019-12-161-10/+10
| | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: I481233b20c017355b1c3c9b6e4010ea9e7ef8560 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1966289 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/host: Format linker scriptCraig Hesling2019-12-161-117/+117
| | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: I55bef2d9f1a4e3e544b2ef1b4d28825b3a628a44 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1966288 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cortex-m/m0: Reformat linkers script with tabsCraig Hesling2019-11-262-604/+635
| | | | | | | | | | | | | | This is just a cleanup of the linker scripts for cortex-m chips. This brings no functional change. BRANCH=none BUG=none TEST=make buildall Change-Id: If9fa43157e8955fed7c7426b910c6af957794b0b Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930392 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/nds32 and riscv-rv32i/ec.lds.S: no assert if section is not presenttim2019-11-222-2/+4
| | | | | | | | | | | | | | | When the h2ram section is not present, we don't need the assert to check the space whether enough or not. BUG=none BRANCH=none TEST=No error when we don't define configration of CONFIG_HOSTCMD_x86 or CONFIG_H2RAM_SIZE. Change-Id: Id5d0e674f65cfdb220bc996c597740390000d861 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: chip enablement of ish5.4 on tgl rvp platformLeifu Zhao2019-11-091-1/+3
| | | | | | | | | | | | | | | | | Chip level enablement of ish5.4 on tgl rvp platform. BUG=b:141519691 BRANCH=none TEST=tested on tgl rvp Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* host: remove leftovers from using system clock in testsJack Rosenthal2019-10-251-21/+0
| | | | | | | | | | | | | | There was some leftover constants and a #include we are no longer using due to using a monotonic counter, clean it up. BUG=chromium:1013701 BRANCH=none TEST=buildall Change-Id: Ieeb130aef9ee89d65459f52c8f34753c30c3c388 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879335 Reviewed-by: Edward Hill <ecgh@chromium.org>
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