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* riscv-rv32i/task: Remove the remove_me functionDino Li2021-04-081-12/+0
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=buildall. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I2cd176556f2294de304eca3d2e3d29f68cff85dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531769 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Hooks: Add HOOK_CHIPSET_HARD_OFFDiana Z2021-03-186-0/+24
| | | | | | | | | | | | | | | Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry to the G3 power state. BRANCH=None BUG=b:166787955,b:167996216,chromium:1045209 TEST=make -j buildall, runs on waddledee with no linking errors Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/riscv-rv32i: rearrange symbols in ILMTing Shen2021-03-031-19/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The symbol `current_image_data` must be located in a static place, so EC-RO can always find the required information inside EC-RW. Move the symbol to a lower offset to make it's location not affected by future code change. BUG=b:181203269 TEST=1) bootable on hayato 2) ec.RW.smap: 80080000 T __flash_dma_start 80080000 t __startup 80080004 t __irq 80080008 t __ec_intc 80080080 T eflash_sig 80080090 T current_image_data 80080090 T __image_data_offset 800800c0 T __entry_irq_0 ... 800800fc T __entry_irq_15 80080100 T __entry_syscall 80080104 t __irq_isr BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iaf05ed8f758d99981eec432afbe404ac2c469dec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2722051 Reviewed-by: Dino Li <dino.li@ite.corp-partner.google.com> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* cortex-m/m0: Add Debug Halting Control and Status RegisterTom Hughes2021-02-236-2/+53
| | | | | | | | | | | | | | | | | | | | | For Cortex-M0, see "C1.6.3 Debug Halting Control and Status Register, DHCSR" in the ARMv6-M Architecture Reference Manual. For other Cortex-M, see "C1.6.2 Debug Halting Control and Status Register, DHCSR" in the ARMv7-M Architecture Reference Manual or https://developer.arm.com/documentation/ddi0337/e/core-debug/core-debug-registers/debug-halting-control-and-status-register. BRANCH=none BUG=b:180144572 TEST=Using Segger J-Trace Pro with icetower v0.1, verify debugger_is_connected is true when debugger is attached and false otherwise Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748fc26c0db4351be5a83086fdb843e5651b5425 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2713753 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/riscv-rv32i: set in_interrupt at beginning of exception handlerTzung-Bi Shih2021-02-192-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are 3 paths when receiving an excaption in core/riscv-rv32i/init.S: 1. __irq_handler 2. excep_handler 3. unhandled_interrupt Originally, in_interrupt_context() returns true only if it goes to 1st path. However, the rest paths are also in interrupt context, especially some function may rely on in_interrupt_context(), for example, uart_flush_output() in common/uart_buffering.c. Note that, only the 1st goes back to normal context. The rest of paths are all going to panic and reset. Sets in_interrupt at the beginning of exception handler instead of start_irq_handler() so that the flag is ON when receiving an exception. BRANCH=none BUG=b:180571536 BUG=b:163300760 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Iba689c506c02c4b5bb1668766f1d7ab5f86f72a4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2702999 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* cortex-m0: convert "b" register constraints to "l"Peter Marheine2021-02-181-4/+4
| | | | | | | | | | | | | | | | | | GCC defines the "b" constraint for ARM targets as the union of the stack register and low registers (r0-r7), but that constraint is marked as internal (not intended for general use) and is not supported by Clang. Instead use "l" (the low registers only), which is intended for general use and supported by clang. BUG=b:172221010 TEST=builds BRANCH=None Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I584274b2aa1c68dfdfef80de779191d1f4d0e7b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2695054 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* core/cortex-m/mpu.c does not compileDenis Brockus2021-02-051-1/+2
| | | | | | | | | | | | | | | | | Fix for loop to be compatible with the tools used in the builders BUG=chromium:1175163, chromium:1175181 BRANCH=none TEST=make buildall Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Ic4d6f1b8aea0e20391eeb0d9496275289a7e21fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2678794 Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jae Hoon Kim <kimjae@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* riscv-rv32i: store EC interrupt number in panic infoDino Li2021-02-042-24/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change stores EC INT number in panic info (TP register) if the number isn't valid. For CPU interrupt and exception code, we can check mcause register in panic info. BUG=b:179206540 BRANCH=none TEST=fire an invalid EC INT (eg, number 188) and checking panic info to see if the number is stored in TP: === EXCEPTION: MCAUSE=8000000b === S11 00000000 S10 00000000 S9 00000000 S8 00000000 S7 00000000 S6 00000000 S5 ffe17b7f S4 fff0bdc0 S3 0000fffe S2 00000000 S1 00000000 S0 00000000 T6 00000000 T5 00000000 T4 00000058 T3 00000009 T2 00000000 T1 00000010 T0 00000800 A7 00000000 A6 00000001 A5 80026860 A4 ffffffff A3 00000008 A2 80109be8 A1 00000000 A0 0000f304 TP bad000bc GP 80103930 RA 80000f2c SP 80106bb8 MEPC 80000dee Exception type: Environment call from M-mode Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If4ead38266d1c5b3453d5dd5e5f65de5af793f57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2638998 Commit-Queue: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-154-4/+4
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* core/riscv-rv32i: correct inline assembly constraint modifierTzung-Bi Shih2021-01-141-1/+1
| | | | | | | | | | | | | | | | | | | To make compiler translate the inline assembly well, use '&' modifier to tell compiler that the `locked' variable is written before the instruction is finished using the input operands[1]. [1]: https://gcc.gnu.org/onlinedocs/gcc/Modifiers.html#Modifiers BRANCH=none BUG=b:176959740 BUG=b:177287581 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3f6e5741afeaf98bf8f8e736c6d8db58daac6a17 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2623869 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Revert "core/riscv-rv32i: Add exception_panic"Nicolas Boichat2021-01-112-16/+7
| | | | | | | | | | | | | | | | | | This reverts commit b3584dd1ea0b11c269424ab7693cb9609b15e568. We found a more efficient way to trap integer division by zero, so this code is technically not required anymore. BRANCH=none BUG=b:173969773 TEST=make buildall Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I3a89ab17477258c46a701935af121c3a4b0d41b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612227 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Use -fsanitize-undefined-trap-on-errorNicolas Boichat2021-01-112-11/+3
| | | | | | | | | | | | | | | | | | | Let's use -fsanitize-undefined-trap-on-error instead, to trap division by zero. This only adds 2 instructions to each division (a branch and an ebreak). BRANCH=none BUG=b:173969773 TEST=crash divzero crashes asurada TEST=tast run -var servo=localhost:9999 dut9999 crash.ECCrash passes Change-Id: I50d6016d457089ddcb105026656e1bf09bd1df81 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612226 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Enable integer division by zero UBSANNicolas Boichat2020-12-302-0/+12
| | | | | | | | | | | | | | | | | | Allows us to trap divisions by zero. It might be better to add a new compiler flag for this (e.g. -mcheck-zero-division that is only only available on MIPS currently). BRANCH=none BUG=b:173969773 TEST=crash divzero actually crashes the system, failing address available in RA register. Change-Id: Id82e035b16e05ba2970779367dd6dc8d10f4955a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605039 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Add exception_panicNicolas Boichat2020-12-302-7/+16
| | | | | | | | | | | | | | | | | | | software_panic is meant for exceptions that are usually software-driven (stack overflow, etc.). Create a new exception_panic function that can be used for the corner cases where we want to replicate exception behaviour of other cores (e.g. integer division by zero), that we do not want to be disabled by CONFIG_SOFTWARE_PANIC. BRANCH=none BUG=b:173969773 TEST=buildall Change-Id: I2253383e356637a62a401f0e695388e514de330f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2606167 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: Make it possible to enable LTONicolas Boichat2020-12-291-0/+5
| | | | | | | | | | | | | | | This is especially useful to reduce the total code size if we enable division by zero UBSAN. BRANCH=none BUG=b:173969773 TEST=Enable on asurada[_scp], boot Change-Id: I86212a5834e5dd86e75bc3247f4365a6e102c45e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2605037 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it8xxx2: enable ILM0Dino Li2020-12-171-0/+6
| | | | | | | | | | | | | | | | | | This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/flash: workaround of IMMU tag is nds32 onlyDino Li2020-12-171-2/+0
| | | | | | | | | | | | | | This change excluded the workaround from core riscv. BUG=b:111808417 BRANCH=none TEST=On asurada and drawcia, no error while erasing and writing flash of address 0x7e000 ~ 0x7f000 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If6510b181173862684552607d688b3afb046aa2c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563356 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-146-45/+38
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m mpu: support configuring regions with difficult alignmentPeter Marheine2020-12-111-59/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing configuration code assumes that provided addresses are at least as aligned as the requested size, which is not true on NPCX797WC (and likely others) where RAM regions are only 64k-aligned but have larger sizes (like 256k). Use a new greedy approach to configuring the MPU which handles these situations corrently: for any given request take the largest possible chunk from the bottom of the memory region (subject to size and address alignment). Maximize the space by aggressively using MPU subregions- this means that in many well-aligned situations this algorithm selects a larger region than the requested size and enables one subregion, but in more difficult situations it is capable of enabling subregions with more exotic positions. BUG=b:169276765 BRANCH=zork TEST=With a test harness to print out computed configurations, manually verified the correctness of a variety taken from real chip configurations (request first, MPU region(s) indented): 0x20000000 size 0x1000 # stm32f03x 0x20000000 size 0x8000 srd fe 0x20000000 size 0x2000 # stm32f03x 0x20000000 size 0x10000 srd fe 0x20000000 size 0x2800 # stm32l100 0x20000000 size 0x4000 srd e0 0x20000000 size 0x4000 # stm32f412 0x20000000 size 0x20000 srd fe 0x80000 size 0xc000 # it8320 0x80000 size 0x20000 srd f8 0xff200000 size 0xa0000 # ish5p4 0xff200000 size 0x100000 srd e0 0x200b0000 size 0x20000 # npcx797wb 0x20080000 size 0x80000 srd e7 0x10070000 size 0x40000 # npcx797wb 0x10000000 size 0x80000 srd 7f 0x10080000 size 0x80000 srd f8 0x200c0000 size 0x10000 # npcx796f 0x20080000 size 0x80000 srd ef 0x10090000 size 0x30000 # npcx796f 0x10080000 size 0x80000 srd f1 0x10090000 size 0x20 0x10090000 size 0x100 srd fe Further verified MPU configuration with the new algorithm succeeds on Dalboz, and test/mpu.c passes on Dragonclaw. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I71d8e2b37c7e20fc7a39166b90eea0b7f7ebcf43 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2434601 Reviewed-by: Edward Hill <ecgh@chromium.org>
* core/riscv-rv32i: support DRAM cacheTzung-Bi Shih2020-11-191-0/+64
| | | | | | | | | | | | | Allocates memory space for dram.* sections. BRANCH=none BUG=b:156222459 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I0825c9daf06d88929ef3410a14c176099bfa1ace Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531753 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: move essential code to ram_code only if supportsTzung-Bi Shih2020-11-191-1/+3
| | | | | | | | | | | | | | | | | | Commit "it83xx: pull more functions into __ram_code section" (https://crrev.com/c/2535899) breaks Asurada SCP. It moves some essential code to .ram_code section but only IT8XXX2 family includes .ram_code in linker script. Moves the context switch code to ram_code only if it supports. BRANCH=none BUG=none TEST=make BOARD=asurada_scp && make BOARD=asurada Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I8602f7ef0103282feeddbfe1757f7cf7fb5512dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546722 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx: pull more functions into __ram_code sectionDino Li2020-11-182-2/+4
| | | | | | | | | | | | | | | | | | Because we have space in the section, so we pulled more functions into the section. If a function is cached in __ram_code section (static cache), we can save latency of fetching code of the function from flash. (Fetching 64 bytes code from flash takes about 4us latency) BUG=none BRANCH=none TEST=buildall. Asurada and Drawcia are both able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8b413bd577c4e5b73a5c67018d17955da1ed0c55 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2535899 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* nds32/task: return invalid task id if task scheduling is not yet startDino Li2020-11-182-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | The send_to_cr50() uses task_disable_task() to disable console task, and task_disable_task() will also suspend a task if it is the current task (tskid == task_get_current()). But send_to_cr50() is called in main routine (task scheduling is not yet start). If a specified FW image hits condition of "tskid == task_get_current()", EC will start scheduling with unexpected status. (eg. at CL:2540390: current_task=0x80880, tasks=0x877a8, and uint8_t current_task - tasks = 9 ) BUG=b:172460745 BRANCH=none TEST=No WDT loops on drawcia Change-Id: If42ef14a198ab5f99686f8e7212151b2d6b573f5 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2544291 Tested-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Zephyr: add more compliant implementation for irq_(un)lockYuval Peress2020-11-081-2/+2
| | | | | | | | | | | | | | | | | | This change replaces the stubbed irq_(un)lock static functions defined in task.h with new functions that behave more like the Zephyr implementation of irq_(un)lock functions. This should make the migration from interrupt_(dis|en)able to Zephyr more seamless. BRANCH=none BUG=b:172060699 TEST=Added unit tests, make runtests -j, and built for various boards: eve, volteer, arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ia7ad2b8d7d411a11699353bf5d3cc36a261fad14 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511720
* COIL: Rename CONFIG_I2C_PERIPHERALDiana Z2020-11-052-6/+6
| | | | | | | | | | | | | Rename CONFIG_I2C_PERIPHERAL and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I3f148e976f3a4d6a1dc6c58686368c056290d5d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-0212-12/+12
| | | | | | | | | | | | | | | | | Rename atomic_read_clear to atomic_clear to be consistent with the rest of the atomic functions, which return the previous value of the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* atomic: remove deprecated atomic functionsDawid Niedzwiecki2020-10-306-329/+0
| | | | | | | | | | | | | | Remove deprecated_atomic_* functions since only atomic_* are now used. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I6b25cc81aec126662ed779cf0f9309dcb77a754e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505142 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-276-62/+56
| | | | | | | | | | | | | | | | | | | | | | | It is done as a part of porting to Zephyr. Since the implementation of atomic functions is done for all architectures use atomic_* instead of deprecated_atomic_*. Sometimes there was a compilation error "discards 'volatile' qualifier" due to dropping "volatile" in the argument of the functions, thus some pointers casts need to be made. It shouldn't cause any issues, because we are sure about generated asm (store operation will be performed). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949 Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* core/nds32: to avoid race conditiontim2020-10-271-3/+12
| | | | | | | | | | | | | | | | | | | | | After the program to line 628(original program), we have determined that the local variable of waiter is 0 because a task is getting the mutex lock then clearing waiter to 0(line 608). If another task enters mutex lock at this time, mtx->waiters will be written to 1 and go to sleep waiting, but the local variable of waiter is still 0. This will cause latter task which cannot be woke up when previous task leaves the mutex unlock. BUG=none BRANCH=none TEST=create two tasks and respectively access mutex_lock and mutex_unlock. There would not happen that latter task cannot be woke up when previous task leaves the mutex unlock. Change-Id: I566a14c1120716af8e9ac99e183a989274a4e72e Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2438084 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/nds32: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-201-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. Adjust the atomic functions' code to support that. GCC builtin functions are not used, because those functions are not available for nds32. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I9e181d3c64117b30a08179f84c16162ab70b25fc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2444992 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
* core/cortex-m0: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-151-4/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. To support such functionality the new ATOMIC_OP define is introduced. The "memory" clobber is added to the asm statement to inform compiler that memory pointed by the input parameter (a) is changed. This is needed, because atomic_* functions are inline. GCC builtin functions are not used, because those functions are not available for cortex-m0. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I713daf388cb279704ae1b3767bd84b71a255f7cd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2438425 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* core/minute-ia: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-131-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. The current state of ATOMIC_OP macro is not designed to return such value so instead of reworking it or writing new custom asm code just use builtin functions. The __atomic_* builtins support variables with different sizes so use them in *_u8 functions as well. For "and" operation, it compiles to "andb" for u8 and to "andl" for u32. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I498ca3dbb14aea6afc2f7a525c530eede7f31fe2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2448497 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-131-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. Use GCC builtin functions instead of the custom asm code in order be sure there are no bugs and be consistent with other architectures. atomic_read_add/sub work the same as atomic_add/sub. atomic_read_add/sub should be replaced and deleted in the next step - use atomic_* instead of deprecated_atomic_*. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I1f4f4ef26acb9e388da75125a4dd8e2f0dba9fe8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2444995 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/host: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-131-0/+28
| | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. Use __atomic insead of __sync atomic functions as it is a recommended way (https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I4617e2f4c4b9e7021f3df572ba98f1f52bcd8975 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2453253 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/cortex-m: add Zephyr compatible atomic functionsDawid Niedzwiecki2020-10-081-0/+29
| | | | | | | | | | | | | | | | | | | | | | Add atomic functions with prototypes equal to the ones in Zephyr. It is done as a part of porting to Zephyr, the next step is to use in the code atomic_* instead of deprecated_atomic_*. Some atomic functions in Zephyr return a value e.g. atomic_add - it returns the value of the variable before the add operation. The current state of ATOMIC_OP macro is not designed to return such value so instead of reworking it or writing new custom asm code just use builtin functions. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Iccd7a4d674601271f11f88834c8b2db08c537534 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428945 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: rename atomic inc and decDawid Niedzwiecki2020-10-071-4/+4
| | | | | | | | | | | | | | | | | Rename atomic_inc function to deprecated_atomic_read_add and atomic_dec to deprecated_atomic_read_add to be more precise what the functions do. It is done as a part of porting to Zephyr, where atomic_inc increments by 1 and atomic_dec decrements by 1. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ide852ac32ce9027698cb937a06543da689c2e136 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428944 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-0611-34/+34
| | | | | | | | | | | | | | | | | | Change the name of atomic_clear to atomic_clear_bits to make to name more clear - the function clears only selected bits, but the name may suggest that it clears the whole variable. It is done as a part of porting to Zephyr, where atomic_clear zeros the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I7b0b47959c6c54af40f61bca8d9baebaa0375970 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428943 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: support enhanced PSL functions in npcx9CHLin2020-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. In npcx7, the PSL (hibernation) wakeup source only can come from physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer) module is introduced to support wakeup from a configurable timeout. 2. support PSL wakeup from the VCC1_RST pin. This function is disabled by default and enabled (and locked) in the firmware in the npcx9 A1 chip. In the npcx9 A2 chip, this function is enabled (and locked) by booter. 3. Support pulse mode and open drain (if pulse mode is enabled) for PSL_OUT pin. 4. support one PSL general-purpose output pin which is powered by VSBY. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds. make sure the reset cause in the console is "power-on hibernate rtc-alarm" TEST="hibernate"; check EC wakes up from hibernate after pressing VCC1_RST button on the internal test board. Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1 power; check EC can wake up from hibernate with any input event. Test=configure the level of PSL_GPO before hibernation; check the level is kept after entering hibernation. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* minute-ia/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-29/+34
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I7f32eec1f03cccf8ddd3af29ac2821459a99629b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381714 Reviewed-by: Jett Rink <jettrink@chromium.org>
* riscv-rv32i/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-19/+25
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I156225d90ea3c7bc5a09e899afd0935e04d71680 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381713 Reviewed-by: Jett Rink <jettrink@chromium.org>
* nds32/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-19/+25
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ic42ab9e334abf95f8437b41e828abe74d065b9d8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381712 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m0/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-9/+17
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I2a5b474b03a65ce4a5c77cf5f5b671d1d72095f2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381711 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m/panic: Use newly provided functions to access panic dataPatryk Duda2020-10-011-9/+17
| | | | | | | | | | | | | | | This change removes usage of PANIC_DATA_PTR where possible. Now panic data is accessed through functions that performs more checks and in case of writing also moves other data when necessary. BUG=b:165773837, b:162254118 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Id4099d2a205f5e6118e83514dc4b88c980054ea9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2381710 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-2912-91/+154
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* coretex-m: fix __image_size value in linker scriptCaveh Jalali2020-09-251-0/+6
| | | | | | | | | | | | | | | | | | | | | This fixes a regression introduced by chromiun:2325768 that broke software sync and forced recovery mode due to an incorrect EC image size value when CONFIG_CHIP_DATA_IN_INIT_ROM is used. also, __image_size was set twice in the linker script with the latter taking precedence when CONFIG_CHIP_INIT_ROM_REGION is enabled. Made the 1st occurrence conditional to avoid confusion. BUG=none BRANCH=none TEST=EC console "hash" command now reports the correct image size and we no longer end up in recovery due to software sync. Change-Id: Ic0fb405f6918bdfa467be5919eed91eb17ef7c2a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428566 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* it83xx: read_clear_int_mask() read and clear interrupt bit.Dino Li2020-09-243-26/+31
| | | | | | | | | | | | | | | | | | This change pulled the operation of interrupt disable into read_clear_int_mask(). Because riscv core supports instruction csrrc to atomic read and clear bit in CSR register. With this change, we won't need to separate operations of reading and clearing interrupt bit on riscv core. BUG=none BRANCH=none TEST=read_clear_int_mask() is able to disable interrupt and return saved interrupt bit on both nds32 and riscv cores. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: support locating .data section in ROM residentKeith Short2020-09-242-9/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Reorganize the RO and RW images so the .data section remains in flash and is not copied into code RAM by the bootloader. This frees effective flash space for more code in the .text and .rodata sections. The EC initialization is changed to copy the .data section directly from flash into data RAM so the runtime access of objects linked into .data are unchanged. This is controlled with a new config option CONFIG_CHIP_DATA_IN_INIT_ROM. This option is automatically enabled when the board enables the ROM resident section with CONFIG_CHIP_INIT_ROM_REGION and the EC chip supports memory mapped access to flash (CONFIG_MAPPED_STORAGE). On Volteer this change saves 1656 bytes of RW flash space. BUG=none BRANCH=none TEST=make buildall TEST=Run "ectool motionsense lid_angle" on Volteer. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2eff814ad240dfb46bfba400b83d78d1f69a8310 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325768 Reviewed-by: caveh jalali <caveh@chromium.org>
* core/nds32: remove unnecessary conditionDino Li2020-09-154-11/+20
| | | | | | | | | | | | | | | | | In the previous implementation, we added conditions to prevent stack overflow panic or memory get overwritten at first context switch. Actually, we won't hit these two situation if scratchpad size is correct. Let's remove them. BUG=none BRANCH=none TEST=EC boots, and the "runtime" is saved in scratchpad at first context switch. Change-Id: I647e1ebb01dbb8fe24adc9f22b6581bb8f8f97fb Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980097 Reviewed-by: Jett Rink <jettrink@chromium.org>
* riscv-rv32i: Enable FPU extension only if CONFIG_FPU is enabledDino Li2020-08-201-1/+3
| | | | | | | | | | | | | | | | | | | At default, CONFIG_FPU option isn't enabled. But currently, FPU extension is always enabled when building FW image. This will cause problem if hardware doesn't support the extension and floating-point instructions are generated. So we fix it. BUG=none BRANCH=none TEST=Floating-point instructions are used for floating point operation if CONFIG_FPU is enabled. Otherwise, library routines are used. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ifb77bd0cca1158ca7f6637fa9ec025ac8712bbfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227779 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
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