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* riscv-rv32i: Enable FPU extension only if CONFIG_FPU is enabledDino Li2020-08-201-1/+3
| | | | | | | | | | | | | | | | | | | At default, CONFIG_FPU option isn't enabled. But currently, FPU extension is always enabled when building FW image. This will cause problem if hardware doesn't support the extension and floating-point instructions are generated. So we fix it. BUG=none BRANCH=none TEST=Floating-point instructions are used for floating point operation if CONFIG_FPU is enabled. Otherwise, library routines are used. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ifb77bd0cca1158ca7f6637fa9ec025ac8712bbfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227779 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cortex-m: Fix flash size calculation boards without flashKeith Short2020-08-181-25/+25
| | | | | | | | | | | | | | | | | | CL:2334389 broke the make debug output for the kukui_scp and flapjack_scp boards. The actual EC image was not affected. This change also cleans up the #ifdef usage to consolidate assignment of the output sections into one place. BUG=b:164696005 BRANCH=none TEST=make buildall TEST=Run "util/compare_board.sh -b cortex-m" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If69cb492e2aa5f1181e27be24ee66f63cc74ff62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359492 Reviewed-by: caveh jalali <caveh@chromium.org>
* Replace __attribute__((noreturn)) with noreturnTom Hughes2020-08-174-6/+8
| | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-151-4/+13
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* npcx: add support for rom resident sectionsKeith Short2020-08-135-1/+168
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC images are copied in full from flash to RAM. When the code RAM size is smaller than 1/2 the flash size, the EC image size is limited to the code RAM size, leaving unused flash space. Create a new linker section .init_rom used to store data objects that are single use in the previously unused flash area. Data objects can be used at runtime by copying into RAM using the flash_read() function. This change is tied to the NPCX flash layout, with asserts to ensure builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by the chip. CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until the predecessor CL:2325764 is available in CPFE images. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=With debug code, use the _init_rom macro and validate the data can be read using flash_read(). TEST=Using hex editor, verify .init_rom section located at 192K boundary and unused bytes are filled with 0xFF. TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-121-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Revert "task: Fix mutex_lock() assert (reland)"caveh jalali2020-08-071-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8d46141f4d45c65712a9ca7509b7b60128fa4d89. Reason for revert: getting EC boot loop on volteer: (note that you have to flash EC-RO to get this) 20-08-07 00:22:33.520 --- UART initialized after reboot --- 20-08-07 00:22:33.531 [Image: RO, volteer_1.1.9999-4284ce1 @caveh] 20-08-07 00:22:33.531 [Reset cause: reset-pin] 20-08-07 00:22:33.531 [0.005149 KB boot key mask 0] 20-08-07 00:22:33.543 [0.005438 init buttons] 20-08-07 00:22:33.543 [0.005669 VB Main] 20-08-07 00:22:33.543 [0.005872 VB Ping Cr50] 20-08-07 00:22:33.543 [0.007148 hash start 0x00040000 0x0002f61c] 20-08-07 00:22:33.833 [0.300169 hash done e4ddc3d0ffd015db085389d94faa38d3922e42290b6887baa8de3067ce846c13] 20-08-07 00:22:33.833 [0.300289 VB Verifying hash] 20-08-07 00:22:33.833 ��������������������������������EC\0 \0 �������S��O�8Ӓ.B) h����0g΄l[0.317577 VB Received 0xec00] 20-08-07 00:22:33.850 [0.317899 Jumping to image RW] 20-08-07 00:22:33.850 20-08-07 00:22:33.850 ASSERTION FAILURE '!in_interrupt_context() && task_start_called()' in mutex_lock() at core/cortex-m/task.c:868 20-08-07 00:22:33.861 20-08-07 00:22:33.861 === HANDLER EXCEPTION: 00 ====== xPSR: 0000000a === 20-08-07 00:22:33.861 r0 :00000364 r1 :100b6815 r2 :100b72ab r3 :100956bd 20-08-07 00:22:33.873 r4 :dead6663 r5 :00000364 r6 :200c1c20 r7 :00000001 20-08-07 00:22:33.873 r8 :00001388 r9 :100b4108 r10:100b4158 r11:00000013 20-08-07 00:22:33.884 r12:10095811 sp :200c0320 lr :200c1c20 pc :200c14f8 20-08-07 00:22:33.884 20-08-07 00:22:33.884 cfsr = 0, shcsr = 70000, hfsr = 0, dfsr = 0 20-08-07 00:22:33.884 20-08-07 00:22:33.884 =========== Process Stack Contents =========== 20-08-07 00:22:33.889 00000000: 100cfc00 00002a3d 00002751 00002731 20-08-07 00:22:33.901 00000010: 00002741 00002711 000027e1 00002791 20-08-07 00:22:33.901 00000020: 000027a1 000027b1 00002771 000027c1 20-08-07 00:22:33.901 00000030: 00002721 00002781 00002761 000027d1 20-08-07 00:22:33.906 20-08-07 00:22:33.906 Rebooting... 20-08-07 00:22:33.996 20-08-07 00:22:33.996 20-08-07 00:22:33.996 --- UART initialized after reboot --- Original change's description: > task: Fix mutex_lock() assert (reland) > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also assert task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > This was first submitted as CL:2309057, then reverted by CL:2323704 > because it broke jump to RW (b/162302011). Fix this by adding check > for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP, jump to RW > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I070a265a95d2128643b536814e608509d81adbe3 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> Bug: b:160975910 Change-Id: I9e37b1eac7344cddbd756fb45b130d7e0aee661b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341706 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-061-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. This was first submitted as CL:2309057, then reverted by CL:2323704 because it broke jump to RW (b/162302011). Fix this by adding check for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I070a265a95d2128643b536814e608509d81adbe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* linker: change symbol used to track available flashKeith Short2020-08-054-30/+41
| | | | | | | | | | | | | | | | | | | | | | Change the linker symbol used to track available flash from __image_size to __flash_used. __image_size is now only used on the struct image_data header. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=Run compare_build.sh against the following boards: cortex-m: volteer (npcx chipset) cortex-m0: honeybuns (stm32f0 chipset) minute-ia: not changed nds32: waddledee (it83xx) riscv-rv32i: asurada (i8xxx2) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I94f5b4827cc0da1055520685cfeb1fafc0119e1c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2334389 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* linker: Add flash sizes as linker defined labelsKeith Short2020-08-054-0/+44
| | | | | | | | | | | | | | | | | Add linker defined labels for the configured flash sizes. This is only used for image analysis. BUG=none BRANCH=none TEST=make buildall TEST=To see the labels run "nm -n build/<board>/RW/ec.RW.elf | grep __config" Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ib4db8478b19a8d93776c68fa24ee31fb21a50a24 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2325765 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: change usage of dummySam Hurst2020-08-057-9/+9
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* hooks: Introduce chipset resume init and suspend complete hooksWai-Hong Tam2020-07-305-0/+50
| | | | | | | | | | | | | | | | | | | | | These hooks are only enabled through a new CONFIG. The resume init hook will be used to initialize the SPI driver, which goes to sleep on suspend. Require to initialize it first such that it can receive a host resume event, that notifies the normal resume hook. The suspend complete hook is paired with the resume init hook, which reverts the initialization of the SPI driver. BRANCH=None BUG=b:148149387 TEST=make buildall -j TEST=Build successfully on both default off and defining this CONFIG. Change-Id: I615e2bf92c75f83a7b0ab3eded61a1ef241dbdcf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321875
* Revert "task: Fix mutex_lock() assert"Edward Hill2020-07-281-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d53b71c17f7845a591fe4099b53717ec28bf5ccf. Reason for revert: Breaks jump to RW due to assert failing in chip/npcx/flash.c. Reverting while I come up with a better fix. Original change's description: > task: Fix mutex_lock() assert > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also add a check for task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I1a941fa78849a4efe586e66bb4787aa5a2a67732 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2309057 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> Bug: b:160975910 b:160208802 b:162302011 Change-Id: Idb38bfc69892fd34a18b9fdc2b46bf8e086f97dd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2323704 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* core: nds32/riscv-rv32i: fix issue of time in exceptions is negativeDino Li2020-07-242-14/+16
| | | | | | | | | | | | | | | | | | | | If 32-bit counter is overflowed in ISR, the high word of the system time (clksrc_high) can't be updated until return from interrupt. So we will get a negative delta time if the overflow occurs between getting start time and end time. This patch fixes the issue. BUG=b:161768286 BRANCH=none TEST=Making a overflow emulation to see what delta time we will get: s = __hw_clock_source_read() = 0xfffffff0; e = __hw_clock_source_read() = 123; e - s = 139; Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I91e6c4d83de3e074388c1a4fc926b05e791b7b47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311997 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* task: Fix mutex_lock() assertEdward Hill2020-07-241-1/+14
| | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also add a check for task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. BUG=b:160975910 BRANCH=none TEST=boot AP Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I1a941fa78849a4efe586e66bb4787aa5a2a67732 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2309057 Reviewed-by: Raul E Rangel <rrangel@chromium.org>
* ec: change usage of "sane" per inclusive languagePaul Fagerburg2020-07-227-7/+7
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the terms "sane", "sanity check", and similar with inclusive/non-stigmatizing alternatives. BUG=b:161832469 BRANCH=None TEST=`make buildall -j` succeeds. `grep -Eir "sane|sanity" .` shows results only in third-party code or documentation. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I29e78ab27f84f17b1ded75cfa10868fa4e5ae88c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311169 Reviewed-by: Jett Rink <jettrink@chromium.org>
* riscv-rv32i: correct printf formatEric Yilun Lin2020-07-221-7/+7
| | | | | | | | | | | | | | unsigned integer should use '%u' rather than '%d' BUG=b:161768286 TEST=make BOARD=asurada BRANCH=none Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Change-Id: I84a5419ce813a4378657c4fbfeba967262faef3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2310220 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* host: Fix task_wait_event() to return TASK_EVENT_TIMEREdward Hill2020-07-131-0/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make -j runhosttests Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ibd753b2eec5d81438dc0884b1a0c12c4c319afe2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294164 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* core/riscv-rv32i: add atomic_inc and atomic_decTzung-Bi Shih2020-07-031-6/+11
| | | | | | | | | | | | BRANCH=none BUG=b:146213943 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3d87c9906df1b631fa3733eeae92d356ec287611 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2275710 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: set volatile for in_interruptTzung-Bi Shih2020-06-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | Given that: - in_interrupt is modified in interrupt context. - Some normal task context call in_interrupt_context() and in_soft_interrupt_context(). To safely share the variable, sets it to volatile. BRANCH=none BUG=b:146213943 BUG=b:157521370 BUG=b:156223049 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ibd1bf9556d8376f6f6389a17cc792a6f21227d4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2237495 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-066-0/+24
| | | | | | | | | | | | | | | | | | | A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are called from the chipset task, while the system has already shut down and all the suspend rails are already off. It will be used for executing pending EC reboot at the chipset shutdown. The EC reboot should be executed when the chipset is completely off. BRANCH=None BUG=b:156981868 TEST=Built all boards. Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* core/riscv-rv32i: remove return valuesTzung-Bi Shih2020-06-042-12/+6
| | | | | | | | | | | | | | | | | | Return values of chip_enable_irq(), chip_disable_irq(), and chip_clear_pending_irq() are not using. Removes them. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic7e3e80483f76f35bfe7781ddea48515ab8e3361 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227778 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: add error handling for chip_get_ec_int()Tzung-Bi Shih2020-06-042-10/+21
| | | | | | | | | | | | | | | | | | chip_get_ec_int() returns -1 if it cannot find the corresponding interrupt source. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I5021ed80f50a99b15d9b9a90a9181077f63bd4be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227777 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: add in_soft_interrupt_context()Tzung-Bi Shih2020-06-031-0/+6
| | | | | | | | | | | | | | BRANCH=none BUG=b:146213943 BUG=b:156218912 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Change-Id: If8df1fb768ea9c83f025d8bd17010481389d7aa1 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217596 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* test: Pass commandline arguments to run_testTom Hughes2020-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | run_test is called by the "runtest" console command. Console commands can take arguments, so pass along the arguments to run_test to allow parameters to be passed to run_test. The following command was used for automatic replacement: git grep --name-only 'void run_test(void)' |\ xargs sed -i 's#void run_test(void)#void run_test(int argc, char **argv)##' BRANCH=none BUG=b:155897971 TEST=make buildall -j TEST=Build and flash flash_write_protect test > runtest 1 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib20b955d5ec6b98f525c94c24aadefd7a6a320a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2209418 Reviewed-by: Yicheng Li <yichengli@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* test: Add on-device test for calculating MPU regions for RWYicheng Li2020-05-303-18/+36
| | | | | | | | | | | | | | | | MPU logic needs to represent RW with no more than 2 MPU regions when locking RW. Add on-device unit test for this calculation. BRANCH=none BUG=b:155410753 TEST=make -j BOARD=bloonchipper TEST=make -j BOARD=nucleo-f412zg test-mpu Then flash the test binary to nucleo board runtest on device ==> Pass Change-Id: Idc746efa9419d31cdae9c6fccc499c92160ac593 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2218595
* cortex-m: Use MPU REGION_CODE_RAM to lock rollback if neededYicheng Li2020-05-291-1/+1
| | | | | | | | | | | | | | | On chips with only 8 MPUs, we need to lock the rollback with unused MPU regions. Since REGION_STORAGE2 may be used to lock RW, use REGION_CODE_RAM instead. BRANCH=none BUG=b:155410753 TEST=make -j buildall Change-Id: Iec0f33b668474ed539809a319bf94d11cb52f64a Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2219578 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* cortex-m: Lock RW flash using aligned MPU regionsYicheng Li2020-05-291-5/+27
| | | | | | | | | | | | | | | | | | | | | | | | On Cortex-M3, Cortex-M4, and Cortex-M7, the base address used for an MPU region must be aligned to the size of the region: https://developer.arm.com/docs/dui0553/a/cortex-m4-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0552/a/cortex-m3-peripherals/optional-memory-protection-unit/mpu-region-base-address-register https://developer.arm.com/docs/dui0646/a/cortex-m7-peripherals/optional-memory-protection-unit/mpu-region-base-address-register#BABDAHJG Try to represent RW flash using aligned MPU regions before configuring MPU. Otherwise configuring MPU will fail. BRANCH=none BUG=b:155410753 TEST=triggered mpu_lock_rw_flash() on bloonchipper and dartmonkey and checked that configuring MPU succeeded. TEST=on bloonchipper and dartmonkey, verified that the MPU configurations make sense by adding logging. Change-Id: Ib460354ea60e96d7b6ac4a4c12730b0db7c6aaac Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213132 Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: remove get_sw_int()Tzung-Bi Shih2020-05-292-18/+2
| | | | | | | | | | | | | | | | Inline the function definition. BRANCH=none BUG=b:146213943 BUG=b:157521370 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Icfde6399b2dd560924128f9e7fbeb54efaa9c14c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2217595 Reviewed-by: Jett Rink <jettrink@chromium.org>
* cortex-m: Init the MPU to check for correct operationAndrew McRae2020-05-272-2/+25
| | | | | | | | | | | | | | | | Disable all a MPU regions using the smallest supported size. BUG=chromium:1085868 TEST=Boot successfully on Puff TEST=Boot successfully on Volteer BRANCH=none Change-Id: Ie6924c3d9691ba6f4b218c9897b4e42b35b12bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212010 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* test: Add on-device MPU unit testTom Hughes2020-05-221-0/+3
| | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:151105339, b:155229277 TEST=make BOARD=bloonchipper test-mpu -j && \ ./util/flash_jlink.py --board bloonchipper \ --image ./build/bloonchipper/mpu/mpu.bin => On console: "runtest" => All tests pass, except last which correctly panics: Data access violation, mfar = 20000000 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1c759f50da5075b1e9027cdba253d8c06843be5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202852 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* core/cortex-m: create private MPU header for use by unit testsTom Hughes2020-05-222-5/+29
| | | | | | | | | | | | | | | | | Expose definitions that we want to use in unit tests, but are internal details that should not be used by other EC code using the rollback functionality. BRANCH=none BUG=b:155229277, b:156501835 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iab14a0cf17d4a986f1a1d9b77d27957976962078 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202851 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* cortex-m/mpu: Check alignment when applying MPU configTom Hughes2020-05-221-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibba15e5319832ba0e0efde913275d618e249bc44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202850 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cortex-m: Always enable MPU in mpu_pre_initTom Hughes2020-05-221-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPU was only being enabled when CONFIG_ARMV7_CACHE and CONFIG_CHIP_UNCACHED_REGION were enabled; these are enabled for the STM32H743 (dartmonkey), but not the STM32F412 (bloonchipper). BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I7bca3864205bd1dd6797732aa903bc3bc325ac6f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200201 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cortex-m: Configure rollback MPU based on number of regionsTom Hughes2020-05-221-4/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rollback MPU support was initially added for the Cortex-M7, which can support 16 MPU regions. REGION_ROLLBACK was defined as MPU region 10. For the Cortex-M4, there are at most 8 regions, so we have to repurpose some of the existing (unused) regions. BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 8040000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" test on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I748b7ea0654dee01d27bb560e82491665025d1ef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200200 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* cortex-m: Clean up MPU logicTom Hughes2020-05-222-18/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add error checking for failures and use IS_ENABLED combined with helper functions for readability. BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Memory is successfully read => FAIL TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0f8d149c8c5c568241457a6779079c65eb38ce32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200199 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* core/riscv-rv32i: define dummy implementation for CPU_INTTzung-Bi Shih2020-05-191-0/+5
| | | | | | | | | | | | | | | Defines dummy implementation for CPU_INT for non-IT8XXX2 chips. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I3c9587133d110fed95042da6c75f1e64e1f87fda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2124436 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: add default __idle()Tzung-Bi Shih2020-05-191-0/+4
| | | | | | | | | | | | | | | Adds default __idle() implementation. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ie4711b568f8d1880eb933027c10fc43672871d23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178701 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: clean up header inclusionsTzung-Bi Shih2020-05-193-10/+4
| | | | | | | | | | | | | | | | | | | | Removes unneeded header inclusions. Especially chip-specific ones: - hwtimer_chip.h - intc.h - registers.h Other rv32i-based boards do not need to provide the headers. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6d158568fb6b626d96215bbd263b66cd8b7ebd57 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178700 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: do not expose get_sw_int()Tzung-Bi Shih2020-05-194-12/+2
| | | | | | | | | | | | | | | Do not expose get_sw_int(). BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I9a5bbeec152780b54b4dd6ce07f2390633c64366 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2178699 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: move interrupt details to IT83XX specificTzung-Bi Shih2020-05-194-40/+26
| | | | | | | | | | | | | | | | Getting source interrupt number is chip specific. Moves the details to chip implementation. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ia72acf8ec9c09cb329f8d7c92d22476512ffa669 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114951 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* core/riscv-rv32i: guard more IT83XX chip specific itemsTzung-Bi Shih2020-05-191-10/+7
| | | | | | | | | | | | | | | | | | | | Guards IT83XX chip specific: - E-flash signature. - BRAM (Battery-backed SRAM). Moves IT83XX_GCTRL_EIDSR to IT83XX chip specific. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I05ea628c6b745136043b9505c98204381bd7a0ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114950 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
* core/riscv-rv32i: separate CHIP_FAMILY_IT8XXX2 specific memory regionsTzung-Bi Shih2020-05-191-9/+55
| | | | | | | | | | | | | | | Separates CHIP_FAMILY_IT8XXX2 specific memory regions. BRANCH=none BUG=b:151897847 TEST=1. make BOARD=asurada 2. flash_ec --board=asurada --image build/asurada/ec.bin 3. (EC console)> version Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I0b337b366e428667ef56cf0a0060c22fe6d2046f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109443 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* cortex-m: provide a function to set IRQ priorityPeter Marheine2020-05-194-18/+32
| | | | | | | | | | | | | | | | On Puff we need to increase some IRQ priorities to meet strict timing requirements. To support that, provide a function encapsulating the bit manipulations to adjust the priority of a single IRQ and update task.c to take advantage of it. BUG=None BRANCH=None TEST=Still builds. Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I9534f5733db48b9650a55f30e5209918a5eb24b1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192456 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* ish: enable IPAPG for ish 5.4 on tgl rvp platformLeifu Zhao2020-05-151-0/+7
| | | | | | | | | | | | | | | | | Enable ip accessible power gating for ish 5.4 on tgl rvp platform. BUG=b:154891699 BRANCH=none TEST=ISH can successfully enter into IPAPG on tgl rvp. Change-Id: Iee30124a0928389f4c75dffff065fab7a5a2d970 Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2164091 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* risc-v: add comments about not needing 16-byte stack frame alignmentDino Li2020-05-133-7/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we are not actually executing on a stack frame that is not 16-byte aligned, we are following the guidance (linked below). Add comments for future developers to explain why. Also, saving system stack pointer in the switch to function since the isr function takes special care to not over write the stack pointer when we are already using the system stack. According to documentation, the stack frame should be 128-bit aligned upon entering function boundaries. "In the standard RISC-V calling convention, the stack pointer sp is always 16-byte aligned" from https://riscv.org/specifications/isa-spec-pdf/ "The stack grows downwards (towards lower addresses) and the stack pointer shall be aligned to a 128-bit boundary upon procedure entry" from https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md See also documentation issues discussing this https://github.com/riscv/riscv-elf-psabi-doc/issues/21 BRANCH=none BUG=none TEST=ITE RISC-V FPU implementation still works Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I3460e6ee2b68c7793c72517e7d2d9bc645aaea65 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2173119 Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/cortex-m[0]: Move core functions assembly files to third_partyNicolas Boichat2020-03-256-765/+6
| | | | | | | | | | | | | | | | The code originally comes from libaeabi-cortexm0. It is unclear which exact git commit the code comes from, but since we have used it without issue for 5 years, it is reliable, and a refresh is probably not required at this stage. BRANCH=none BUG=chromium:884905 TEST=make buildall -j, which also include basic tests. Change-Id: I910c1c4e6a46b2f0fe8b7a429f1b6f0f50c2dc21 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1599762 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core/cortex-m0/curve25519: Move code to third_party folderNicolas Boichat2020-03-257-3240/+1
| | | | | | | | | | | | | | Also, add LICENSE file (some files are under CC0, some are public domain), and METADATA file. BRANCH=none BUG=chromium:884905 TEST=make buildall -j, which also include basic tests. Change-Id: Ib3a7eb9245a0634c4052064c3e36cbe2ddafbcb9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1599761 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-211-0/+15
| | | | | | | | | | | | | | | | | | | | | | | IT81302 (144-pins package) and IT81202 (128-pins package) chips belong to it8xxx2 family. So we apply the same chip options of it83202bx (except ADC pin order config option) and setup the correct flash size, ram size, and ram base. With this change, we are able to build FW image with IT81202 or IT81302 chip variant. BUG=none BRANCH=none TEST=EC boots and test console commands (version, sysinfo, sysjump, flasherase, flashwrite, and flashread) on IT81202 EVB. Hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-192-50/+34
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
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