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* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* atlas: boost VBUS by 2%Caveh Jalali2019-02-231-0/+1
| | | | | | | | | | | | | | | | | this increases the voltage on PP5000_A by 2% to improve our margin on VBUS. BUG=b:123666005 BRANCH=none TEST=verified setting is preserved across S0ix transition, farzam verified voltages. Change-Id: I82809521543b01dc4ec93afa11aff482a1b44116 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1480944 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: enable active discharge on all railsCaveh Jalali2018-12-181-0/+2
| | | | | | | | | | | | | | | | this enables active discharge on all 12 power rails controlled by the ROHM ROP PMIC. BUG=b:120619543 BRANCH=none TEST=discharge behavior verified by sajedfarzam@ Change-Id: I842dbdcc1eab596230e12130dca272a1f449e268 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1371226 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* atlas: clean up ROP PMIC registersCaveh Jalali2018-11-151-0/+6
| | | | | | | | | | | | | | | | | this replaces some ROP PMIC register magic numbers with their actual names. corrected a few comments about the bits we're writing into these registers along the way. BUG=b:75070158 BRANCH=none TEST=boots on atlas Change-Id: If3be6b4c1d550d7e0770450e9f713282835656b5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1278096 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bd99992: add some more register definitionsCaveh Jalali2018-08-241-0/+6
| | | | | | | | | | | | | | | | | this adds definitions for some additional PMIC registers we're using in our codebase. BUG=b:112732855 BRANCH=none TEST=flashed atlas with new EC build Change-Id: Ibad7b11b3770f00c925c2d8fc3b24109147aa643 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1187899 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* bd99992: add top level header file for PMICCaveh Jalali2018-06-181-0/+16
this introduces a top-level header file for the bd99992 PMIC.the temp sensor portion of this chip already has an established header file, so we can just include it. at this point, we only need one new register definition - the SDWNCTRL (shutdown control) register. BUG=b:110237370 BRANCH=none TEST=it compiles Change-Id: I324df08ed37d6d6d85520e1217135657b18a23a0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096484 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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