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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-566/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* nx20p348x: Check device status reg for sink modeCaveh Jalali2021-08-171-3/+8
| | | | | | | | | | | | | | | | | | | | | | | This fixes an issue where we sometimes time out waiting for the HVSNK_STS bit to get set after enabling sink mode using the EN_SINK GPIO. Checking for HV_SNK mode in the device status register is more robust as it appears to reflect the state of the EN_SINK pin as expected. I'm still not sure why the HVSNK_STS bit isn't set as expected sometimes. I suspect that it only gets set when there is actual voltage presented by the connected device. BRANCH=none BUG=b:194833460 TEST=with additional debug code, verified that we detect HV_SNK mode even when HV sink switch is off.N Change-Id: Ifa5b9ebaedfc03755306ecb4e3e6e1fa654418d0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058079 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* nx20p348x: Fix DB_EXIT flag handlingCaveh Jalali2021-07-281-1/+1
| | | | | | | | | | | | | | | | This fixes a typo where the CTRL_DB_EXIT was being set on the wrong variable. this appears to date back to the very first commit of this driver with chromium:966926. BRANCH=none BUG=b:74206647 TEST=buildall passes Change-Id: I2c389419c09b0bed1e341dcd6ae6d187a698efcd Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058078 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* ppc/nx20p348x: Initialize device control regCaveh Jalali2021-07-221-0/+5
| | | | | | | | | | | | | | | | This initializes the Device Control Register (0x0b) to its power-on reset value. This chip is not connected to the system reset signal, so we need to explicitly set registers to their power-on reset value so we start from the same configuration when we reboot as we do on system power on. BRANCH=none BUG=b:193211352 TEST=charging from another chromebook is reliable now Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I82ce3fd624091b89668a682cb8748af171552d72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044412
* ppc/nx20p348x: Disable VBUS discharge in sink modeCaveh Jalali2021-07-221-4/+26
| | | | | | | | | | | | | | | | | This explicitly disables VBUS discharge when entering sink mode. According to the vendor, keeping VBUS discharge enabled can cause some noise and that explains some of the instability we had observed when charging from another chromebook and 5V3A charger. BRANCH=none BUG=b:193211352 TEST=charging from another chromebook is reliable now Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I117dd3f7f9efddce00f903c2b290fa85c6052c5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044411 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* ppc/nx20p348x: Improve nx20p3483 supportstabilize-14093.B-mainCaveh Jalali2021-07-151-39/+98
| | | | | | | | | | | | | | | | | | | | This improves support for the nx20p3483 PPC. The original driver supports both the nx20p3481 as well as nx20p3483, but did not capture some of the differences. VBUS source and sink control has been improved as that is one of the main functional differences between these chips. The nx20p3481 controls these using a switch control register while the nx20p3483 uses external signals from the TCPC. BRANCH=none BUG=b:192370665 TEST=delbin can charge reliably from brya USB3 DB Change-Id: Ic7f90a92f1ead50673157a0255021c49d70e8a80 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3003965 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* NX20P348x: Only check sink bit for sink_enable errorDiana Z2021-05-071-1/+1
| | | | | | | | | | | | | | | | | | | When a port is sourcing (ex. to a dongle), running sink disable on the port will currently return failure because the 5VSRC bit is set. However, sinking has been successfully disabled. Reflect this in the error return by only checking the specific sinking bit in the status register. BRANCH=None BUG=b:187220141 TEST=on guybrush, plug and unplug AC on C0 with a dongle on C1. Verify no failures to disable sinking are present. Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I529d33b41dc4bc55f7c647742c70832a125fd367 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2877866 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* tcpm: Move tcpm.h into an include directorySimon Glass2020-12-221-1/+1
| | | | | | | | | | | | | | | | | | This header file is used from quite a few files, relying on the EC build system to find includes in the driver/tcpm directory. For Zephyr we don't want to add that as an include. It makes more sense for header files to be in an include directory, so move it and fix up the users. BUG=b:175434113 BRANCH=none TEST=build Zephyr and ECOS on volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985 Reviewed-by: Keith Short <keithshort@chromium.org>
* driver: ppc: Drop paths from driver/ppc filesSimon Glass2020-12-181-1/+1
| | | | | | | | | | | | | | | These paths don't seem to be necessary and don't currently work with Zephyr. Drop them. BUG=b:175434113 BRANCH=none TEST=build zephyr for volteer emerge-volteer -q chromeos-ec Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I482a4a701265631439e3302c4a360e4cb5dba051 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2595220 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-021-1/+1
| | | | | | | | | | | | | | | | | Rename atomic_read_clear to atomic_clear to be consistent with the rest of the atomic functions, which return the previous value of the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | | | | It is done as a part of porting to Zephyr. Since the implementation of atomic functions is done for all architectures use atomic_* instead of deprecated_atomic_*. Sometimes there was a compilation error "discards 'volatile' qualifier" due to dropping "volatile" in the argument of the functions, thus some pointers casts need to be made. It shouldn't cause any issues, because we are sure about generated asm (store operation will be performed). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949 Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-291-2/+2
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc: string de-duplicationKeith Short2020-07-021-5/+5
| | | | | | | | | | | | | | | De-duplicate strings in PPC drivers. Saves 312 bytes on Volteer. Average flash increase of 211 bytes. BUG=b:158572770 BRANCH=none TEST=make buildall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I5ca5c935f974b04216ce4d90e6f6d6b9103e8b75 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2278586 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* nx20p3483: vbus_source_enable failure correctionDenis Brockus2020-02-121-30/+32
| | | | | | | | | | | | | | The nx20p3483 can not use the switch status register because TCPCI was used to enable the switch control. BUG=none BRANCH=none TEST=verify on TCPMv2 that USB3.1 gen 2 functions Change-Id: I5681996640568d74b51fdfc2d5dac20a97e4908a Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051010 Reviewed-by: Edward Hill <ecgh@chromium.org>
* Add a board specific helper to return USB PD port countKarthikeyan Ramasubramanian2019-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Certain SKUs of certain boards have less number of USB PD ports than configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable board specific helper to return the number of USB PD ports. This helps to avoid initiating a PD firmware update in SKUs where there are less number of USB PD ports. Also update charge manager to ensure that absent/ invalid PD ports are skipped during port initialization and management. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-011-3/+3
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ppc: driver changes for FRSDenis Brockus2019-10-081-1/+1
| | | | | | | | | | | | BUG=b:138599955 BRANCH=none TEST=make buildall -j Change-Id: I84f54f4bef9f38bc194e2a45802fb6fcf335e643 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1834023 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc: initialize vbus current limit on initJett Rink2019-08-131-0/+9
| | | | | | | | | | | | | | | The nx20p348 should also set the initial current limit during its initialization. BRANCH=octopus BUG=b:139110010,b:139201733 TEST=with CL stack, phaser limits both ports to 1.5A Change-Id: I876b32434bd37bf410d546a3d27f0f7ba949d3ea Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1749945 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-4/+4
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* driver/ppc/nx20p348.c: Handle overcurrent eventKarthikeyan Ramasubramanian2019-01-171-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the overcurrent event is logged but not handled. Report the overcurrent event to the USB PD framework which in turn will handle the overcurrent event further. BUG=b:115475862 BRANCH=octopus TEST=Boot to ChromeOS in grabbiter. No overcurrent events reported when the sink is drawing <= 3.20 A. Overcurrent events are reported when the sink is drawing > 3.25 A. After 3 reports, the port is latched off and power delivery is stopped. The port is re-enabled only after the sink is disconnected. Also when the sink is drawing current at 3.24 A, there is one report of overcurrent. The port gets disabled in response to that event. But the port is re-enabled after 1 second since overcurrent event is reported only once. After the port is re-enabled, the sink is able to draw the set current. When the overcurrent event is reported, I can see in the kernel logs that the overcurrent condition is detected by the kernel. EC Logs: [3391.984462 C1: PPC detected Vbus overcurrent!] [3391.984953 C1: overcurrent!] [3392.044935 C1: PPC detected Vbus overcurrent!] [3392.045425 C1: overcurrent!] [3392.061404 C1: PPC detected Vbus overcurrent!] [3392.061894 C1: overcurrent!] [3392.062142 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.077226 C1: PPC detected Vbus overcurrent!] [3392.077532 C1: overcurrent!] [3392.077891 C1: OC event limit reached! Source path disabled until physical disconnect.] [3392.092660 C1: PPC detected Vbus overcurrent!] [3392.092966 C1: overcurrent!] [3392.093213 C1: OC event limit reached! Source path disabled until physical disconnect.] Kernel Logs: [ 3356.560456] usb usb2-port1: over-current condition [ 3356.768434] usb usb2-port2: over-current condition [ 3356.976446] usb usb2-port4: over-current condition [ 3357.184441] usb usb2-port5: over-current condition [ 3357.392445] usb usb2-port6: over-current condition Change-Id: I0af69a132fdd1dd5bab4d530c3b060b2a5aea501 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1412448 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc/nx20: add more fault condition printsJett Rink2018-11-161-2/+11
| | | | | | | | | | | | | | When the PPC detects a fault condition such as a short or reverse current, we should print something to the EC console. BRANCH=none BUG=b:115307099 TEST=build. Couldn't get this to trip on demand though. Change-Id: Ib5298074b08a7d7d0d278258822fb7edf562c7aa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1334527 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Octopus: Vbus gone from USB-C port after cold reboot with USB-A driveDiana Z2018-10-251-8/+13
| | | | | | | | | | | | | | | | | | | | | When Vbus turns on while we're in the process of running nx20p348x_vbus_source_enable(), a sink can incorrectly be detected as a charger. This change moves the initialization of the flag indicating we're attempting to source Vbus, and will restore the previous flag state on failure. BRANCH=None BUG=b:117616479 TEST=on yorp, cold booted with USB key and saw it was not detected as a charger on both ports, cold booted with actual charger to verify it was correctly detected on both ports Change-Id: Ie8de18f4b4cd335118d5d44e1476b0ececbcc029 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1298400 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc: Add support for nx20p3481Scott Collyer2018-09-131-10/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL is an incremental change to the nx20p348x driver to add support for the nx20p3481 ppc. Sink/source modes are controlled via the switch control register instead of gpio signals. Another difference is that the values of mode in register 0x1 are slightly different between the 3481 and 3483. The 3481 needs to use the switch status register to verify whether it's in sink or source mode. This register is now checked for both the 3483 and 3481. A delay is required for the switch status register to reflect the control setting just applied. In addition, the nx20p3481 supports Fast Role Swap (FRS). For FRS, only the detection is supported, and it's assumed that it's caused by the removal of an external charger, not an actual FRS event. BUG=b:111281797 BRANCH=none TEST=Verified on DragonEgg that port acts correctly as a sink. Have not been able to verify source operation. Change-Id: I2fb4200a5d9c3ce460e9b913a5b09441e458bb7e Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178995 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ppc: nx20p3483: Rename driver to nx20p348x to support NX20P3481Scott Collyer2018-08-161-0/+368
This CL doesn't change any functionality, but renames the driver from 3483 to 348x. The motivation for this is that we need to support the NX20P3481 PPC as well. Those chips use the same registers, but the 3481 adds FRS support and sink/source control is done via I2C writes instead of gpio controls. Because the chips are slighlty different the config option CONFIG_USBC_PPC_NX20P3483 needs to remain. BUG=b:111281797 BRANCH=none TEST=make -j buildall Change-Id: Ie1085140eb2ef23c0b6e1a79a6f2d7f823326c6d Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1176382 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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