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* TUSB544: Set TUSB544 always to DP Alt mode sourceSue Chen2020-09-291-4/+2
| | | | | | | | | | | | | | | | | | Since all chromebooks are DP SRC, set TUSB544 always at DP Alt mode source (set TUSB544_DIR_SEL_USB_DP_SRC to register TUSB544_REG_GENERAL6). BUG=b:169303733 BRANCH=zork TEST=Plug in typeC monitor which can provide 20V power and make sure it can display while boot to S0 on Ezkinil. Change-Id: I893f7f0ca98ede6ffd678c1118212cad9184d2ba Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2431313 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* bb_retimer: Bypass safe mode configuration in retimermadhusudanarao amara2020-09-231-1/+15
| | | | | | | | | | | | | | | | | BUG=b:161327513 BRANCH=none TEST=Type-C dock multiple hot plug enumerated successfully as SS device. TBT dock enumeration is successful. USB4 dock enumeration is successful. DP Type-C cable plug-in worked fine. Signed-off-by: madhusudanarao amara <madhusudanarao.amara@intel.corp-partner.google.com> Change-Id: Ie4a48dbdfc6904408f11d19b77b5afecf88d4fbe Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324812 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* bb retimer: Use mutex to lock the access to shared NVMVijay Hiremath2020-08-252-12/+15
| | | | | | | | | | | | | | | | | | | If the BB retimer has a shared NVM we need 40ms delay after releasing the RESET line to synchronize, load and initialize both the retimers. On a non-shared NVM we need 20ms delay to load and initialize. In order to synchronize, instead of 40ms delay this CL uses a MUTEX to lock the access of another retimer by not releasing the RESET line until the first retimer completes initialization. BUG=b:165895649 BRANCH=none TEST=Tested on volteer(non shared NVM), tglrvpu_ite (shared NVM) Retimer is able to initialize (DP, USB, TBT, USB4 are detected) Change-Id: I709377c2e6401faa26871289143d71665ee516d1 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2368223 Reviewed-by: Keith Short <keithshort@chromium.org>
* pi3hdx1204: Print error if enable failsEdward Hill2020-08-221-3/+9
| | | | | | | | | | | | BUG=none BRANCH=none TEST=none Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I33b574d42008330b58ae21d5bfbfc6fc73d50271 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2367313 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Ezkinil: Fix HDMI retimer suspend / resumeEdward Hill2020-08-221-0/+3
| | | | | | | | | | | | BUG=none BRANCH=none TEST=none Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I9eac47383695156ca0d222eb75f75492065720b7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2364112 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* BB retimer: Remove FORCE_PWR GPIO from EC driverVijay Hiremath2020-08-192-6/+14
| | | | | | | | | | | | | | | | | | FORCE_PWR GPIO is used for keeping the BB retimer in active state during f/w updating. On TGLRVP, control to enable the FORCE_PWR GPIO was given to EC to support the I2C based F/W updating. I2C based f/w updating is deprecated and the LSx interface is POR hence the FORCE_PWR GPIO control is given to AP now. Thus, removing the FORCE_PWR GPIO from EC driver. BUG=b:165214747 BRANCH=none TEST=make buildall -j Change-Id: If9bb7199a68c93f704f698552e5594a58bd68f7c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363334 Reviewed-by: Ayushee Shah <ayushee.shah@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Set USB3 speed only when USB mode is enabledAyushee2020-07-311-8/+9
| | | | | | | | | | | | | | | This commit sets USB3 speed (Bit 6) only if the mux state is set to USB_PD_MUX_USB_ENABLED BUG=b:152544514 BRANCH=None TEST=Abe to clear bit 6 when DP dock enters in Safe mode. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I1955e22fccb1f86d38f063f614f789d67394de5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2329152 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* retimer/tusb544: set the HPD pin for DP/Dock modeDivagar Mohandass2020-07-181-3/+7
| | | | | | | | | | | | | | | DP lanes are getting disabled if the HPD pin are not set. Drive the HPD_IN pin in USB type-c DP/Dock mode and clear it in the no MUX mode. BRANCH=None BUG=b:160572502 TEST=Check DP/HDMI display out on Waddledee USB type-c sub board Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com> Change-Id: Ie5a467572a88471155fe84e1054ffe64de5f7964 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2304239 Reviewed-by: Diana Z <dzigterman@chromium.org>
* zork: Use CBI only and remove retimer probe codeDenis Brockus2020-07-174-35/+0
| | | | | | | | | | | | | | | | | | | Before CBI was being used, zork used I2C probing to detect basic hardware configuration. Now that CBI is supporting FW_CONFIG, this is being removed. BUG=b:151232257 BRANCH=none TEST=verify zork still boots with valid configuration Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: I267d99f8f3894aff2f6301df167c470db373509e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2304380 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org> Auto-Submit: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* bb_retimer: add power up timingKeith Short2020-07-011-0/+14
| | | | | | | | | | | | | | | | | Ensure the Burnside Bridge is held in reset when the AP is off and add a delay to reset de-assertion to meet Burnside Bridge requirements. BUG=b:159743964 BRANCH=none TEST=make buildall TEST=Verify BB initialization is skipped when the AP is off (verified with extra debug) TEST=Verify operation of USB, DP, and USB4 devices on Burnside bridge. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I4a4f05aaf84bf93b3c3032998bc811591c8fbf35 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2271697 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* usb_pd: Remove pd_cable dependent Thunderbolt code from common codeAyushee2020-06-261-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. Separated the common functions needed to check for port/cable's Thunderbolt mode compatibility back into TCPMv1. 2. Refactored the common Thunderbolt mode functions using pd_cable structure for mode information by adding a. Generic function that returns the Discover Mode response of specified SVID. b. Thunderbolt specific functiion that returns Discover Mode response of Intel SVID. 3. Removed the redundant pd_cable structure from DRP state machine policy engine. BUG=b:158294748 b:150611251 BRANCH=None TEST=1. Able to enter into Thunderbolt mode on TCPMv1 Change-Id: I30c8f1a007228408e08520502db00601ca3a2521 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2249020 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* usb_pd: TBT: Refactor limiting the cable speedAyushee2020-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | Refactored 'get_tbt_cable_speed()' to return thunderbolt-compatible speed as per the speed supported by DUT's port or cable speed whichever is lowest. Also removed 'usb_pd_limit_cable_speed()' to retain cables's actual VDO response. BUG=b:157671582 BRANCH=none TEST=Able to limit thunderbolt cable speed, if the cable speed is higher than the speed supported by DUT's port. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I77d3efddb425daa7bd12e9ed21be7088074285bb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227088 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Add 'vPro_Dock_Detect/DP_Overdrive' bitAyushee2020-06-032-0/+12
| | | | | | | | | | | | | | | | | For DFP, if SOP discover SVID supports Thunderbolt-Compat mode then, vPro_Dock_Detect/DP_Overdrive is set according to discover mode SOP response. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I7a53396725052a4dfa12e934919c2e1d601c8949 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2153825 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* BB retimer: Correct setting USB4 cable speedAyushee2020-05-292-33/+37
| | | | | | | | | | | | | | | | For DFP, TBT/USB4_cable_speed_support is set according to a. Discover mode SOP' response for Thunderbolt-compat mode and b. Discover ID SOP' response for USB4 mode. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Ic031489878dab701177936ea8e2f50d434dba25b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2152287 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Set 'active/passive' bit for USB modeAyushee2020-05-271-3/+4
| | | | | | | | | | | | | | | | | For DFP, if the mux state is USB/DP/Thunderbolt-comp/USB4 Active/Passive bit should be set according to the Discover mode SOP' response. Ref: Burnside Bridge spec Table 13: Connection state register. BUG=b:152544514 BRANCH=None TEST=Checked with volteer, able to set Active/Passive bit according to the type of cable connected Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I7fe2c28f72d95d792d8f2ea0b8f74a21e2b5f2b7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2216554 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: For USB/DP/USB4, set 'Re-timer_Driver' bit based on SOP' VDO2Ayushee2020-05-271-4/+18
| | | | | | | | | | | | | | | For DFP, if the mux state is either USB/DP/USB4, then the re-timer_Driver bit is set according to the SOP' VDO2 response. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=Able to set Re-timer_Driver bit with a Gen3 Active cable Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Idb1134600617161137c6f500790b6c0c3b836200 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2152286 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Refactor TBT retimer bitsAyushee2020-05-271-53/+84
| | | | | | | | | | | | | | | | | | | | | | For DFP, the following bits depend on the Discover Mode SOP and SOP' response. Bit 2: RE_TIMER_DRIVER Bit 17: TBT_TYPE, Bit 18: CABLE_TYPE, Bit 20: TBT_ACTIVE_LINK_TRAINING Bits 29-28: TBT_GEN_SUPPORT Hence setting these bits accordingly in "retimer_set_state_dfp()" function. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=Able to see Thunderbolt getting enumerated on the CPU console Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: I0172cd9c74ba37c0f3e87db55cbd58ebaeef5ebe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139281 Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Refactor 'Active/Passive' bitAyushee2020-05-211-17/+37
| | | | | | | | | | | | | | | | | | For DFP, all the alternate modes i.e DP/Thunderbolt-comp/USB4 Active/Passive bit should be set according to the Discover mode SOP' response. Ref: Burnside Bridge spec Table 13: Connection state register. BUG=b:152544514 BRANCH=None TEST=Checked with volteer, able to set Active/Passive bit according to the type of cable connected Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Iac69754111d9d1ccfc033e7f66dacf604558eaee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139282 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Add 'USB3_Speed' bitAyushee2020-05-212-0/+9
| | | | | | | | | | | | | | | | | USB3_Speed bit is set to 1 if USB3 Gen1/Gen2 is supported. Hence, added functions to return cable rev 2.0 speed and cable rev 3.0 speed. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=Tested on volteer, with a Type-C dock, able to get USB3 Gen1/2 speed by checking "lsusb -t" on CPU console. Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Idd7d7de3446e82ac81025cda36ee8a7e1f274138 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139279 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* BB retimer: Add 'USB2_connection' bitVijay Hiremath2020-05-212-11/+48
| | | | | | | | | | | | | | | | | | USB2_CONNECTION bit is set to 1 if the cable is either Passive or a Gen3 active cable with USB2.0 support. Hence, added a function that indicates if the cable supports USB2 connection. Ref: Burnside Bridge spec Table 13: Connection state register BUG=b:152544514 BRANCH=None TEST=Tested on volteer by connecting a dock using a Gen3 Active cable with a USB2.0 connected to the dock, able to set USB2_connection bit. Change-Id: I125182b23becaa7d00011f6eadb1916b48c79803 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139278 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* pi3hdx1204: Allow tuning to be adjusted.David Huang2020-05-212-5/+63
| | | | | | | | | | | | | BUG=b:156058725 BRANCH=none TEST=check i2c writes Signed-off-by: David Huang <david.huang@quanta.corp-partner.google.com> Change-Id: I636a39e7b0540bea9cd7db70aa91330fa80ea5b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2192454 Tested-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* BB retimer: Update Bit 12Ayushee2020-05-192-9/+0
| | | | | | | | | | | | | | | | Bit 12 for the retimer is reserved. Hence updating the Bit 12 from DEBUG_ACCESSORY_MODE to reserved. Ref: Burnside Bridge spec Table 13: Connection state register. BUG=b:152544514 BRANCH=None TEST=make buildall -j Signed-off-by: Ayushee <ayushee.shah@intel.com> Change-Id: Ida60b3002f303054612e95b197c62dc2786f58fe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139280 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* pi3hdx1204: Add driver.Edward Hill2020-05-052-0/+45
| | | | | | | | | | | | | | Add simple driver to just turn power on and off via I2C. BUG=b:154874071 BRANCH=none TEST=check i2c writes Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I836340dbd7a9e41380d1469dac0a94e268bd2bf6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2181793 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* USB-C: Determine port partner's data role based on PD's data roleVijay Hiremath2020-03-191-3/+4
| | | | | | | | | | | | | | | | | | | | | Current code uses the CC lines to find out the data role of a port partner, however when the PD based data role swap happens DR_swap command has no effect on the CC lines. Hence need to use PD's data role to determine port partner's data role. Reference: USB Type-C cable and connector specification, Release 2.0 4.5.1.4.2 USB PD-based Power Role, Data Role and VCONN Swapping Table 4-12 USB PD Swapping Port Behavior Summary BUG=b:151653348 BRANCH=none TEST=UFP/DFP is correctly configured hence no PMC timeout errors observed on Volteer. Change-Id: I237d5c3f88096f4bd2d043ab823c98fe47686fa9 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107890 Reviewed-by: Keith Short <keithshort@chromium.org>
* TUSB544: Add driver structure declarationDiana Z2020-03-162-20/+22
| | | | | | | | | | | | | | | This adds the extern declaration for the tusb544_drv structure for boards to use, clarifies the name of the I2C address flag, and updates to the new redriver driver type. BUG=None BRANCH=None TEST=builds Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I045b76599f6cc5a4c64ae88bda7cd72c94a19e40 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101218 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* variant trembyle: use fw_config for mux initializationDenis Brockus2020-03-124-0/+5
| | | | | | | | | | | | | | | | Setup the usb_muxes table to the correct values based on fw_config instead of using probing. BUG=none BRANCH=none TEST=verify USB is still working Signed-off-by: Denis Brockus <dbrockus@chromium.org> Change-Id: I7550d15d563f987def4fe70d52a55e31b655b753 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094743 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* nb7v904m: Fix bug with CHIP_EN polarityAseda Aboagye2020-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | The driver's set_low_power_mode() function had its logic inversed. If we want to enable low power mode, we need to clear the CHIP_EN bit. BUG=b:150822611,b:150875209 BRANCH=None TEST=Flash waddledoo with an AP FW that has the fixed VBT, flash the EC with an image that contains this patch, verify that external displays over USB-C are working and that hot plugging the displays are working as well. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Idc3c4d663365d0898b3e7c869b9c6e2dd088fa78 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2090082 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* bb_retimer: Set Data_Connection_Present bit in Safe modeVijay Hiremath2020-03-051-0/+1
| | | | | | | | | | | BUG=b:150764332 BRANCH=none TEST=Data_Connection_Present is set in safe mode on Volteer Change-Id: Ib00ab10d2527636d9e6342de937477a72625f8bf Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2087902 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_mux: retimer: mux as chained mux and retimerDenis Brockus2020-02-2810-195/+182
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes retimers appear as generic muxes. By allowing a chain of muxes they can be stacked up to the new configurations that zork requires and will continue to work as they did before on configurations that only have a single mux. The code used to have two different arrays, 1) muxes and 2) retimers. On one of the zork configurations the processor MUX stopped being the primary mux and the retimer took its place. In a different configuration of that same platform it left the primary and secondary alone but the mux_set FLIP operation had to be ignored. Since the same interfaces needed to be available for both it stopped making sense to have two different structures and two different methods of handling them. This consolodates the two into one. The platforms that do not have retimers, this change will not make any difference. For platforms like zork, it will remove the retimers and make them chained muxes. So testing on trembyle makes sense to verify, BUG=b:147593660 BRANCH=none TEST=verify USB still works on trembyle Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* volteer: Update USB C1 reset for next buildstabilize-volteer-12931.B-masterKeith Short2020-02-261-4/+9
| | | | | | | | | | | | | | | | Update the GPIO assignment for the USB_C1_RT_RST_ODL signal for the next board build. BUG=b:144933528, b:148243971 BRANCH=none TEST=make buildall TEST=Check unassigned board ID or board ID=0 uses legacy GPIO setting. Otherwise new GPIO setting is used. Change-Id: I4621e039e4461a4e10ab87bc2d4e000b5dcaa885 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057496 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TUSB544: Add driverDiana Z2020-02-252-0/+142
| | | | | | | | | | | | | Driver code for the TUSB544 redriver BRANCH=None BUG=b:149561847 TEST=builds Change-Id: I391d6d264ff9d326c2d45569124dd1366f892812 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062766 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* trembyle: adjust gain on USB-A ps8811 for gen2 speedsDenis Brockus2020-02-061-0/+50
| | | | | | | | | | | | | BUG=b:138600008 BRANCH=none TEST=verify gen2 speeds on ps8811 equipt USB-A connections Change-Id: I5226fccf2460009dd7f873ca6869b57048bd65fc Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2040096 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* ps8818: debug cleanupDenis Brockus2020-02-062-56/+49
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I54817e28b255fddece2f4911ebef1fdbb86af367 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039912 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8802: debug cleanup and make wake_up accessibleDenis Brockus2020-02-062-76/+104
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I4fe0ce5fa1996367dfeeb982077a498e164c9a59 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039911 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* PS8818: use read/modify/write for regs with reserved bitsDenis Brockus2020-02-012-15/+36
| | | | | | | | | | | | | | | | | | PS88xx has a tendency to document undocumented register bits as reserved. Some of these are reserved and others should not be reset to 0 and should remain the value they were previously. The gain control appears to be of the latter type on the PS8818 BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: Ia67824c9b2676ad9984e4a8535ddd37bb8f2190b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2033304 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ps8802: fix redriver configurationDenis Brockus2020-01-312-23/+210
| | | | | | | | | | | | | | | | | | | | | | | | in driver Added software IN_HPD control Added compile time optional debug in board specific tune function in usb_retimer Added gain control Added display lane control NOTE: PS8802 has reserved register bits that are being used internally, so be cautious just hitting these with 0, i.e. use field update to set a value to retain the old reserved fields BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: I0b539df15fade509058492d6ab73a7b3ca9181df Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031646 Reviewed-by: Edward Hill <ecgh@chromium.org>
* ps8818: fix redriver configurationDenis Brockus2020-01-312-9/+94
| | | | | | | | | | | | | | | | | | | in driver Added software IN_HPD control Added compile time optional debug in board specific tune function in usb_retimer Added gain control Added DP lane control BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: Ida0cc243413b8fa469d3edb706040535e4a3f0e0 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031645 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Burnside bridge retimer: Add USB4 mode bitsAyushee2020-01-312-22/+37
| | | | | | | | | | | | | | | | | | | | | | | | | Intel burnside bridge retimer supports the ability to train the link and operate both USB4 Gen2(10Gbps) and USB4 Gen3(20Gbps) Adding the following fields in the configuration register of the retimer to USB4 mode: 1. Active cable - Active/passive cable 2. Cable type - Optical or Electrical 3. Active link training - Unidirectional or bidirectional link training 4. USB4 cable speed - 10Gbps/20Gbps active/passive cable 5. USB4 Generation - 3rd Generation or 4th Generation Thunderbolt cable BRANCH=None BUG=b:140819518 TEST=Able to configure the retimer in USB4 mode on TGLRVP Change-Id: I3d6bfd92eccc4881dac2b892926aafc2281e2a12 Signed-off-by: Ayushee <ayushee.shah@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926383 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* ps8818: allow access to all of the register pagesDenis Brockus2020-01-302-12/+93
| | | | | | | | | | | | | | | | Added possible registers that we may need to adjust and many of them are not on page0. So changed the base code to handle different pages BUG=none BRANCH=none TEST=verify different pages can be accessed Change-Id: If6a7a2e141d9c052dfa8da612b9e5268d21630a7 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2022915 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* TCPMv1: Cleanup sending TBT control flags to hostVijay Hiremath2020-01-291-11/+11
| | | | | | | | | | | BUG=b:148114593 BRANCH=none TEST=tested on Volteer, able to get correct TBT control flags Change-Id: If673d4a194d3cc6b9579f0f32511c6363f2614f3 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013825 Reviewed-by: Keith Short <keithshort@chromium.org>
* driver/retimer: Add support for ON Semi NB7V904MAseda Aboagye2020-01-292-0/+184
| | | | | | | | | | | | | | | | | This commit adds support for the ON Semiconductor NB7V904M USB Type-C Alt Mode Linear Redriver. BUG=b:147782066 BRANCH=None TEST=Enable on waddledoo, `make -j BOARD=waddledoo` Change-Id: Ia6fe76d0ad99bf7a8129e5d453ff12183990a50a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018707 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* usb_mux: cleanup: Replace mux state enums with ec_command bit flagVijay Hiremath2020-01-283-18/+18
| | | | | | | | | | | BUG=b:145796172 BRANCH=none TEST=make buildall -j Change-Id: Ie4ffaf208745764262931501f0dff77b525a4e59 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2017569 Reviewed-by: Jett Rink <jettrink@chromium.org>
* zork: PS8802/PS8818 dynamic detection cleanupDenis Brockus2020-01-234-9/+105
| | | | | | | | | | | | | | | | | | | | | | | | | Changed the method for detection to a non-destructive mechanism so it could be called from any of the interfaces. Added in switching to direct calling the detected driver once the hardware has been determined. The 8802 is the main mux when it is present and the fp5 mux should only select the lanes to send. Flip should not be sent to the FP5. It is a specialized form of a secondary MUX and currently being placed in as a retimer. In the future the retimers will all become MUXes and they will chain... just not today. BUG=b:147428570 BRANCH=none TEST=verify USB-C1 device with AP running Change-Id: I6b0eedd1dfcc91c3114f8dc481f5ca2841eb9e85 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2014311 Reviewed-by: Edward Hill <ecgh@chromium.org>
* retimer: framework cleanup for chip specific control configDenis Brockus2020-01-164-16/+39
| | | | | | | | | | | | | | | | combine the optional control variables into a union of structures to reduce the amount of space needed for a particular board type. BUG=b:147593165 BRANCH=none TEST=make buildall -j Change-Id: If02c4c8065f4570aba210c3e34b30bc0d5c7a852 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2001134 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* ps8802: use hardware pin for IN_HPDDenis Brockus2020-01-141-2/+1
| | | | | | | | | | | | | | we have a hardware line to this pin, so we should use that instead of setting it in firmware BUG=b:139432598 BRANCH=none TEST=make buildall -j Change-Id: I0e7e826930d4421f2cb6e03d09ea9d7036a9ad26 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1993862 Reviewed-by: Edward Hill <ecgh@chromium.org>
* TCPMv1: Correct the TBT3 Discovery and Entry FlowVijay Hiremath2020-01-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | Ref: USB Type-C Cable and Connector Specification 2.0 F.2 TBT3 Discovery and Entry Flow - Corrected the TBT3 Discovery flow - Corrected the TBT3 Entry Flow - Enabled the Active cable TBT3 mode entry - Refactored TBT & Cable VDO code on TCPMv1 so that same VDO structures can be used for TCPMv2 - Corrected getting the cable version - Cleaned up the code for super speed cable detection BUG=b:146006708, b:140643923, b:147134610 BRANCH=none TEST=Make buildall -j Able to detect Thunderbolt-compatible devices on TGLRVP Change-Id: I65f82e241d0cc2187050913e7d16942fdaa0ebd4 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1981276 Reviewed-by: Diana Z <dzigterman@chromium.org>
* retimer: Add PS8802 driverEdward Hill2019-12-262-0/+102
| | | | | | | | | | | | | BUG=b:138682132, b:143147353 BRANCH=none TEST=USB3 device enumerates as 5G on Trembyle OPT3 USB-C1 Change-Id: I214517f9b2f821fd47079ea0828a810a0b7bb287 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980391 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org>
* retimer: Add PS8818 driverEdward Hill2019-12-202-0/+68
| | | | | | | | | | | | BUG=b:139428235, b:145766506 BRANCH=none TEST=USB3 device enumerates as 5G on Trembyle OPT1 USB-C1 Change-Id: I96ddd393626000630daf1ce517e003f6472c50cd Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1977983 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Burnside bridge retimer: Add Thunderbolt-compatible mode bitsAyushee2019-12-172-12/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel burnside bridge retimer supports the ability to train the link and operate in both Thunderbolt 1/2(10Gbps) and Thunderbolt 3 (20Gbps) link speeds. Adding the following fields in the configuration register of the retimer to support Thunderbolt-compatible mode: 1. Active cable - Active/passive cable 2. Thunderbolt connection - Thunderbolt configured or not 3. Thunderbolt type - Type-C Type-C or Type-C legacy thunderbolt adapter 4. Thunderbolt Cable type - Optical or Electrical 5. Active link training - Unidirectional or bidirectional link training 6. Thunderbolt cable speed - 10Gbps/20Gbps active/passive cable 7. Thunderbolt Generation - 3rd generation or 4th generation thunderbolt cable BUG=b:140645327 BRANCH=None TEST=Manually verified on Tglrvp-U, able to configure the registers Change-Id: I4ac351702df156c5bddf4ead141f59000a6d6af5 Signed-off-by: Ayushee <ayushee.shah@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1926380 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_pd: Get current DP pin modeVijay Hiremath2019-12-111-1/+1
| | | | | | | | | | | | | | As part of the new changes in CL:1949052 getting DP pin mode status is removed hence adding back old CL:1646534 on TOT. BUG=b:146006717 BRANCH=none TEST=Manually tested on TGLRVP, able to see DP working Change-Id: I09cee179ad64c1b7753ec87ce83a1d5dc54770cd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961150 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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