| Commit message (Collapse) | Author | Age | Files | Lines |
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factory-brya-14909.124.B-main"
This reverts commit 184d13e77614be3be5374d3fef9d1edf66ec8687.
Reason for revert: broken build due to ec-utils.
Original change's description:
> Merge remote-tracking branch cros/main into factory-brya-14909.124.B-main
>
> Generated by: util/update_release_branch.py --baseboard brya --relevant_paths_file
> baseboard/brya/relevant-paths.txt factory-brya-14909.124.B-main
>
> Relevant changes:
>
> git log --oneline 19d4d68ffa..aa40b859b3 -- baseboard/brya board/agah
> board/anahera board/banshee board/brya board/crota board/felwinter
> board/gimble board/kano board/mithrax board/osiris board/primus
> board/redrix board/taeko board/taniks board/vell board/volmar
> driver/bc12/pi3usb9201_public.* driver/charger/bq25710.*
> driver/ppc/nx20p348x.* driver/ppc/syv682x_public.*
> driver/retimer/bb_retimer_public.* driver/tcpm/nct38xx.*
> driver/tcpm/ps8xxx_public.* driver/tcpm/tcpci.* include/power/alderlake*
> include/intel_x86.h power/alderlake* power/intel_x86.c
> util/getversion.sh
>
> e6da633c38 driver: Sort header files
> 234a87ae2d tcpci: Add FRS enable to driver structure
> a56be59ccd tcpm_header: add test for tcpm_dump_registers
> 57b3256963 Rename CONFIG_CHARGER_INPUT_CURRENT to _CHARGER_DEFAULT_CURRENT_LIMIT
> e420c8ff9a marasov: Modify TypeC and TypeA configuration.
> 43b53e0045 Add default implementation of board_set_charge_limit
> b75dc90677 Add CONFIG_CHARGER_MIN_INPUT_CURRENT_LIMIT
> f1b563c350 baseboard: Sort header files
> 7d01b1e58d driver/retimer/ps8818.h: Add I2C ADDR FLAGS 0x30, 0x58, 0x70
> ec31407993 Add CONFIG_CHARGER_INPUT_CURRENT_DERATE_PCT
> 8f89f69a5b crota: disable lid angle sensor for clamshell
>
> BRANCH=None
> BUG=b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
> BUG=b:247100970 b:254328661
> TEST=`emerge-brya chromeos-ec`
>
> Force-Relevant-Builds: all
> Change-Id: I0ecfa0e6af68631283c7a9e8f1afb9d827176c62
> Signed-off-by: YH Lin <yueherngl@google.com>
Bug: b:260630630 b:163093572 b:259002141 b:255184961 b:259354679
Bug: b:247100970 b:254328661
Change-Id: Ia14942d1bd6a502062399d77cb59d1f4b549b2c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077247
Auto-Submit: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: YH Lin <yueherngl@chromium.org>
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Sort all includes in driver with the clang-format rules used by
the zephyr project.
BRANCH=None
BUG=b:247100970
TEST=zmake build -a
TEST=./twister --clobber -v -i
TEST=make -j72 buildall_only runtests
TEST=zmake compare-builds -a
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Change-Id: I675e0db416b6b7cbcfce031c97fd24ad97b66f4f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4052767
Reviewed-by: Yuval Peress <peress@google.com>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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When safe mode was first introduced, it was added only to drivers on the
boards with virtual muxes and the mode wasn't sent to other drivers.
Since safe mode is defined as an input for the mux API, ensure all
drivers can handle this input. For now, set up all drivers which did
not have handling to handle it the same as None, which was previously
sent to them.
LOW_COVERAGE_REASON=20 of the changed drivers have no emulators
BRANCH=None
BUG=b:234772074
TEST=make -j buildall; search for all files containing a usb_mux_driver
without any reference to USB_PD_MUX_SAFE_MODE and ensure they are
correct to not reference it
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ib927057bbf1638d09000bdad98bc096a6e103611
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3902611
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
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Split struct usb_mux into struct usb_mux_chain and struct usb_mux. The
first structure is linked list to construct USB muxes chain and has
pointer to struct usb_mux. New struct usb_mux contains only information
about mux itself, not it position in the chain.
This is first CL and it changes common EC files.
LOW_COVERAGE_REASON=no emulator for some of the muxes set up yet
BUG=b:236274003
TEST=zmake build -a
TEST=./twister -T zephyr/test
TEST=make buildall
BRANCH=None
Cq-Depend: chromium:3779618, chromium:3779619, chromium:3779620
Cq-Depend: chromium:3779621, chromium:3779622, chromium:3779623
Cq-Depend: chromium:3779624, chromium:3779625, chromium:3779626
Cq-Depend: chromium:3779627, chromium:3779628, chromium:3779629
Cq-Depend: chromium:3779630, chromium:3779631, chromium:3779632
Cq-Depend: chromium:3779633, chromium:3779634, chromium:3779635
Cq-Depend: chromium:3779636, chromium:3780397, chromium:3780398
Cq-Depend: chromium:3780399, chromium:3780400, chromium:3780401
Cq-Depend: chromium:3780402, chromium:3780403, chromium:3780404
Cq-Depend: chromium:3780405, chromium:3780406, chromium:3780407
Cq-Depend: chromium:3780408, chromium:3780409, chromium:3780410
Cq-Depend: chromium:3780411, chromium:3780412, chromium:3780413
Signed-off-by: Tomasz Michalec <tm@semihalf.com>
Change-Id: Ida64c87b8194dbf4a1273d66aaa773a21b2cff87
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3748785
Commit-Queue: Tomasz Michalec <tmichalec@google.com>
Tested-by: Tomasz Michalec <tmichalec@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Code-Coverage: Tomasz Michalec <tmichalec@google.com>
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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Ided2361c208c09b5cb6bcb1ac2c6553d7834b062
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730074
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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In order to correctly sequence HPD sets with the AP, allow the HPD set
to wait on an ACK from the AP before proceeding.
BRANCH=None
BUG=b:202137658
TEST=on brya, validate retimer and virtual mux are kept in sync as
expected
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I368c3290b69d627829a70847876d7b47a8c36948
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3232293
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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As a followup to CL:3104290, give the TCPCI TRANSMIT and
RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used
for receiving, not just transmitting. Fix lint errors thus revealed.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995
Reviewed-by: Keith Short <keithshort@chromium.org>
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Since we have definitions for HPD IRQ and level in the mux flags, extend
this to the HPD update function in the usb_mux structure as well.
BRANCH=None
BUG=b:172222942
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I19c3a65fc821a341338d73fabd7876339b37fe7d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095437
Reviewed-by: Keith Short <keithshort@chromium.org>
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Convert usages of this enum to tcpm_sop_type.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I5fed273d72e7ad0e191db0cb0d121b70bdd9ecdb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104291
Reviewed-by: Keith Short <keithshort@chromium.org>
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Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be
used for Rx as well. Describe it in comments. This prepares to
consolidate enum pd_msg_type into this enum.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290
Reviewed-by: Keith Short <keithshort@chromium.org>
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Currently, only the virtual mux driver uses the mux ACK feature, but the
actual wait for the host command ACK is a part of the usb_mux general
code. Generalize this mux ACK wait so it's available if needed in the
future for more muxes.
Additionally, moving this wait out of the mux set will allow us to lock
the muxes intelligently between tasks, without keeping the muxes locked
during the inactive ACK wait.
BRANCH=None
BUG=b:172222942,b:186777984
TEST=tast typec.Mode*.manual on voxel
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I61a043425a482cc6f3170548c888d91ec20c2a82
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078411
Reviewed-by: Keith Short <keithshort@chromium.org>
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After the first BIST Test Data packet, enable BIST Test Mode if the TCPC
supports it (currently just TCPCI). While in BIST Test Mode, mask
ALERT.ReceivedSOP*MessageStatus. Unmask it when the test ends, due to
Hard Reset or to detach.
BUG=b:173023378,b:169385081,b:172709198,b:173028832,b:173028791
BUG=b:173141941,b:173142113
TEST=Complete TDA.2.1.2.2 BMC PHY RX INT REJ on volteer without running
out of Rx buffer space or watchdog timeout (still fail though)
BRANCH=firmware-volteer-13521.B-master
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I03bbc4cfacceebd0334aa814e11a16e09177a322
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2545667
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This header cannot currently be accessed by Zephyr since it is in a
driver directory, not an include directory. This header has quite a
bit of public stuff in it, so it seems reasonable to consider
everything public.
Move the header file and update all users.
BUG=b:175434113
BRANCH=none
TEST=make buildall -j30
build volteer on zephyr
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ibba37f47a06783fafb5095f853f2a68d92b6df87
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607745
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This header file is used from quite a few files, relying on the EC
build system to find includes in the driver/tcpm directory. For Zephyr
we don't want to add that as an include.
It makes more sense for header files to be in an include directory, so
move it and fix up the users.
BUG=b:175434113
BRANCH=none
TEST=build Zephyr and ECOS on volteer
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985
Reviewed-by: Keith Short <keithshort@chromium.org>
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There is an option in the task_set_event function which force
the calling task to wait for an event. However, the option is never
used thus remove it.
This also will help in the Zephyr migration process.
BUG=b:172360521
BRANCH=none
TEST=make buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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CL:2542865 adds calls to tcpm_sop_prime_enable() function but there is no
implementation of sop_prime_enable() provided in anx74xx_tcpm_drv.
This causes EC crashes during firmware_PDTrySrc test.
This patch adds tcpci_tcpm_sop_prime_enable() and implementation of
sop_prime_enable() in anx74xx_tcpm_drv, similarly to other ANX drivers.
BUG=b:168560801, b:162254118
BRANCH=none
TEST=Flash eve with EC ToT, run firmware_PDTrySrc test.
Make sure that EC doesn't crash during test.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I7cb2738f2a238901d03e3d8cb98ee39ce26bf38a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2560635
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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The ANX3429 was developed before the PD 3.0 specification and is not PD
3.0 compliant. Disallow building this driver with PD 3.0 enabled.
BRANCH=None
BUG=b:159253723
TEST=make -j buidall passes; configure eve for PD 3.0 and see it fails
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I1d46d313f2914e98180e9a599b8ccdeb430afdef
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2354629
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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When we receive hard reset, we should do Vbus on-off cycle
and should keep cc connection. So I change the event setting
from PD_EVENT_TCPC_RESET to PD_EVENT_RX_HARD_RESET for ITE TCPC.
Stand alone TCPCs also use hard reset event instead of calling
pd_execute_hard_reset(), because waked up pd_task() may have chance
setting to other state.
BRANCH=None
BUG=b:159394180
TEST=On board reef_it8320, and it81202_pdevb:
1.TCPMv1: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
2.TCPMv2: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: Ie94757580e8fed4fb33896f9c1e071def49ff03d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284504
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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The original get_chip_info() returns a point of point to the chip_info.
This way helps to cache the chip_info to a static variable and the
function just returns the pointer to the static variable.
This static variable has a race condition on the PS8805 chip. The PS8805
chip returns a different PID when the firmware is corrupted, i.e. 0x8803
instead of 0x8805. The !live case fixes the PID, by modifying the static
variable directly. When another task calls the same function for the
live case, the static variable is modified and has a race condition.
This change fixes the issue by changing the get_chip_info() parameter to
a point of the chip_info. The caller has to allocate a buffer in the
stack and pass the address to the function. For the !live case, the
function copies the cache value from the static variable to the buffer.
So the static variable doesn't have a race condition.
BRANCH=None
BUG=b:159588335
TEST=Used ectool to check the PD chip PID 0x8805 (was 0x8803).
localhost ~ # ectool pdchipinfo 1
vendor_id: 0x1da0
product_id: 0x8805
device_id: 0x1
fw_version: 0x0
min_req_fw_version: 0x0
Change-Id: Ic24615af77ea58016d286480572d2a282c4fa09a
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2264477
Reviewed-by: Julius Werner <jwerner@chromium.org>
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In TCPCI Rev2, the extended status register was
added that allows Safe0V to be known. For other
platforms, this code will revert back to using
Safe0V will be !Safe5V, as it currently is.
BUG=none
BRANCH=none
TEST=verify USB functionality
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: Ifd6b5c3bb45ff076fd0d3b4b0bb687ccf6f4c91b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2199037
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
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this is to add near future functionality to allow
not only the current PRESENT range check but to add
Save0V range checking as well, for platforms that
allow for this. This just lays the framework and
is functionally equivalent.
BUG=none
BRANCH=none
TEST=verify basic USB functionality
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: I1eb3411bc3aa9b792c9b97799e1721e5cb229f64
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2199036
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
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The cached pull is no longer needed, so removing the code.
BUG=none
BRANCH=none
TEST=make buildall -j
Signed-off-by: Denis Brockus <dbrockus@google.com>
Change-Id: Ib408b085452d6956ebbff04c038f6385a5202227
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107995
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Auto-Submit: Denis Brockus <dbrockus@chromium.org>
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CL:2001938 renamed SOPP/SOPPP to SOP_PRIME/SOP_PRIME_PRIME, but didn't
change some affected code. This CL fixes the incorrect names.
BUG=none
TEST=`make BOARD=kappa` with TCPMV2 enabled
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I91526f5552a188e01338b72bc47125fb12ff53b2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088826
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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This makes retimers appear as generic muxes. By allowing a
chain of muxes they can be stacked up to the new configurations
that zork requires and will continue to work as they did before
on configurations that only have a single mux.
The code used to have two different arrays, 1) muxes and 2)
retimers. On one of the zork configurations the processor
MUX stopped being the primary mux and the retimer took its
place. In a different configuration of that same platform
it left the primary and secondary alone but the mux_set
FLIP operation had to be ignored. Since the same
interfaces needed to be available for both it stopped making
sense to have two different structures and two different
methods of handling them. This consolodates the two into
one.
The platforms that do not have retimers, this change will
not make any difference. For platforms like zork, it will
remove the retimers and make them chained muxes. So
testing on trembyle makes sense to verify,
BUG=b:147593660
BRANCH=none
TEST=verify USB still works on trembyle
Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794
Commit-Queue: Jett Rink <jettrink@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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TCPCIr2 had an issue with setting CC coming out of DRP
that if the polarity was not retained that the connection
dropped back to OPEN. Unfortunately this change broke
many of the other TCPCI implementations. I am working
on a different method of dealing with coming out of DRP
and this is no longer needed.
BUG=none
BRANCH=none
TEST=verify USB-C is working
Change-Id: Ifa8f26d417df2f5d5f41a23fbf7e6f9129031e94
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056968
Reviewed-by: Jett Rink <jettrink@chromium.org>
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When we have SNK_DTS polarity, we still want to drive both CC
lines with the appropriate pull. SRC_DTS should not show as
having a polarity. Non-DTS should show the correct polarity.
We were only handling the last sentence of that.
BUG=b:147754772
BRANCH=none
TEST=verify SuzyQ works on zork
Change-Id: I013f9d881427d6d97b655f88cfb3a94e3ed10c61
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2022914
Tested-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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BUG=b:145796172
BRANCH=none
TEST=make buildall -j
Change-Id: Ie4ffaf208745764262931501f0dff77b525a4e59
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2017569
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Some of the NCT38XX driver code was more generic TCPCI
than specific to the chip. So moved a number of the
functions over to be generically handled.
In doing this I propagated the idea of tri-state
polarity. It is now either NORMAL, FLIPPED, or NONE
for unattached. This is needed for the generic handling
of correctly setting CC. This required changing the
polarity from NONE to the appropriate detected polarity
when in auto toggle.
tcpci_tcpm_set_cc will now only set a single CC line
when attached and both when unattached.
BUG=b:146003980, chromium:951681
BRANCH=none
TEST=Charging works with both plug orientations with AP on
TEST=Device works with both plug orientations with AP on
TEST=Charging works with both plug orientations with AP off
Change-Id: Ie4b5cc998902a346a4f4a2c1480204b3a81017dd
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1967932
Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Certain SKUs of certain boards have lesser number of USB PD ports than
defined by CONFIG_USB_PD_PORT_COUNT. Hence rename
CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT.
BUG=b:140816510, b:143196487
BRANCH=octopus
TEST=make -j buildall; Boot to ChromeOS
Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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Refactor code to use proper type for cc1 and cc2 lines.
BRANCH=none
BUG=none
TEST=builds. No functional change.
Change-Id: Id292db8480920e2b191bac9d9ecc2685f61e4ea9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1744654
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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The extentions were added to make the compiler perform most
of the verification that the conversion was being done correctly
to remove 8bit addressing as the standard I2C/SPI address type.
Now that the compiler has verified the code, the extra
extentions are being removed
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
TEST=verify sensor functionality on arcada_ish
Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as
follows:
0 -> Return hard-coded info for Vendor ID/Product ID and cached info for
the Firmware Version
1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version
Also rename the 'renew' field to 'live' to match the new semantics.
BUG=b:128820536,b:119046668
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS.
Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Opt for 7bit slave addresses in EC code. If 8bit is
expected by a driver, make it local and show this in
the naming.
Use __7b, __7bf and __8b as name extensions for i2c/spi
addresses used in the EC codebase. __7b indicates a
7bit address by itself. __7bf indicates a 7bit address
with optional flags attached. __8b indicates a 8bit
address by itself.
Allow space for 10bit addresses, even though this is
not currently being used by any of our attached
devices.
These extensions are for verification purposes only and
will be removed in the last pass of this ticket. I want
to make sure the variable names reflect the type to help
eliminate future 7/8/7-flags confusion.
BUG=chromium:971296
BRANCH=none
TEST=make buildall -j
Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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tcpc_config contained a field for both the alert polarity and open
drain/push pull configuration. There is also a possible difference in TCPC
reset polarity. Instead of adding yet another field to describe this
configuration, it would be better to convert alert polairty, open
drain and reset polarity into a single flags field.
This CL modifies the tcpc_config struct to use a single flags field
and adds defines for what existing flag options can be.
BUG=b:130194031
BRANCH=none
TEST=make -j buildall
Change-Id: Ifb7e7604edb7021fb2d36ee279049eb52fefc99e
Signed-off-by: Scott Collyer <scollyer@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1551581
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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If USB is enabled, the original logic uses the pin assignment D
which also connects the ML0 and ML1 switches, not matter DP is
enabled or not. It affects some DP signal integrity on the other
port which shares the same DP source. Should make the ML0/ML1
switches unconnected if DP is not enabled.
BRANCH=none
BUG=b:116879483
TEST=According to the bug, manually typing the i2c command like this
change to disconnect ML0/ML1 fixes the issue.
Change-Id: Icfa10b97331be7935bb626771b41eb509fa61f50
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1282005
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Remove unneeded mask from variable
BUG=b:122109575
BRANCH=none
TEST=manual
Change-Id: I257233f73db4f76dc251814cde88ea38eaffef88
Signed-off-by: Sam Hurst <shurst@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1401122
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Rename the registers which configures the internal switches.
No logic change.
BRANCH=None
BUG=b:116879483
TEST=None. No logic change.
Change-Id: I10bcbc7d0da1b8e97be0811b8f3a188037c5d68c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1282004
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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Currently, the PD stack ignores messages received from SOP' and SOP'' and
this prevents the stack from communicating with VCONN Power Devices and
Cable Plugs in general.
I propose encoding the message address (SOP*) in the message header. The
message header is encoded as a 16-bit value but the TCPC drivers use a
32-bit type for the header.
The SOP* address will be stored in bits 31 to 28 of the message header
and the PD stack can check those bits to determine the address of the
message.
BUG=b:122109575
BRANCH=none
TEST=manual
Change-Id: I2b34c16cae186202c9cf0bc5f940e05151e88cbf
Signed-off-by: Sam Hurst <shurst@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1390951
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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All chip info for the anx74xx and ps8xxx chips should be cached
after the first read, so that the info can be accessed in the
future without worrying about chip state. Now that we check the
version registers for these two chips, we need to cache that
information as well.
BRANCH=none
BUG=b:117301622
TEST=on warm reboot with GBB flags cleared, cbmem -t shows
the EC verification stage taking ~30ms instead of ~65ms.
Change-Id: I6077438b58e64b66a23db2992ba025ae3a864c19
Signed-off-by: Paul Moy <pmoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1291794
Commit-Ready: Martin Roth <martinroth@chromium.org>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The tcpc_cc_voltage_status enum contains different values for different
detected resister values of the port partner. Both Ra and Rd values
contained that in the name, but Rp values did not. Update _SNK_ tag to
_RP_ tag to make it more clear what resistor is being applied by port
partner.
Also adding a few more comments in usb_pd_tcpm.h for clarify on the
different uses of CC resistor enums.
BRANCH=none
BUG=none
TEST=builds. just a rename change.
Change-Id: Id5f7bb502f735bef5937585e2e8bd516ad428a99
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1278103
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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When it appears that the TCPC queue handling logic may be stuck in an
infinite loop, the EC will break the loop by disabling the port in order
to avoid task starvation. However, nothing attempts to resume the port,
and it therefore remains disabled until the next EC reset. Wake back up
after a reasonable interval in order to automatically retry. On port
suspend, completely drain the TCPM message queue.
BUG=chromium:891713
TEST=On Careena hardware, with analogix TCPC firmware v1.5 and an
electronically marked cable that sends SOP' messages, verify that the EC
auto-retries every second. After removing the offending cable, and PD
power supply will work.
BRANCH=grunt
Change-Id: I563b763501333eb36ee1f76e6f484ebb3245c82a
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1258571
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Due to SOP' false detection issues, anyone using ANX3429 should upgrade
the firmware to version 1.6
This new field will be used by factory/automated tests to ensure new
boards (and existing board that cherry pick these changes) remember to
upgrade the TCPC FW thus avoiding discovering the same bugs in each
project.
BRANCH=none
BUG=b:64752060,b:116255749
TEST=tested ps8751 path with is the same as ANX. I don't have a device
with ANX3429 right now.
Change-Id: Id4df192aca30f82baee3021189aef72a62deee4e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1246266
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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Add a new field to the pdchipinfo host command that exposes the minimum
required firmware version that we know about. This will allow factory
tests or automated test to compare this version to the current version
and fail.
BRANCH=none
BUG=b:116068318
TEST=with corresponding ectool change, min value is reported correctly
Change-Id: Idf338795c3fd6f9f95e51471d0f6a7a422901d52
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1240457
Reviewed-by: Justin TerAvest <teravest@chromium.org>
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When in PD_STATE_DRP_AUTO_TOGGLE, we were always enabling DRP
auto-toggle, even when drp_state is PD_DRP_TOGGLE_OFF or
PD_DRP_FORCE_SINK, which prevents us from acting as source.
This caused an infinite loop of entering and exiting low power
mode when a sink-only device was plugged into a PS8751 port when
the system is in S5/G3.
To fix this, only enable DRP auto-toggle when drp_state allows
us to be dual-role.
One problem with doing this is that the ANX3429 doesn't support
low power mode with auto-toggle disabled. Luckily, the ANX3429
will stay in low power mode when a sink-only device is connected.
BRANCH=none
BUG=b:72007056,b:111663127
TEST=sink device + ANX3429: low power mode [1]
TEST=sink device + PS8751: low power mode [1]
TEST=charger via hub + ANX3429: 50% chance fail to charge [2]
TEST=charger via hub + PS8751: starts charging
(all tests with Grunt in G3)
[1] dut-control pp3300_tcpc_mw -> 3.5
[2] b/72007056 still remains to be fixed.
Change-Id: Id190a3daa78847871288e66d8f229a485a6522e3
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194352
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle(), since enable=0
was unused.
BRANCH=none
BUG=b:111663127
TEST=PD and TCPC low power still work on Grunt
Change-Id: I760a067b11984a579261deac856419d46400497b
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1194353
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The alert line for TCPC will stay asserted as long as there are RX
messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear
all of the RX messages we know about during a single alert handling
session.
This CL can stand on its own, but it is a part of a CL stack that will
tighten the critical section of time between received messages from the
TCPC and sending follow up message out through the TCPC.
See go/usb-pd-slow-response-time for more details.
BRANCH=none
BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761
BUG=b:113057273,b:112825261
TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to
adversely affect state machine negotiation. Full CL stack consistently
sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the
24 ms threshold we need to be under for USB PD spec compliance.
Also testing pd_suspend scenario manually and EC was responsive after
port 1 suspend because of "bad behavior"
Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185727
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This converts the compile time option of
CONFIG_USB_PD_TCPM_TCPCI_MUX_ONLY into a runtime option to better
support draggon egg designs and reduce CONFIG complexity in general.
Introduce new mux_read/write to read from tcpc_config_t or mux driver
depending on new flag setting.
Audited all mux drivers for any use of tcpc_read/write and updated to
mux_read/write.
BRANCH=none
BUG=b:110937880
TEST=On Bip with CL stack:
Verified by connecting DP monitor at boot;
Verified plug / unplug of DP cable works;
Change-Id: I968893b886ff0ccc4074beae5ec42973814ae77c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1200062
Commit-Ready: Gaggery Tsai <gaggery.tsai@intel.corp-partner.google.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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There is a unneeded level on indirection for the anx74xx alert handler
that we can remove. This also make is more clear what is happening in
the child CLs.
See go/usb-pd-slow-response-time for more information.
BRANCH=none
BUG=none
TEST=no change on grunt device
Change-Id: I61f7caf09fc5cb5fa889fb727ee39bea681a97e9
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185726
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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This interrupt pin by default is a push-pull. It causes leak to EC VSPI
power during EC watchdog reset. As in our design, we use this interrupt
pin as open-drain. Should configure the register to make it open-drain.
BRANCH=none
BUG=b:112906111
TEST=Flashed the EC image to Cheza rev-2 board. Typed "reboot" command
and then EC reset properly.
Change-Id: Iee5db3cb5b5291778d97dee4fc70369d34344ce7
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1185871
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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