| Commit message (Collapse) | Author | Age | Files | Lines |
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If the pd port has previous connection and supplies
Vconn, then RO jumping to RW reset the system,
we never know which cc is the previous Vconn pin,
so we always turn both cc pins off when disable
Vconn power switch.
This change is leveraged from it83xx (CL:3178341),
although Vconn is controlled by ppc on asurada series
and asurada series don't happen the bug, but we still
need this change for the future that if there is a
project control Vconn by GPIO.
BUG=none
BRANCH=none
TEST=make board hayato
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I66e7961d5ba412c18948a433103c17b79e7c5e08
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180703
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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As a followup to CL:3104290, give the TCPCI TRANSMIT and
RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used
for receiving, not just transmitting. Fix lint errors thus revealed.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995
Reviewed-by: Keith Short <keithshort@chromium.org>
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Convert usages of this enum to tcpm_sop_type.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I5fed273d72e7ad0e191db0cb0d121b70bdd9ecdb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104291
Reviewed-by: Keith Short <keithshort@chromium.org>
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Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be
used for Rx as well. Describe it in comments. This prepares to
consolidate enum pd_msg_type into this enum.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290
Reviewed-by: Keith Short <keithshort@chromium.org>
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Separate pd interrupt functions to ite_pd_intc for
easier maintenance on cros_ec and zephyr.
And enable PD interrupt functions for zephyr.
BRANCH=none
BUG=none
TEST=1.can zmake hayato and make asurada
2.PD port functions work on board hayato
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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There is a name mismatch with some of the registers needed in this
driver. Use #define for now until we can change these in ECOS, or
remove the ECOS code.
BUG=b:189855648, b:190860075
BRANCH=none
TEST=with other CLs, build asurada for Zephyr
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I73da708c6e876db092b345ff7e0b28d99960b4d1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2957548
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Rename it83xx_tcpm_drv to it8xxx2_tcpm_drv for chip it8xxx2 series.
BUG=none
BRANCH=none
TEST=1.make buildall -j
2.on hayato, connecting to adapter and dongle can go to ready state.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I2622e7fe0884d3ae20a63ec48219de00d5537bc6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717430
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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If explicit contract is set in bbram when EC boot up, then TCPMv1
set soft reset as first state instead of unattached.SNK, so we need
to enable BMC PHY for tx module.
And same as TCPMv2, we turn on/off BMC PHY and set low power mask
when hook_dis/connect is called.
BUG=none
BRANCH=none
TEST=on icarus, the explicit contract is set in bbram when EC boot up,
and we can tx soft reset (won't happen tx timeout).
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I3c8d3db240d2290ced17b90aeb0420ac9f20598d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2712213
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Before disabling cc 5v tolerant, we need to make sure cc voltage
detector is enabled and Vconn is dropped below 3.3v (>500us) to
avoid the potential risk of voltage fed back into Vcore.
BRANCH=none
BUG=none
TEST=on drawcia and hayato:
Connect to dongle, then make sure that Vconn doesn't fed back
into Vcore (EC not crash), after we turn off Vconn power.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Idc8cd0d97a7f26c0af7a67127b5a9984c2a4c5d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2655166
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Replace PD_VCONN_SWAP_DELAY with CONFIG_USBC_VCONN_SWAP_DELAY_US. This
is the approximate result of the following command, run from
platform/ec:
find . -type f -\( -name '*.c' -o -name '*.h' -\) | \
xargs sed -iE 's/PD_VCONN_SWAP_DELAY/CONFIG_USBC_VCONN_SWAP_DELAY/g'
Fix some latent formatting errors in usb_pd_protocol.c, because they
were preventing pre-upload hooks from passing.
BUG=b:144165680
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Icaf3b309c08fdcd162e960cf5dc88185016b5d2d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Rename function name from it83xx_* to it8xxx2_* for it8xxx2 driver.
Rename function name from *_tcpm_sw_reset to *_tcpm_hook_disconnect.
BUG=none
BRANCH=none
TEST=make BOARD=drawcia -j
make BOARD=asurada -j
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8111ec5b9972d1badae625e87248c62e99eabbf6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598298
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Use the already existent board configuration PD_VCONN_SWAP_DELAY
for Vconn drop.
BUG=none
BRANCH=none
TEST=on hayato, Vconn drop to 0v before we disable 5v tolerant on cc.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I2cf52e1d2ba4cb4c1ce1fb9e09bf20fb9859359a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592212
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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Register BMC PHY (00h bit0) enable/disable both Tx and Rx module,
and we shouldn't enable/disable Tx module when Rx_enable() called,
So I change to set Rx decode enable/disable only in Rx_enable().
Setting PD sleep mask shouldn't tie with Rx_enable(), so I change
to set sleep mask by HOOK_CONNECT/DISCONNECT. Enable deep sleep mode,
when all ITE ports are in Unattach.SRC/SNK state and other ports
aren't pd_capable(). Disable deep sleep mode, when one of ITE port is
in Attach.SRC/SNK state or one of other ports is pd_capable().
BUG=none
BRANCH=none
TEST=on hayato, plug-in dongle and adapter:
1.console cmd "pd 0 hard", hard reset tx done is set within 1ms.
2.check PD sleep mask: nothing attached = 0, one port attached = 1
3.In G3(Rd_5.1k), then plug-in adapter, can go to
SNK_READY state
4.can send SOP' to E-mark cable
5.console cmd "sysjump rw", can go to SNK/SRC_READY
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I4af2657ae028e612715e5a99bf7562ffcf585896
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592211
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
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Add function for board hayato to tune cc pre-driving parameters,
so that we can improve eye diagram.
BUG=b:171279731
BRANCH=none
TEST=on hayato, console check registers
0x3773 = 0x1,
0x3774 = 0x2,
0x3873 = 0x1,
0x3874 = 0x2,
values are same as setting.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8829f1fb4672bc98287e9526458f71026e19ca16
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537528
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Add the ability to enable or disable SOP' traffic through a new
parameter. Name the function for "enable" to match other EC
conventions.
BRANCH=None
BUG=b:168560801
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ife52e7d7d098825ab2163c70a4c59510da958876
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2542864
Reviewed-by: Keith Short <keithshort@chromium.org>
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Refer to https://crrev.com/c/2381030, implement decode SOP' and SOP''
disable function to avoid system reboot when tcpm_sop_prime_disable()
is called.
BUG=b:170745517
BRANCH=none
TEST=Connect Gatkex/Tapex to TGL RVP U, no reboot, and TBT connection
is established
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Iccfdce78d626ab1d0c136d1597eec05e29512805
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2470234
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The SOP header wasn't encoded in the header if
CONFIG_USB_PD_DECODE_SOP enabled.
BUG=b:170297334
TEST=ensure DP plug not trigger soft-reset, ensure the SOP header is
encoded
BRANCH=none
Change-Id: Ie7e0203be78d8844ea365c892a895b24ada20c96
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2465438
Reviewed-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Between we disconnect Rd_DB and set USBPD_START(port),
CCs are open state for few micro seconds, so I move
Rd_DB disconnection behind USBPD_START(port) to avoid
CCs temporarily open state. But this will cause about
1.5us that CCs assert both Rd_5.1k and Rd_DB.
BUG=b:169691804
BRANCH=none
TEST=on board asurada and reef_it8320, connect to adapter then,
1.power on reset: can go to SNK_READY
2."Reboot" reset: can go to SNK_READY
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I15656cf41c5c123efbb7b7c6ee56a5e74b8a21cb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2425792
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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We change Rd_DB to Rd_5.1k in EC hibernate. HW auto asserts Rd_DB
on CCs when EC is power off.
BUG=none
BRANCH=none
TEST=on board reef_it8320 and it8320_evb, in EC hibernate mode:
1.can wakeup by AC plug in, then pd state to SNK_READY.
2.Rd_5.1k power consumption is more 1uA than Rd_DB.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I2d78838c9076dbe36a5d27204207c9da7cad9948
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2423668
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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We change Rd_DB to Rd_5.1k in EC hibernate, so the cc voltage
level won't false trigger chip H1 when there is nothing attached
on c port.
BUG=b:167937680
BRANCH=none
TEST=on board asurada and it81202_evb, in EC hibernate mode:
1.can wakeup by AC plug in, then pd state to SNK_READY.
2.Rd_5.1k power consumption is more 1.5uA than Rd_DB
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: If670e65bfed864ca9b1ca97ee66957a5e11accaa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2413190
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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When all ITE ports are Rx disabled, ITE embedded TCPC does low power
mode in idle_task(), so the CONFIG_USB_PD_TCPC_LOW_POWER didn't
support. Now, there are projects with ITE embedded TCPC and stand
alone TCPC on a board, and stand alone TCPC need the config, so I
add CONFIG_USB_PD_TCPC_LOW_POWER option and only return success,
if TCPM calls.
We should check only ITE active ports rx status instead of totally
ports on board.
BUG=none
BRANCH=none
TEST=on board drawcia and it81202_pdevb:
When CONFIG_USB_PD_TCPC_LOW_POWER is defined,
ITE ports can transit to "LowPowerMode" state and exit in TCPMv2.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I04897d5d86151fc9ca39a802b7cf4f2b76af6f5b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2362372
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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ITE embedded TCPC doesn't support HW auto toggle, but stand alone TCPC
needs the config, so I let function pointer point to NULL, then this
port won't transit to TC_DRP_AUTO_TOGGLE state, if
CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE is defined.
BUG=none
BRANCH=none
TEST=on board drawcia and it81202_pdevb:
When CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE is defined,
ITE ports cc are toggled by TCPM switch unattach.SNK/SRC state
in TCPMv2.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I5c6cd337c7e91c4af7d408d5e631dc74d71de77a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2366417
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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According PD version set HW auto retry count.
BUG=none
BRANCH=none
TEST=on board reef_it8320 and it81202_pdevb,
check the retry count by Lecroy log.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: Ia64950748faab1a684b8b05f49a8a7f17bdc5c9e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340937
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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We are retrying in both the TCPC hardware (4 total) and
in the Protocol layer (3 total) when we do not get a GoodCRC back from
the port partner. We are only suppose to retry up to nRetryCount times
which is 2. This means we should be sending 3 total replies.
Also correct a misinterpretation of the spec around SOP' and SOP"
retries. We were not retrying those packets, but we should be retry them
as the SOP. The SOP' device will not retry, but we (as the SOP) should
retry packet that we are sending to them.
The TCPM is not fast enough to meet the timing for tRetry (195 usec), so
we need to perform the retries in the TCPC hardware layer.
BRANCH=none
BUG=b:150617035
TEST=Verify passing compliance test with GRL-C2 on Trembyle
Change-Id: I55c4ab2f5ce8f64acf21af943862d96d9088622d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2248960
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Implement detect cc disconnection interrupt for source. When TCPC
detect SNK/audio/debug device plug out (cc lines open), TCPC can
interrupt pd task to update cc state.
BUG=b:160548079
BRANCH=none
TEST=test on board reef_it8320, it81202_pdevb with TCPMv1, TCPMv2.
Connect to dongle, adapter and DRP, check
1.Plug in/out interrupt fire correctly.
2.Power role swap can state to SRC_READY and SNK_READY.
3.When partner disconnect, we discharge Vconn within
tVconnOFF(35ms).
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I58bc8a5a9289df4ea4e8b3efec000d3a9ab1cb5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294626
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Implement fast role swap function from initial SNK to new SRC
for chip it8320 and it81202.
BUG=none
BRANCH=none
TEST=1.When we detect FRS cc low signal, we can output properly
GPIO signal.
2.FRS false-positives test: PD traffic(ex.power nego,
data and power swap, soft and hard reset) on the CC line
after FRS is enabled.
Change-Id: I3a7bc6a684e57fb19e50c41305751b2fca1ffe2d
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1786462
Reviewed-by: Diana Z <dzigterman@chromium.org>
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The original get_chip_info() returns a point of point to the chip_info.
This way helps to cache the chip_info to a static variable and the
function just returns the pointer to the static variable.
This static variable has a race condition on the PS8805 chip. The PS8805
chip returns a different PID when the firmware is corrupted, i.e. 0x8803
instead of 0x8805. The !live case fixes the PID, by modifying the static
variable directly. When another task calls the same function for the
live case, the static variable is modified and has a race condition.
This change fixes the issue by changing the get_chip_info() parameter to
a point of the chip_info. The caller has to allocate a buffer in the
stack and pass the address to the function. For the !live case, the
function copies the cache value from the static variable to the buffer.
So the static variable doesn't have a race condition.
BRANCH=None
BUG=b:159588335
TEST=Used ectool to check the PD chip PID 0x8805 (was 0x8803).
localhost ~ # ectool pdchipinfo 1
vendor_id: 0x1da0
product_id: 0x8805
device_id: 0x1
fw_version: 0x0
min_req_fw_version: 0x0
Change-Id: Ic24615af77ea58016d286480572d2a282c4fa09a
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2264477
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Update prototype based on the tcpm_drv definition change in CL:1967932.
BUG=none
TEST=Verify this compiles with a WIP asurada board
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Ib4640ad0d44261c431f6182352012465955e1b31
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2087099
Reviewed-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Add PD driver for chip it8xxx1/8xxx2 series.
BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
(set cc toggle by console cmd):
1.pin configuration
console cmd "gpioget" check gpio settings.
memory dump check cc pin alternate settings.
2.Tx data error handle
Message discard, No GoodCRC, Tx not enable, Timeout
errors happen, corresponding INT will be triggered
then do properly handle.
3.basic pd connection
SNK:connect with adaptor, request max power (15V,3A),
state SNK_READY.
SRC:enable DRP role,
connect with dongle, provide power (5V,1.5A),
source Vconn 5v, get ack of cable discover id,
state SRC_READY.
4.pd module disable
SNK:connect with adapter.
console cmd "hibernate sec", driver disable pd module,
check still connection with adapter via dead battery rd.
And when resume from hibernate, pd init can re-enable
pd module, re-connect with adapter.
SRC:connect with dongle.
console cmd "hibernate sec", driver disable pd module,
check cc pin (not Vconn source pin) volt power down
to ~0v. And when resume from hibernate, pd init can
re-enable pd module, re-connect with dongle.
5.Tx hard reset
console cmd "pd port hard", check hard reset message by
lecroy analyzer.
6.Tx cable reset
check cable reset message by lecroy analyzer.
7.SOP' enable
SRC:connects to SNK via E-mark cable.
Source Vconn successfully, and receives cable's ack
of discover id request.
Not source Vconn to cable, and receives nothing
of discover id request (this isn't effect on
request SNK flow).
8.power role swap
console cmd "pd port swap power", check pd protocol
by lecroy.
Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>
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