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* ec_commands: Rename 'renew' to 'live' in EC_CMD_USB_PD_CHIP_INFOKarthikeyan Ramasubramanian2019-07-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | Semantics of renew field in EC_CMD_USB_PD_CHIP_INFO is changing as follows: 0 -> Return hard-coded info for Vendor ID/Product ID and cached info for the Firmware Version 1 -> Return the live chip info for Vendor ID/Product ID/Firmware Version Also rename the 'renew' field to 'live' to match the new semantics. BUG=b:128820536,b:119046668 BRANCH=None TEST=make -j buildall; Boot to ChromeOS. Change-Id: Ie3dd022336b0be5c9728bb0ebabef32b7a6b5d57 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1617893 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Auto-Submit: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* driver: TCPM: nct38xx: add support for NCT38XX series chipsCHLin2019-04-261-7/+12
| | | | | | | | | | | | | | | | | | | | This commit adds the driver to support for Nuvoton TCPC NCT38XX series chips. BRANCH=none BUG=none TEST=No error for "make buildall" TEST=Apply this and related CLs.Test on a reworked yorp platform with NCTT38XX AIC card. PD Functions including source, sink, and ALT DP mode work fine. Change-Id: Ibd4d3faf29afa55b150971e2aef2587686f523d5 Signed-off-by: Amit Maoz <Amit.Maoz@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1436658 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Ampton: Set the PS8751 to source mode before enter low power modeJames_Chao2019-01-251-0/+1
| | | | | | | | | | | | | BUG=b:113830171 BRANCH=octopus TEST=check the power consumption is lower Change-Id: I527cdc5d1e4dd5de137ab0927e66c171696758ce Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1426306 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: Enable USB PD SOP' and SOP'' CommunicationSam Hurst2019-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, the PD stack ignores messages received from SOP' and SOP'' and this prevents the stack from communicating with VCONN Power Devices and Cable Plugs in general. I propose encoding the message address (SOP*) in the message header. The message header is encoded as a 16-bit value but the TCPC drivers use a 32-bit type for the header. The SOP* address will be stored in bits 31 to 28 of the message header and the PD stack can check those bits to determine the address of the message. BUG=b:122109575 BRANCH=none TEST=manual Change-Id: I2b34c16cae186202c9cf0bc5f940e05151e88cbf Signed-off-by: Sam Hurst <shurst@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1390951 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* pdchipinfo: add min firmware version to pdchipinfoJett Rink2018-09-281-1/+1
| | | | | | | | | | | | | | | | Add a new field to the pdchipinfo host command that exposes the minimum required firmware version that we know about. This will allow factory tests or automated test to compare this version to the current version and fail. BRANCH=none BUG=b:116068318 TEST=with corresponding ectool change, min value is reported correctly Change-Id: Idf338795c3fd6f9f95e51471d0f6a7a422901d52 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1240457 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* pd: Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle()Edward Hill2018-09-171-1/+1
| | | | | | | | | | | | | | | Change tcpm_set_drp_toggle() to tcpm_enable_drp_toggle(), since enable=0 was unused. BRANCH=none BUG=b:111663127 TEST=PD and TCPC low power still work on Grunt Change-Id: I760a067b11984a579261deac856419d46400497b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1194353 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: add TCPC RX circular buffer in ECJett Rink2018-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The alert line for TCPC will stay asserted as long as there are RX messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear all of the RX messages we know about during a single alert handling session. This CL can stand on its own, but it is a part of a CL stack that will tighten the critical section of time between received messages from the TCPC and sending follow up message out through the TCPC. See go/usb-pd-slow-response-time for more details. BRANCH=none BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761 BUG=b:113057273,b:112825261 TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to adversely affect state machine negotiation. Full CL stack consistently sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the 24 ms threshold we need to be under for USB PD spec compliance. Also testing pd_suspend scenario manually and EC was responsive after port 1 suspend because of "bad behavior" Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1185727
* tcpc/mt6370: Fix state debouncing when enable auto-toggling w/o battery.Yilun Lin2018-08-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | mt6370 updates CC pin information to different registers according to whether it is DRP toggling or not. When DRP toggling: CC information will update to CC_STATUS 0x1D When DRP not toggling: CC information will update to ROLE_CTRL 0x1D However, there is a situation that when we are enabling CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE: When we detach the battery, and plug type-c port to boot EC, the type-c port is already connected, before auto-toggling is on. mt6370 here updates CC information to ROLE_CTRL 0x1D, rather than CC_STATUS. So here, we should determine where to retrieve the CC information dynamically. BRANCH=None BUG=b:112113303 TEST=w/ battery: check state transition behaves correctly when sourcing and sinking. TEST=w/o battery: check state transition behaves correctly when sinking. Change-Id: Icf9e39f68aedb43a8fceba5d31795126a433d547 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1177465 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpc: debounce entry into low-power modeJett Rink2018-07-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | We need to keep track of the low-power mode hardware state for each TCPC so we can put a TCPC back into low power mode when it exits low power mode before the software TCPM state machine wants it out of low power mode. This change also breaks the low power mode entry out of the drp_toggle method into its own method: enter_low_power_mode. BRANCH=none BUG=b:77544959 TEST=Verified Analogix does not get into low-power mode loop. Tested other SRC/SNK capabilities as well. Tested the device will go back into low power mode if the AP access the TCPC via the 'ectool usbpdmuxinfo' command. Change-Id: I2fdefeda2bf13c2b79d988f0017629115438d313 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1119255 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ppc: Add tcpci snk/src control via the COMMAND registerScott Collyer2018-04-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | The ANX7447 has a sink/source control lines which can be connected to a PPC. The NX20P3483 PPC requires this control to set it's sink/source switch control. The ANX7447 contols these lines via the tcpci COMMAND register. This CL adds new tcpm_set functions to set either SNK or SRC control via the COMMAND register. BUG=b:77583452 BRANCH=NONE TEST=Tested on port 0 of Yorp with an external charger. Prior to this CL the PPC would remain in standby state because both snk/src control remained low. With these changes, verifed that snk_ctrl is driven high and vbus_sink_enable() function no longer returns an error. Change-Id: Icbea0d3edb63ad19f3d2c76636208497b6939a72 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/996239 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ps8xxx: use custom tcpm_drvCaveh Jalali2017-08-161-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | the ps8xxx family of TCPCs (ps8751, ps8805) have historically used the generic tcpci_tcpm_drv functions, but we need to override some of these entry points because the parade parts need to be woken up before accessing registers. in most cases, this doesn't matter because we access the chip in quick succession where we can "safely" assume the chip is awake -- and the code is structured to implicitly keep the chip awake. the new case we need to address here is where we need to suspend the pd_task and TCPC at an arbitrary point in time. the driver's .release method is called to shut down the chip, and that involves first waking up the chip to be able to access its regs to mask off interrupts, etc. BUG=b:35586896 BRANCH=none TEST=tested from depthcharge - we no longer get errors in the EC console logs about TCPC "release" failed. Change-Id: Ic2a90b71050b3f68c697b1cef48d736ed88b3f41 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://chromium-review.googlesource.com/616460 Reviewed-by: Shawn N <shawnn@chromium.org>
* pdchipinfo: Add option to force renewalDaisuke Nojiri2017-02-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This change adds an option to pdchipinfo command to force ec to get the version from the chip instead of the cache (if it's available). This option will be used after firmware update, which makes the cache value stale. BUG=chrome-os-partner:62383 BRANCH=none TEST=Run ectool as follows: localhost ~ # /tmp/ectool pdchipinfo 0 on vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # /tmp/ectool pdchipinfo 1 on EC result 2 (ERROR) Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/441271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add host command to get PD chip informationDaisuke Nojiri2017-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a host command to get PD chip info. For PS8751, tcpci_get_chip_info will fail if the chip is in low power mode. It can be woken up by reading a random register first then wait for 10ms. This code doesn't have the wake-up read to avoid 10ms delay. Instead, we call this function immediately after the chip is initialized because it'll gurantee the chip is awake. Once it's called, the chip info will be stored in cache, which can be accessed by tcpc_get_chip_info without worrying about chip states. localhost ~ # ectool pdchipinfo 0 vendor_id: 0xaaaa product_id: 0x3429 device_id: 0xad fw_version: 0x15 localhost ~ # ectool pdchipinfo 1 vendor_id: 0x1da0 product_id: 0x8751 device_id: 0x1 fw_version: 0x37 BUG=chrome-os-partner:62383 BRANCH=none TEST=ectool pdchipinfo 0/1. make buildall Change-Id: I3f1667d00ce1826936d90882ada1df6ed6b0ea37 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/433166
* reef: enable tcpc low power modeKevin K Wong2016-11-111-0/+1
| | | | | | | | | | | BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890 BRANCH=none TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/399882 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* reef: enable tcpc-controlled drp toggleKevin K Wong2016-11-021-0/+3
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:54668 BRANCH=none TEST=Verified SNK is detected in S0 (toggle on), S3 (toggle off), and S5 (force sink). SRC is detect in S0 only, stays detected when entered S3, but unplug/plug while in S3 will not re-detect until system back in S0. When go to S5, SRC will get disconnected until back in S0, and hotplug SRC in S5 will not get detected. Checked power role swap with another chromebook in the above scenario also. Change-Id: I2a487fca5cb04c45524aa3efde84fcd10ff0579e Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/396918 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* tcpc: Enable vbus discharge using PD discharge registersKevin K Wong2016-09-131-0/+1
| | | | | | | | | | | | | | | BUG=chrome-os-partner:56040 BRANCH=none TEST=Manually tested on Reef. Used scope to monitor VBUS & it dropped to 0.8V within 650ms. Change-Id: Icaea1dc11a7342a5cc1493d6d3c2ec3408d6d37b Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/367482 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: select dynamically Rp valueVincent Palatin2016-08-251-0/+3
| | | | | | | | | | | | | | | | | | | | | Add API to switch the Rp pull-up value on CC dynamically at runtime. This is a preparatory work for boards having a more complex maximum source current policy (eg 2 ports sharing a common pool of power). For fusb302, update the voltage thresholds for open/Rd/Ra as they depend on the Rp (was missing from the previous change). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:56110 TEST=make buildall Change-Id: Id3c24a31a16217075a398ec21ef58ee07187a882 Reviewed-on: https://chromium-review.googlesource.com/373501 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: tcpci: Properly get / set mux polarityShawn Nematbakhsh2016-06-281-4/+5
| | | | | | | | | | | | | | | | | | | CONFIG_STANDARD_OUTPUT bit 0 on the TCPC is used to indicate connector orientation flipped status. BUG=chrome-os-partner:53502 BRANCH=None TEST=Manual on amenia / reef. Verify USB3 drive is properly detected as SuperSpeed for either polarity. Change-Id: I707e46064cbf0f89b3098c850b1cee55c9fead58 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/355670 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* elm: anx7688: add anx7688 hpd driverRong Chang2016-06-161-0/+18
| | | | | | | | | | | | | | | | | | | | ANX7688 is a TCPCI compatible port controller with HDMI to DP converter. The HDMI converter needs a reset every time after enabling its function. BRANCH=none BUG=chrome-os-partner:52815 TEST=manual boot elm proto plug and unplug dingdong and check DP output plug/unplug adapter and check pd 0 state Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com> Reviewed-on: https://chromium-review.googlesource.com/340371 Commit-Ready: Koro Chen <koro.chen@mediatek.com> Tested-by: Koro Chen <koro.chen@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tcpm: update code to support multiple tcpm driverKevin K Wong2016-04-171-0/+3
| | | | | | | | | | | BUG=chromium:593822 BRANCH=none TEST=make buildall Change-Id: Ic30c1b890da7639aa80a53040ecc5bebfb4be2e8 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/336030 Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpc: add support for TCPC with integrated high-speed muxesVincent Palatin2016-01-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The TCPCI specification defines ane optional register 18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way of steering the high-speed muxes. Implement the feature as a usb_mux_driver, under the conditional flag CONFIG_USB_PD_TCPM_MUX. The USB PD port index should be set in the port_addr field of the 'usb_mux' structure. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:49605 TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP muxing. Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5 Reviewed-on: https://chromium-review.googlesource.com/322956 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpc: re-initialize tcpc if it reboots while tcpm is runningAlec Berg2015-10-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | On TCPC startup, set an alert to notify TCPM that we have been reset. When TCPM gets this notification, it should re-send initial TCPC parameters. If we were in a stable contract as a sink, make sure we don't reset connection. If not, then reset PD protocol state machine to the default state. This fixes a bug where if the TCPC reboots while the TCPM is still running, then the TCPC would not get re-initialized and therefore no PD communication would not work. This also fixes it such that if we are in a stable contract as a sink and the TCPC reboots, then we don't lose power. BUG=chrome-os-partner:46676 BRANCH=none TEST=tested on glados. reboot PD MCU with and without a charger plugged in and verify that PD communication works after the reboot. verify that with a charger, we don't lose power. also tested with a hoho plugged in during reboot. Change-Id: I84fec4577b0daf5891bd8461d3f3d925014a5ecf Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307187 Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpc: update to tcpci RC3Alec Berg2015-09-161-25/+39
| | | | | | | | | | | | | | Update TCPCI to match specification version RC3. BUG=none BRANCH=none TEST=tested on glados and samus by plugging in a zinger with both polarities and verifying we make a power contract. Change-Id: I9cd6d8db7b7149995847ec1b071fba1f4d4cd5a3 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299713 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Enable detection of VBUS via the TCPM/TCPCI interfaceScott2015-08-211-0/+1
| | | | | | | | | | | | | | | | | | | | | Modified TCPC layer to utilize the Power_Status and Power_Status_Mask registers. VBUS status is stored in Power_Status and when a change is detected, it's communicated to the TCPM via the ALERT# line. BUG=chrome-os-partner:43440 BRANCH=none TEST=Tested the feature on Glados and Oak connecting to both Ziger and Samus. Verfied that VBUS status is communicated via the TCPCI and that PD contracts are established without using the VBUS_WAKE GPIO lines on Glados and Oak. Change-Id: Ie5aa32eecc887f3cb00880a285f1e710b7064384 Signed-off-by: Scott Collyer <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289931 Reviewed-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* tcpc: move tcpc initialized bit into error status registerAlec Berg2015-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | Move TCPC initialized bit from alert register into error status register. This is not part of the TCPCI spec, but the existing code creates a bug that if TCPM reboots without TCPC also rebooting, then we will never get the initialized alert from TCPC since it has already happened, so the TCPM will loop indefinitely waiting for TCPC to be ready. This fixes the bug by moving the bit to a status register, which is more appropriate. BUG=none BRANCH=none TEST=load on glados, reboot and make sure TCPM see's that the TCPC is initialized. Change-Id: I8e96b59031e01a4faec8f519727df1fa95f498bc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288342 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpc: update TCPCI register mapAlec Berg2015-07-241-10/+9
| | | | | | | | | | | | | Update TCPCI register map to match version 0.64 of spec. BUG=none BRANCH=none TEST=load on glados, test can make power contract with zinger. Change-Id: I62e6428b5836aeb018fa7b4f38b6f3b419aed0c6 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288341 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpc: update tcpci registers to latest specAlec Berg2015-06-301-24/+28
| | | | | | | | | | | | | | | Update TCPCI registers to version 0.62 of PD Interface specification. BUG=none BRANCH=none TEST=test on glados and samus Change-Id: I57338b385123371e90f3b79b84e652af15be1bf1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/282067 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: refactor tcpm and move alert function to tcpm driverAlec Berg2015-06-301-0/+85
Refactor the tcpm/tcpc split such that the tcpm driver implements the alert functionality since it may be unique for different tcpc chips. BUG=chrome-os-partner:41842 BRANCH=none TEST=make -j buildall. run on samus and glados. Change-Id: I23f2d7f8627d5337b8d001a09bf27622be24fe33 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/281631 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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