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* rt1718s: fix incorrect alert methodTing Shen2021-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | rt1718s driver incorrectly used the common alert function instead of its own implementation. This bug was not detected by `make buildall` because no one actually enables rt1718s until CL:2793783. BUG=b:177391887 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I303cb0b6b7d0177648871ea36c1fc5c513fbb336 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058082 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* ppc/rt1718s: notify charger task about vbus changeTing Shen2021-07-291-8/+9
| | | | | | | | | | | | | | | | | | | PPC driver is responsible to notify charger task about vbus change. Original driver didn't implementation this. Also make BC1.2 driver correctly enables BC1.2 detection on vbus change. BUG=b:192422592 TEST=manually verify PD and BC1.2 works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I0bcbe0a1a43d9a9bcae61d69e247829648dd0d7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045249 Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* raa489000: Wait 853us before checking VBUS at initwangganxiang2021-07-201-0/+2
| | | | | | | | | | | | | | | | | According to the RAA489000 manual, extend the time to read the vbus after the ADC initialization is completed. BUG=b:193402296 BRANCH=keeby TEST=make BOARD=cappy2 pass Signed-off-by: jesen <wangganxiang@huaqin.corp-partner.google.com> Change-Id: Ie326932a9a5d3849e31e15a090074ad1274a7266 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3023762 Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* rt1718s: implement low power modeTing Shen2021-07-202-1/+18
| | | | | | | | | | | | | | | enable low power mode to further decrease power consumption. BUG=b:192815893 TEST=manually measure power BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ib5d22d1d3c9cc8ed644075b8ed239f96d0eea67e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004127 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* TCPC: add flag to disable debug accessory controlBoris Mittelberg2021-07-131-0/+2
| | | | | | | | | | | | | | | | | The NCT38xx TCPC takes over the GPIO we otherwise use to control the Burnside Bridge on Brya P1 devices. To get the BB out of reset we add the flag to tcpc_config structure to take the control back to TCPM. BRANCH=none BUG=b:191516281 TEST=running deployment in the lab; running FAFT PD test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I73ddf26964cc6363640ddd80fbcbf353704d3198 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3016406 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* driver/tcpm/ite_pd_intc: separate pd interrupt to ite_pd_intcRuibin Chang2021-07-094-16/+134
| | | | | | | | | | | | | | | | | Separate pd interrupt functions to ite_pd_intc for easier maintenance on cros_ec and zephyr. And enable PD interrupt functions for zephyr. BRANCH=none BUG=none TEST=1.can zmake hayato and make asurada 2.PD port functions work on board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* NCT3807: Set up correct FRS enableDiana Z2021-07-071-1/+23
| | | | | | | | | | | | | | | | | | | | | The NCT3807 requires a few steps for FRS enablement. Specifically: - Zero out VBUS_SINK_DISCONNECT_THRESHOLD - Enable FRS interrupt (already done in TCPCI code) - Set FRS enable to 1 Note that it should not use the TCPCI specification method of clearing AutoDischargeDisconnect as soon as FRS is set. This results in the CC lines immediately reading as Open. BRANCH=None BUG=b:183586640,b:192012189 TEST=on guybrush C0, confirm FRS can execute successfully with WooHubs, HooToo, and Moshi Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ida0d33ae9ce4b8660615a0b9f3064cf90f5ae3bd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987598 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* nct38xx: Avoid LPM exit when not alertingCaveh Jalali2021-06-251-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids taking an nct38xx port out of low power mode when it is not alerting. The nct38xx chips exit low power mode when they assert Alert. This means we don't have to explicitly take the port out of LPM to check its Alert status register. So, directly access the Alert register to check if the associated port was the source of the Alert. The nct3808 is a dual port chip with a single Alert pin. We need to be careful when servicing Alerts because the usual tcpc_read(), et. al. functions are wrappers that take the port out of LPM mode. When this happens, the nct3808 generates a CC status change alert on a disconnected port. Servicing this "phantom" Alert causes the other port to similarly generate a "phantom" alert. These CC status Alerts can effectively oscilalte between the two ports for a long time. BRANCH=none BUG=b:191531291 TEST=brya no longer gets into ALERT loops on C0/C2 Change-Id: Ib4be6b49a98f3053e5639477e8651b6ba487a0f9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977473 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPM: Add new LPM bypass TCPC accessorsCaveh Jalali2021-06-251-2/+7
| | | | | | | | | | | | | | | | | | | | This adds a set of light-weight TCPC register access functions for special cases where the caller arranges for the TCPC to be accessible and the complexity of fully taking a TCPC out of LPM mode is not desirable. A typical use case is for alert service routines to be able to peek at a TCPCs alert register to determine if further processing is requested. BRANCH=none BUG=b:191531291 TEST=buildall passes Change-Id: Ib5c9add95f04be311315808168b070793b51cb24 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2986601 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* ps8xxx: Add board_ps8xxx_tcpc_init methodDevin Lu2021-06-252-0/+13
| | | | | | | | | | | | | | This patch adds method to allow boards to customize with ps8xxx tcpc initial. BUG=b:189587527 BRANCH=firmware-volteer-13672.B-main TEST=make buildall Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I0c160eb140500847505a367af08b3d2e82cbbec5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2972022 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* ps8815: Add displayport related settingsDevin Lu2021-06-251-0/+21
| | | | | | | | | | | | | | This patch adds one more register for displayport related settings with ps8815. BUG=b:189587527 BRANCH=firmware-volteer-13672.B-main TEST=make buildall Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: If79dce87a581923bb1f382786042018bc37c737a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2972021 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* RAA489000: Take sinking into account during debug detachDiana Z2021-06-241-3/+8
| | | | | | | | | | | | | | | | | When detaching from debug accessories, we need to set the CC lines to Open which may cause a loss of Vbus. However, if the port isn't sinking Vbus, then it should be okay to run this detach regardless of our current battery level. BRANCH=None BUG=b:191465743 TEST=on blipper, run the battery down with servo_v4 attached and observe the DUT can be woken normally by a charger on C0 after hibernate Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I5f946b23607c0bb3936132e93355875ff5688b30 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2983694 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rt1718s: set OVP to 23VSue Chen2021-06-232-0/+14
| | | | | | | | | | | | | | Set VBUS_VOL_SEL to 20V (4'b1111). BUG=b:191609106 BRANCH=none TEST=boot up system by plugging in adapter to typc port 1 with battery on Cherry dut. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: If3c3a82b2e0dbcecb1adaa62cb5d8ade4bae1942 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977866 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: tcpm: Update ITE driver to support zephyr namesSimon Glass2021-06-221-0/+16
| | | | | | | | | | | | | | | There is a name mismatch with some of the registers needed in this driver. Use #define for now until we can change these in ECOS, or remove the ECOS code. BUG=b:189855648, b:190860075 BRANCH=none TEST=with other CLs, build asurada for Zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I73da708c6e876db092b345ff7e0b28d99960b4d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2957548 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Fix compilation issues with nocturne SDKPatryk Duda2021-06-171-2/+6
| | | | | | | | | | | | | | | | | | | | | Compiler in nocturne cros SDK doesn't allow for variable declaration inside for loop. This patch removes variable declaration inside for loop in code which is used by nocturne board. This patch doesn't introduce any logical changes. BUG=b:160676144 BRANCH=none TEST=Make sure EC points to commit on cros/main. On nocturne SDK: cros_workon-nocturne start chromeos-ec emerge-nocturne chromeos-ec chromeos-bootimage Make sure that firmware compiles Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* NCT38xx: Add notification for chip resetDiana Z2021-06-162-0/+15
| | | | | | | | | | | | | | | | An external reset of the chip will reset some information we've gathered from that chip. Notify the driver so stored information may be reset as well. BRANCH=None BUG=b:183660105 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib3335cf2984f2b13bbed7cacee603ba47edd2a51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953875 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* NCT38xx: Export boot type informationDiana Z2021-06-162-11/+31
| | | | | | | | | | | | | | | Outside code may need an understanding of our board's boot type, so allow it to be exported from the driver. BRANCH=None BUG=b:183660105 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Iec61872be283f9ef65ccf71e99d89cee7184f2f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953874 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* gingerbread: Use CONFIG_USB_PD_VBUS_DETECT_TCPC for C1Scott Collyer2021-06-161-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL changes the stm32gx TCPM driver to allow CONFIG_USB_PD_VBUS_DETECT_TCPC to still be defined on boards that also use the stm32gx TCPM driver. This is required for gingerbread which has a PPC on C0 for VBUS detection, but relies on the TCPC to detect VBUS on port C1. BUG=b:159330563 BRANCH=quiche TEST=validated that can attach as SRC/DFP on C1 > pd 1 state Port C1 CC2, Enable - Role: SRC-DFP-VC TC State: Attached.SRC, [10.435540 C1: PE_SRC_Ready] [10.436511 pin_mode: 4, mf: 0, mux: 2] [10.442645 C1: PE_VDM_Request_DPM] [10.470346 C1: Entered DP mode] [10.470480 C1: PE_SRC_Ready] Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I986d504b1306c02132869abe7cbd630a966e0acd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949954 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ps8805: Add driver method to set/get GPIO signalsScott Collyer2021-06-162-0/+90
| | | | | | | | | | | | | | | | | The PS8805 has 3 GPIO signals which can be controlled by the EC with I2C register accesses. This CL adds functions to both set and get a one of the 3 PS8805 GPIO signals. BUG=b:159330563 BRANCH=quiche TEST=verified on gingerbread that VBUS control is functioning. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I1ef688e713ea84d2b0c6a6c23385fe6afb4f96b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953868 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* raa489000: vbus_mv should greater than 3900mvMike Lee2021-06-091-1/+1
| | | | | | | | | | | | | | | | We need to add a condition for vbusmv to avoid that when the vbus_mv value is small but not zero vbus_mv, it is still considered as an adapter and open asgate. BUG=b:189090988 BRANCH=dedede TEST=make BOARD=storo Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: Ic046e65ed69f8616d6bc7d8ca28fc27cf894ed07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949627 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* Create a public header for it83xxSimon Glass2021-06-091-5/+2
| | | | | | | | | | | | | | | | | | | Add a separate public header for this chip so we can include it from Zephyr. Drop the #ifdef since the linker will give an error if the function is missing. BUG=b:189855648 BRANCH=none TEST=make BOARD=hayato -j30 Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: Ic4c755da2b576d6cd3465cfd803dfb0e4ad0fbef Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2941810 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org>
* COIL: Update RT1718S address defineDiana Z2021-06-081-1/+1
| | | | | | | | | | | | | | Update RT1718S address define to match current i2c naming conventions in the codebase. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ieed8871d02185a55335fa2e1ebe87d40a5cb6fac Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2946315 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TCPCI: Add OCP reportingDiana Z2021-06-071-1/+14
| | | | | | | | | | | | | | | | | If a TCPC supports OCP and the TCPC has reported OCP in its fault register, assume we should report this to the OCP module. Additionally, enable fault alerts for all TCPCI TCPCs. BRANCH=None BUG=b:174334068 TEST=on galtic, verify OCP events are reported when current is overdrawn Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I1a13b4a0869d8917f8660fd356d43c28e0e43814 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923237 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* IOEX_CCGXXF: Add 1.8V level GPIOs supportIurii2021-06-031-0/+2
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=Tested voltage levels on CCGXX validation platform Change-Id: Ibc8f0dc05ac4351e96d9479a99227633742ec7bc Signed-off-by: Iurii Berezhanskyi <iurii.berezhanskyi@infineon.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891837 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* NCT38xx: Set debug accessory control conditionallyDiana Z2021-06-011-4/+35
| | | | | | | | | | | | | | | | | | | | If we've booted in dead battery mode with a debug accessory connected, then changing the TCPC_CONTROL.DebugAccessoryControl bit will result in a significant delay to detecting the CC line state. Track our boot type and use it plus the presence of a debug accesssory to determine if we'll change this bit. BRANCH=None BUG=b:186799392 TEST=on mancomb, boot and reboot with servo_v4 power only and ensure we detect the CC lines correctly with no dealy. Also plug in servo_v4 with BJ power attached first to ensure we set the debug accessory control bit correctly and verify we can PR swap back and forth. Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I5bcdee1de61ed198cab82bae1ab6ac5996b9e80b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919942 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rt1718s: implement BC1.2 driverTing Shen2021-06-012-1/+264
| | | | | | | | | | | | | BUG=b:177391887 TEST=manually BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I250c33c8e7c433679fa3a2fcc31e0c59656190e8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2880133 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* driver/tcpc: implement rt1718s tcpc/ppc driverTing Shen2021-06-012-0/+227
| | | | | | | | | | | | | BUG=b:177391887 TEST=none BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I8f017e21b74c1e27ca7f257b76b0ef74fd0343f2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2639734 Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* TCPCI: Move debug accessory control set to NCT38xx driverDiana Z2021-05-272-12/+13
| | | | | | | | | | | | | | | | | | | This debug accessory control setting was initially added to the TCPCI driver to support the NCT3807, but now should move into the NCT driver since it will need to be conditional on specific register conditions. Note that NCT is the only driver currently implementing the debug_accessory driver field, so it's not expected to affect other TCPCs. BRANCH=None BUG=b:186799392 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id5832c474378a3f8735c6c72c5535ddb5d9229d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919940 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* CCGXXF: Enable Auto Discharge DisconnectIurii Berezhanskyi2021-05-261-0/+2
| | | | | | | | | | | | | | | | | | Enable Auto Discharge functionality in TCPM driver by hooking tcpci_tcpc_enable_auto_discharge_disconnect() wrapper into tcpci_tcpm_drv structure. BUG=none BRANCH=none TEST=Tested on ADLRVP, USB4 with TCPCI works as expected Change-Id: I87af20b031ce58e74f9fa7e9b4a8b5eee0002d72 Signed-off-by: Iurii Berezhanskyi <iurii.berezhanskyi@infineon.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914973 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
* dedede: Rework `extpower_is_present()`Aseda Aboagye2021-05-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The dedede boards erroneously assumed that if VBUS was present, then "extpower" was present. "extpower" is generally connected to the ACOK signal for the battery charger IC. It indicates that the voltage present at the switching node is valid for bucking or boosting. For our Type-C systems, this needs to be at least 4V. However, just because VBUS is present doesn't mean that the voltage is present at the switching node. The FETs on the selected charge port needs to be enabled first. This commit simply changes the logic to check the battery charger ICs' ACOK status to reflect whether extpower is present. BUG=b:187965740 BRANCH=dedede TEST=Build and flash drawcia and madoo, verify that "AC on" prints are emitted when the charge port is selected and not just when VBUS appears on the port. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If5a4a10d502f2f08ccf1d3228e42f48fa6d45909 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2901254 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* raa489000: enable adc functionMike Lee2021-05-131-10/+31
| | | | | | | | | | | | | | | | | Enable adc function so that We can quickly get the bus voltage. and move clear ADC bit after charger_get_vbus_voltage to reduce power consumption BUG=b:178981107,b:178728138 BRANCH=dedede TEST=storo can keep asgate not drop with ac only TEST=sasukette can keep asgate not drop with AC only Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: I39db6f80a5439dbd890c788981796165abb49415 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2890492 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* I/O Expander: Add CCG6XX driverVijay Hiremath2021-05-051-0/+44
| | | | | | | | | | | | | | | Cypress CCGXXF PD has built-in I/O Expander, added driver to enable GPIO functionality. BUG=none BRANCH=none TEST=Tested on ADLRVP, ioexget & ioexset works as expected Change-Id: I8503178703ad166ac77e96d1990133c88169d23a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2853143 Tested-by: Svyatoslav Paliy <svpaliy@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ps8xxx: Handle null pointersCaveh Jalali2021-04-301-1/+9
| | | | | | | | | | | | | | | This adds a null pointer check to prevent undefined behavior. Also, add check for board_get_ps8xxx_product_id() returning an error. BRANCH=none BUG=b:186189039 TEST=buildall passes Change-Id: I40f5836528e9beaabac27d39ef6dd25013b9302c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2857795 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* raa489000: Check VBUS ADC over POWER_STATUSAseda Aboagye2021-04-291-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to boot without a battery, we need to send the SinkVBUS command to the TCPC as soon as possible once we are aware. Previously, we were checking the TCPC registers, however since this is being done in the TCPC init, the TCPC registers weren't initialised yet so we couldn't really use this field. However, this part is a combined TCPC and charger IC, therefore we can use the charger IC-side APIs to check if VBUS is present. This commit simply checks the VBUS ADC register over consulting the POWER_STATUS TCPC register. BUG=b:178728138,b:178981107 BRANCH=dedede TEST=Build and flash madoo, unplug battery, verify DUT can boot up from either Type-C port with a 45W PD charger. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: I4801fcd2655a65e74dc8feddc06e369635a2ce34 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848245 Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Coachz:PS8XXX: Add 5ms delay to make CC being judged correntlytongjian2021-04-271-0/+10
| | | | | | | | | | | | | | | | | | | This may be a PS8XXX firmware issue, Parade is still trying. BUG=b:185202064 TEST=emerge-strongbad chromeos-ec 0. Insert the Dock to the typeC ports and shutdown the devices; 2. Press powerbutton and poweron the unit; 3. Use lsusb command, list can not find the Dock information; 4. Can find the Dock. BRANCH=Trogdor Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: Ib667df88549fc9e4f0e4603574af5d70ef326e11 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847867 Reviewed-by: Rock Chiu <rock.chiu@paradetech.corp-partner.google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* raa489000: Sink VBUS before switching to TCPC sideMike Lee2021-04-231-1/+1
| | | | | | | | | | | | | | | | | Modify start sinking VBUS condition. in the first initial state, the power status is in the uninit state. BUG=b:178728138 BRANCH=dedede TEST=build and flash sasukette, remove battery, plug in 45W charger, verify that DUT can boot up. Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: Id7223474046528ebece0e1267ec56d1c4d148f41 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847866 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Cleanup: Get Sink & SRC state from PD or PPCVijay Hiremath2021-04-212-22/+9
| | | | | | | | | | | | | | Added option to get the Sinking or Sourcing state from either PD or PPC. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ibb21ef69b5825ea5722ceacd5d7ef6f535aad17c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2838127 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* raa489000: Sink VBUS before switching to TCPC sideAseda Aboagye2021-04-211-15/+15
| | | | | | | | | | | | | | | | | | | | When the RAA48900 switches from charger IC control to TCPC control, it will disable the ASGATE. In cases where the board is booted without a battery, this can cause a loss in VSYS. This commit has the board attempt to sink VBUS if it's present prior to switching the part to TCPC control. BUG=b:181712325 BRANCH=dedede TEST=Build and flash galith, remove battery, plug in 45W charger, verify that DUT can boot up. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Id5b3269911d3b8222b28886f66ef724e3e82c637 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829115 Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* TCPC/PPC: Add code for Cypress EZ-PD CCG6DF, CCG6SFVijay Hiremath2021-04-201-0/+17
| | | | | | | | | | | | | | | | | | | | | | CCG6DF and CCG6SF are dual-port and single-port USB Type-C controllers respectively. These can act as either PD or TCPC based on the Phy firmware flashed on the internal flash. These chips use standard TCPCI driver. BUG=none BRANCH=none TEST=With the initial Phy F/W able to test following on ADL RVP 1. Single port Type-C is validated 2. Dead battery boot 3. Source & Sink path 4. SOP* 5. USB, DP, TBT 6. 100K, 400K, 1MHz I2C Change-Id: I1b1a2f759139ac1c7aab42d851b8a7866664e28a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2551653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Cleanup: Enable PPC from PD or Power MUXVijay Hiremath2021-04-207-8/+12
| | | | | | | | | | | | | | | Some PD chips have integrated SRC FET and control the SRC/SINK FET from GPIOs hence cleaned up the code to enable Power Path Control from either from PD or from Power MUX. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I77f96b681fd2e5fca35bce425e4bd5ec87d5ccfd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2828980 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* raa489000 : clear 'Enable ADC' bit on port 1YongBeum.Ha2021-04-151-9/+10
| | | | | | | | | | | | | | 9mW is reduced on S0iX power consumption by clearing 'Enable ADC' bit. BUG=b:178356507 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I585ce87bf778f8386edfe8ccaaf1aa53f0374eff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2801175 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Export even more symbols from ps8xxxSimon Glass2021-04-131-9/+0
| | | | | | | | | | | | | | | | | It turns out we need more symbols for some boards, such as when the board_get_ps8xxx_product_id() function is implemented. Export some more things. BUG=b:183296099 BRANCH=none TEST=make BOARD=lazor -j30 Build lazor on zephyr Change-Id: Iccef72582f6033a1a34abe28a636ebe254f1bd5a Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822390 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* Revert "RAA489000: Clear debug accessory state on init"Diana Z2021-04-071-15/+0
| | | | | | | | | | | | | | | | This reverts commit 756dc91b0a57aa6d557ee4cb486972d8a7b8106a. There will now be a general debug detach on entry to Unattached.SNK/SRC every boot and so this should no longer be necessary. BRANCH=None BUG=b:177870522 TEST=on galith, ensure that refresh+power resets with servo_v4 sink plugged in results in a successful connection with the servo_v4 Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I991ca7fbb5d51d2d8fc07d3a8d8e885e43e94b44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2792691 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* RAA489000: Check battery level in debug detachDiana Z2021-04-071-0/+5
| | | | | | | | | | | | | | | Since our debug detach routine requires setting our CC's to open, we may end up losing Vbus. Protect ourselves by checking the battery level prior to allowing this to be set. BRANCH=None BUG=b:183619502 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I45acb7bce2f9a312c2f35ec74dc4563a947ee059 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2792689 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32gx: ucpd: BIST mode control and correct nRetryCountScott Collyer2021-03-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This CL implements the driver method to enable/disable BIST test mode in the ucpd driver. When this mode is enabled, the upcd driver only needs to send GoodCRC messages in response to BIST data messages which are received. This CL also fixes the value of nRetryCount to make it based off the port partner'd USB-PD version. BUG=b:181179550 BRANCH=None TEST=Manual Verified that nRetryCount fix enables TD.PD.LL.E3. Soft Reset Usage to pass. Verfied that adding BIST mode control enables TD.PD.PHY.E1. BIST Test Data to pass. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I251e1c3c235d976d934406cdb22df0c177c6f14b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2667241 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* Revert "ps8815: delete CONFIG_USB_PD_TCPM_PS8815_FORCE_DID"Zhuohao Lee2021-03-251-0/+45
| | | | | | | | | | | | | | | | | This reverts commit e2761c8be4571adcfc425a9187290872ffa9d02d. In order to support the old TCPC chip which bcd revision is smaller than 0x7, we need to bring back the CONFIG_USB_PD_TCPM_PS8815_FORCE_DID and force the TCPC firmware be updated in the factory line. BUG=b:177251013, b:159289062, b:182018599, b:178978970 BRANCH=firmware-volteer-13672.B TEST=the old TCPC chip can update its firmware. Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: I66d12aee569137cc7823a186e3251ca8b187e767 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784327 Reviewed-by: Keith Short <keithshort@chromium.org>
* ucpd: Add support to turn off type-2 BIST modeScott Collyer2021-03-161-0/+15
| | | | | | | | | | | | | | | | | | | This CL adds changes to the ucpd driver to support turning off BIST mode once it's been started. For ucpd, the peripheral has to be disabled and reset for this purpose. BUG=b:182436876 BRANCH=None TEST=Verfied that honeybuns can pass TDA.2.1.1.1: BMC-PHY-TX-EYE compliance test, which previously was failing because BIST type-2 mode was not being stopped. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ib6aa898ef5727dd5887e5d1c0b2eee94fdb366b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2751328 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* Raa489000: Set Vbus Target Voltage lowerMike Lee2021-03-102-1/+2
| | | | | | | | | | | | | | | Set Vbus Target Voltage lower,so that meet power noise test. BUG=b:181801175 BRANCH=dedede TEST=test power noise pass, meet spec 4.75V--5.25V Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: I7aa137b37acc678dfbba76d8e72733b8196f8c41 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2745181 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* RT1715: Reset on EC reboot instead of POREric Herrmann2021-03-091-7/+6
| | | | | | | | | | | | | | | | | | | | Currently we reset the RT1715 only when it is coming out of power-down mode; however this requires explicitly putting it into power-down mode or a full power cycle. An EC reboot will not power cycle the TCPC though, and we really should be doing the reset following an EC reboot. Do a soft_reset the 1st time we initialize the TCPC following an EC reboot. Don't check the power-down bit. BUG=b:179234089 TEST=Write to unused vendor registers such as 0x99; check that the values are reset when "reboot" is used to reset the EC. BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I0cc05ac88ec1314c20ceb357605156292b57b7c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698779 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* RAA489000: Clear debug accessory state on initDiana Z2021-03-041-0/+15
| | | | | | | | | | | | | | | | | | | | | | During our first boot, clear out any residual state left from past debug accessory connections. In most cases, the TC state machine or PD task init can set open in order to ensure the TCPC doesn't get wedged. However, there is still a lingering corner case when the EC is reset through the security chip on ITE platforms. Always set open during init if we have the power to survive it to catch this case. BRANCH=None BUG=b:177870522 TEST=on galtic, run refresh+power resets with servo_v4 sink plugged in and verify the port does not become stuck. Also run refresh+power resets with a charger and hub plugged in to verify they connect fine after the reset. Also verify battery-less boot still works Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ia25959cae4d42163ac03280a319d785193e29422 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2733916 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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