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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-0534-12866/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* SSFC: Framework to support two charger sourcesParth Malkan2021-09-241-14/+21
| | | | | | | | | | | | | | | | | | Many platforms have requirements to support more than one charge source (eg. pirika). It can't be supported by just enabling two different CONFIGS as that can lead to conflicts. Eg.USD_PD_VBUS_DETECT_TCPC vs USB_PD_VBUS_DETECT_DISCHARGE. This change provides a framework that supports two different charger sources in the same build. Please see the CL for relevant logs. BRANCH=None BUG=b:194375840 TEST=make -j buildall Signed-off-by: Parth Malkan <parthmalkan@google.com> Change-Id: I309cc5930233983e615d90a4290fc749abf7aa2d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088232 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver/tcpm/it83xx: turn both cc pins off when disable VconnRuibin Chang2021-09-241-9/+17
| | | | | | | | | | | | | | | | | | | | | If the pd port has previous connection and supplies Vconn, then RO jumping to RW reset the system, we never know which cc is the previous Vconn pin, so we always turn both cc pins off when disable Vconn power switch. BUG=b:199461325 BRANCH=none TEST=on board haboki, RO jump to RW, check Vconn low and pd can nego Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I526af287d3f52ca27c38f342553aac9b3a241d84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3178341 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Tested-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Commit-Queue: Diana Z <dzigterman@chromium.org>
* driver/tcpm/it8xxx2: turn both cc pins off when disable VconnRuibin Chang2021-09-241-7/+16
| | | | | | | | | | | | | | | | | | | | | | | | If the pd port has previous connection and supplies Vconn, then RO jumping to RW reset the system, we never know which cc is the previous Vconn pin, so we always turn both cc pins off when disable Vconn power switch. This change is leveraged from it83xx (CL:3178341), although Vconn is controlled by ppc on asurada series and asurada series don't happen the bug, but we still need this change for the future that if there is a project control Vconn by GPIO. BUG=none BRANCH=none TEST=make board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I66e7961d5ba412c18948a433103c17b79e7c5e08 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3180703 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* ccgxxf: Add correct I2C address flagsstabilize-14235.B-mainVijay Hiremath2021-09-221-2/+1
| | | | | | | | | | | | | | | | CCGXXF exposes I2C addresses 0x0B for 1st port & 0x1B for second port hence corrected the I2C address flags in header file. BUG=none BRANCH=none TEST=Able to initialize second Type-C port Change-Id: I9dc955d1035b1f488e92a47cdac49bdd6154f4ae Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172253 Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* ps8xxx: Add support for ps8815 A2 with bad FWCaveh Jalali2021-09-211-0/+7
| | | | | | | | | | | | | | | | This adds the low level chip ID of the ps8815 A2 so we can recognize the chip when its main firmware is inoperative. BRANCH=none BUG=b:186189039 TEST=with next patch in series, verified the brya EC reports the correct device ID when the firmware is corrupted. Change-Id: I2696b9c20fdefd8afd02f7394a45f1c4c5636d71 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2857796 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* rt1718s: refactor: move gpio control to driver moduleTing Shen2021-09-142-6/+74
| | | | | | | | | | | | | | | | | | | | This CL moves RT1718S gpio control from board file to common driver codebase, and implements the set flag and get/set level functions. Note that this CL does not fully implement IOEX interface because TCPC has different init process than usual ioexpanders. BUG=none TEST=1) pass faft_pd 2) manually test pd source/sink/frs on port 1 BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: If2a0bca2b13ad4748eea54b4c8004da7dc6fc6a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3159643 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* tcpm/rt1718s: fix race condition between tcpc_init and usb_chg taskTing Shen2021-09-091-3/+0
| | | | | | | | | | | | | | | | | | | | | Two different functions controls the BC12_SNK_FUNC register, one is bc12_init, another one is usb_charger_task. This causes a racing condition happens during EC soft reset: bc12_init resets the BC12_SNK_FUNC register to its initial value when usb_chg task starts bc1.2 detection. To solve this, let usb_chg task has full control of the register. BUG=b:199226158 TEST=bc1.2 detection works after ec soft reset. BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ie423e2d9ddad1e1fadb97e1b73b8b5e535121601 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3147512 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* tcpm: Mitigate EC RX circular buffer overflowNathan K2021-09-031-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | There are two FIFO buffers for USB-PD packet reception. One is located in TCPC, another was added in EC layer in crrev/c/1185727 . There are scenarios that may lead to overflow. In these scenarios, the EC RX circular buffer overflows without clearing the TCPC ALERT# signal. This in turn results in a tight-loop in the TCPC interrupt handler, leading to port "suspend". This CL is a reduced hotfix to mitigate this scenario. Further CL is needed to perform proper TCPCI spec-compliant overflow handling. BRANCH=none BUG=b:192382194 TEST=1. Connect CB282K via DP to G5 dock on old FW 2. Connect G5 dock to AKEMI on TCPMv1 3. Allow MST VDM:Attention communication to occur 4. Observe EC console prints via SuzyQ Change-Id: Ic579a3763fc595b8250d4ca78c3942675450295a Signed-off-by: Nathan K <nkolluru@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3135041 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ps8xxx: Fix PD task hang if PS8xxx device is missingKeith Short2021-09-021-2/+3
| | | | | | | | | | | | | | | | | | | | CL:3084331 added logic to retry reading the PS8xxx FW version register to ensure the chip has woken up from low power mode. If the PS8xxx device is damaged/missing, there was an unbounded loop so the initialization never completed, hanging the corresponding PD task. BUG=b:198619831 BRANCH=none TEST=Verify herobrine boots AP when the battery and right I/O board are disconnected. Also observe "LPM recovery failed" reported on the console for the missing type-C port. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I578f20a9a63dd54fc777dcc0acc26a7540a1bb46 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139975 Reviewed-by: Michał Barnaś <mb@semihalf.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* rt1718s: don't update charge_manager on supplier = NONETing Shen2021-09-021-1/+3
| | | | | | | | | | | | | | | | | Same bug as CL:3113487. charge_manager accidentally overwrites other global variable when supplier = -1. BUG=b:198552518 TEST=Add debug log in charge_manager.c, make sure charge_manager does not receive invalid arguments. BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I12787ab66fba7d8328440835867262e3828ac723 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3140013 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* TCPM: Rename enum tcpm_sop_type and its constantsAbe Levkoy2021-08-318-48/+48
| | | | | | | | | | | | | | | As a followup to CL:3104290, give the TCPCI TRANSMIT and RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used for receiving, not just transmitting. Fix lint errors thus revealed. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995 Reviewed-by: Keith Short <keithshort@chromium.org>
* USB MUX: Convert usb_mux HPD functions to use mux_state_tDiana Z2021-08-305-5/+11
| | | | | | | | | | | | | | Since we have definitions for HPD IRQ and level in the mux flags, extend this to the HPD update function in the usb_mux structure as well. BRANCH=None BUG=b:172222942 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I19c3a65fc821a341338d73fabd7876339b37fe7d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095437 Reviewed-by: Keith Short <keithshort@chromium.org>
* rt1718s: enable FRSTing Shen2021-08-252-10/+43
| | | | | | | | | | | | | BUG=b:190348051 TEST=Combined with other CLs in the chain, verify FRS workable on Tomato BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I52a020b1288928eb9a0f3ada1364776cd8e78337 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3109709 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* Homestar: Distinguish PS8755 with hidden registerxuxinxiong2021-08-252-0/+26
| | | | | | | | | | | | | | | | | | When TCPC PS8755 is upgraded to PS8805 firmware, the product id cannot distinguish whether the chip is PS8755 or PS8805. Only the hidden register value of PS8755 is 0x80, so use this hidden register to distinguish whether it is PS8755. BRANCH=trogdor BUG=b:196889096 TEST=emerge-strongbad chromeos-ec Change-Id: I99b50dfb2f5ae47c3d4dbb3334dcdae20c281478 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3113261 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* TCPM: Remove enum pd_msg_typeAbe Levkoy2021-08-183-6/+6
| | | | | | | | | | | | | Convert usages of this enum to tcpm_sop_type. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I5fed273d72e7ad0e191db0cb0d121b70bdd9ecdb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104291 Reviewed-by: Keith Short <keithshort@chromium.org>
* TCPM: Rename enum tcpm_transmit_typeAbe Levkoy2021-08-188-11/+14
| | | | | | | | | | | | | | | Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be used for Rx as well. Describe it in comments. This prepares to consolidate enum pd_msg_type into this enum. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290 Reviewed-by: Keith Short <keithshort@chromium.org>
* ps8xxx: Wait for chip to wake up from LPMCaveh Jalali2021-08-171-1/+51
| | | | | | | | | | | | | | | | | | The ps8815 can take up to 50ms to fully wake up from sleep/low power mode. When the chip is asleep, the 1st I2C transaction will fail but the chip will begin to wake up within 10ms. After this delay, I2C transactions succeed, but the firmware is still not fully operational. The way to check if the firmware is ready, is to poll the firmware register for a non-zero value. BRANCH=none BUG=b:195087071,b:186189039 TEST=buildall passes Change-Id: If047fc122d7f61ed5fc361f97b47180e5cf08970 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084331 Reviewed-by: Keith Short <keithshort@chromium.org>
* ps8xxx: Check for register access errorsCaveh Jalali2021-08-161-7/+15
| | | | | | | | | | | | | | This adds error checking to ps8815_disable_rp_detect_workaround_check. BRANCH=none BUG=none TEST=buildall passes Change-Id: I6c901893e0f5f8ea02fbcb0e6dc082671f13a172 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3087984 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* ps8xxx: Refactor role control delay logicCaveh Jalali2021-08-141-8/+13
| | | | | | | | | | | | | | | | | | This refactors how we deal with ps8xxx_role_control_delay. An array of booelans is replaced with an array of delay values with default of 0ms. Instead of checking the array to determine whether a 1ms delay should be performed, the array unconditionally specifes the delay to be performed. The default 0ms delay is equivalent to the previous "false" entry. BRANCH=none BUG=b:186189039 TEST=buildall passes Change-Id: Ie351c58442eb206f38cea7a1f30dd1789a8c8025 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084330 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* USB MUX: Generalize mux ACKDiana Z2021-08-145-11/+35
| | | | | | | | | | | | | | | | | | | | Currently, only the virtual mux driver uses the mux ACK feature, but the actual wait for the host command ACK is a part of the usb_mux general code. Generalize this mux ACK wait so it's available if needed in the future for more muxes. Additionally, moving this wait out of the mux set will allow us to lock the muxes intelligently between tasks, without keeping the muxes locked during the inactive ACK wait. BRANCH=None BUG=b:172222942,b:186777984 TEST=tast typec.Mode*.manual on voxel Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I61a043425a482cc6f3170548c888d91ec20c2a82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078411 Reviewed-by: Keith Short <keithshort@chromium.org>
* ps8xxx: Simplify firmware version logicCaveh Jalali2021-08-141-21/+18
| | | | | | | | | | | | | | This removes a test that we know is always true before fetching the firmware version number from the chip. BRANCH=none BUG=none TEST=buildall passes Change-Id: Ie3096f80cb229291681ebe6c48f69a4b7a4d7be3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093036 Reviewed-by: Keith Short <keithshort@chromium.org>
* ps8xxx: Remove redundant & operator on functionsCaveh Jalali2021-08-131-27/+27
| | | | | | | | | | | | | This removes redundant usage of the address operator on function names. BRANCH=none BUG=none TEST=buildall passes Change-Id: Idd9fbe03af90e3ee75f6b420041a0c9bf67be884 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3093034 Reviewed-by: Keith Short <keithshort@chromium.org>
* IOEX: nct38xx: Map Type-C port to IOEX portVijay Hiremath2021-08-132-3/+28
| | | | | | | | | | | | | | | | Default function assumes Type-C port number to be same as the I/O expander number. This logic can differ based on the board design hence added overridable function to map Type-C port to I/O expander port. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Iec9deba7d2a6bf981664ec8d1665f54dfa2905b6 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3076471 Reviewed-by: caveh jalali <caveh@chromium.org>
* rt1718s: implement adc readTing Shen2021-08-132-6/+119
| | | | | | | | | | | | | | | | | | | | Cherry uses the VBUS1 adc channel in RT1718S to check the VBUS voltage on port 1. Thus add this function for Cherry. BUG=b:196001868 TEST=1) manually check the readings of ADC_VBUS1 2) Combined with board/ side changes, `ectool usbpdpower` shows correct value BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I243f28b2bd4e8541257afcacb50a024a72e301fd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3040801 Reviewed-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com> Tested-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* nct38xx: Split after-reset timestabilize-14151.B-mainDevin Lu2021-08-131-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Split after-reset time for NCT3807 and NCT3808, since the after-reset time is not the same. From the datasheet (section 4.4.2 Reset Timing) as following: * | Min | Max | * ----------------------+-------+-------+ * NCT3807 (single port) | x | 1.5ms | * ----------------------+-------+-------+ * NCT3808 (dual port) | x | 3ms | * ----------------------+-------+-------+ Currently the after-reset time for NCT3807 is zero. Change to 2ms to fit specification as well. BUG=none BRANCH=none TEST=On Redrix. Initial success with NCT3807. TEST=On Dirinboz. Initial success with NCT3807. TEST=make buildall. Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I1f47f57c0d8955946b1c2522e1a1736739217f41 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3068492 Reviewed-by: caveh jalali <caveh@chromium.org>
* rt1718s: add proper define guardTing Shen2021-08-061-0/+2
| | | | | | | | | | | | | | | | | The original code can't compile if CONFIG_USB_PD_TCPC_LOW_POWER not defined. Compiler complains that tcpci_enter_low_power_mode not found. BUG=none TEST=make BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: If59bf9e82bf5db879d83eb02b64a36c32c9613b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3076474 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* tcpm/rt1718s: implement software workaroundTing Shen2021-08-032-0/+65
| | | | | | | | | | | | | | | | Implement the software workarounds suggested by Richtek. See issue link for details. BUG=b:194982205 TEST=On Cherry & Tomato, manually verify PD works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I7d9c6c5fd3c9266f27e52c1756a7ecedc75f1846 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848280 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ps8xxx: patch ps8805 A3 chip Device IDSue Chen2021-08-032-0/+43
| | | | | | | | | | | | | | | | | Add config option for the ps8805 to override the TCPCI Device ID field based on the page 0 register 0x62 bit 7-4. A2 chip: reg 0x62 bit7-4 = 0x0 A3 chip: reg 0x62 bit7-4 = 0xA BUG=b:193099851 BRANCH=trogdor TEST=ectool pdchipinfo can show overridden DID for both A2 and A3 chip on Lazor DUTs Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I99767c92a97c2fcefd3bbe03e3cd2b90de192ff3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3056225 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cherry: enable usb pdTing Shen2021-07-291-0/+4
| | | | | | | | | | | | | BUG=b:177391887 TEST=verify pd works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ied4516abef3d544b8b4bdf8355f0f9fc305629a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2793783 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* rt1718s: fix incorrect alert methodTing Shen2021-07-291-1/+1
| | | | | | | | | | | | | | | | | | | | rt1718s driver incorrectly used the common alert function instead of its own implementation. This bug was not detected by `make buildall` because no one actually enables rt1718s until CL:2793783. BUG=b:177391887 TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I303cb0b6b7d0177648871ea36c1fc5c513fbb336 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058082 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* ppc/rt1718s: notify charger task about vbus changeTing Shen2021-07-291-8/+9
| | | | | | | | | | | | | | | | | | | PPC driver is responsible to notify charger task about vbus change. Original driver didn't implementation this. Also make BC1.2 driver correctly enables BC1.2 detection on vbus change. BUG=b:192422592 TEST=manually verify PD and BC1.2 works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I0bcbe0a1a43d9a9bcae61d69e247829648dd0d7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3045249 Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* raa489000: Wait 853us before checking VBUS at initwangganxiang2021-07-201-0/+2
| | | | | | | | | | | | | | | | | According to the RAA489000 manual, extend the time to read the vbus after the ADC initialization is completed. BUG=b:193402296 BRANCH=keeby TEST=make BOARD=cappy2 pass Signed-off-by: jesen <wangganxiang@huaqin.corp-partner.google.com> Change-Id: Ie326932a9a5d3849e31e15a090074ad1274a7266 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3023762 Reviewed-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* rt1718s: implement low power modeTing Shen2021-07-202-1/+18
| | | | | | | | | | | | | | | enable low power mode to further decrease power consumption. BUG=b:192815893 TEST=manually measure power BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ib5d22d1d3c9cc8ed644075b8ed239f96d0eea67e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004127 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* TCPC: add flag to disable debug accessory controlBoris Mittelberg2021-07-131-0/+2
| | | | | | | | | | | | | | | | | The NCT38xx TCPC takes over the GPIO we otherwise use to control the Burnside Bridge on Brya P1 devices. To get the BB out of reset we add the flag to tcpc_config structure to take the control back to TCPM. BRANCH=none BUG=b:191516281 TEST=running deployment in the lab; running FAFT PD test Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I73ddf26964cc6363640ddd80fbcbf353704d3198 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3016406 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* driver/tcpm/ite_pd_intc: separate pd interrupt to ite_pd_intcRuibin Chang2021-07-094-16/+134
| | | | | | | | | | | | | | | | | Separate pd interrupt functions to ite_pd_intc for easier maintenance on cros_ec and zephyr. And enable PD interrupt functions for zephyr. BRANCH=none BUG=none TEST=1.can zmake hayato and make asurada 2.PD port functions work on board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* NCT3807: Set up correct FRS enableDiana Z2021-07-071-1/+23
| | | | | | | | | | | | | | | | | | | | | The NCT3807 requires a few steps for FRS enablement. Specifically: - Zero out VBUS_SINK_DISCONNECT_THRESHOLD - Enable FRS interrupt (already done in TCPCI code) - Set FRS enable to 1 Note that it should not use the TCPCI specification method of clearing AutoDischargeDisconnect as soon as FRS is set. This results in the CC lines immediately reading as Open. BRANCH=None BUG=b:183586640,b:192012189 TEST=on guybrush C0, confirm FRS can execute successfully with WooHubs, HooToo, and Moshi Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ida0d33ae9ce4b8660615a0b9f3064cf90f5ae3bd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2987598 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* nct38xx: Avoid LPM exit when not alertingCaveh Jalali2021-06-251-10/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | This avoids taking an nct38xx port out of low power mode when it is not alerting. The nct38xx chips exit low power mode when they assert Alert. This means we don't have to explicitly take the port out of LPM to check its Alert status register. So, directly access the Alert register to check if the associated port was the source of the Alert. The nct3808 is a dual port chip with a single Alert pin. We need to be careful when servicing Alerts because the usual tcpc_read(), et. al. functions are wrappers that take the port out of LPM mode. When this happens, the nct3808 generates a CC status change alert on a disconnected port. Servicing this "phantom" Alert causes the other port to similarly generate a "phantom" alert. These CC status Alerts can effectively oscilalte between the two ports for a long time. BRANCH=none BUG=b:191531291 TEST=brya no longer gets into ALERT loops on C0/C2 Change-Id: Ib4be6b49a98f3053e5639477e8651b6ba487a0f9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977473 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* TCPM: Add new LPM bypass TCPC accessorsCaveh Jalali2021-06-251-2/+7
| | | | | | | | | | | | | | | | | | | | This adds a set of light-weight TCPC register access functions for special cases where the caller arranges for the TCPC to be accessible and the complexity of fully taking a TCPC out of LPM mode is not desirable. A typical use case is for alert service routines to be able to peek at a TCPCs alert register to determine if further processing is requested. BRANCH=none BUG=b:191531291 TEST=buildall passes Change-Id: Ib5c9add95f04be311315808168b070793b51cb24 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2986601 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* ps8xxx: Add board_ps8xxx_tcpc_init methodDevin Lu2021-06-252-0/+13
| | | | | | | | | | | | | | This patch adds method to allow boards to customize with ps8xxx tcpc initial. BUG=b:189587527 BRANCH=firmware-volteer-13672.B-main TEST=make buildall Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I0c160eb140500847505a367af08b3d2e82cbbec5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2972022 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* ps8815: Add displayport related settingsDevin Lu2021-06-251-0/+21
| | | | | | | | | | | | | | This patch adds one more register for displayport related settings with ps8815. BUG=b:189587527 BRANCH=firmware-volteer-13672.B-main TEST=make buildall Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: If79dce87a581923bb1f382786042018bc37c737a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2972021 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* RAA489000: Take sinking into account during debug detachDiana Z2021-06-241-3/+8
| | | | | | | | | | | | | | | | | When detaching from debug accessories, we need to set the CC lines to Open which may cause a loss of Vbus. However, if the port isn't sinking Vbus, then it should be okay to run this detach regardless of our current battery level. BRANCH=None BUG=b:191465743 TEST=on blipper, run the battery down with servo_v4 attached and observe the DUT can be woken normally by a charger on C0 after hibernate Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I5f946b23607c0bb3936132e93355875ff5688b30 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2983694 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rt1718s: set OVP to 23VSue Chen2021-06-232-0/+14
| | | | | | | | | | | | | | Set VBUS_VOL_SEL to 20V (4'b1111). BUG=b:191609106 BRANCH=none TEST=boot up system by plugging in adapter to typc port 1 with battery on Cherry dut. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: If3c3a82b2e0dbcecb1adaa62cb5d8ade4bae1942 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2977866 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* zephyr: tcpm: Update ITE driver to support zephyr namesSimon Glass2021-06-221-0/+16
| | | | | | | | | | | | | | | There is a name mismatch with some of the registers needed in this driver. Use #define for now until we can change these in ECOS, or remove the ECOS code. BUG=b:189855648, b:190860075 BRANCH=none TEST=with other CLs, build asurada for Zephyr Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I73da708c6e876db092b345ff7e0b28d99960b4d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2957548 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Fix compilation issues with nocturne SDKPatryk Duda2021-06-171-2/+6
| | | | | | | | | | | | | | | | | | | | | Compiler in nocturne cros SDK doesn't allow for variable declaration inside for loop. This patch removes variable declaration inside for loop in code which is used by nocturne board. This patch doesn't introduce any logical changes. BUG=b:160676144 BRANCH=none TEST=Make sure EC points to commit on cros/main. On nocturne SDK: cros_workon-nocturne start chromeos-ec emerge-nocturne chromeos-ec chromeos-bootimage Make sure that firmware compiles Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* NCT38xx: Add notification for chip resetDiana Z2021-06-162-0/+15
| | | | | | | | | | | | | | | | An external reset of the chip will reset some information we've gathered from that chip. Notify the driver so stored information may be reset as well. BRANCH=None BUG=b:183660105 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ib3335cf2984f2b13bbed7cacee603ba47edd2a51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953875 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* NCT38xx: Export boot type informationDiana Z2021-06-162-11/+31
| | | | | | | | | | | | | | | Outside code may need an understanding of our board's boot type, so allow it to be exported from the driver. BRANCH=None BUG=b:183660105 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Iec61872be283f9ef65ccf71e99d89cee7184f2f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953874 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com>
* gingerbread: Use CONFIG_USB_PD_VBUS_DETECT_TCPC for C1Scott Collyer2021-06-161-2/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL changes the stm32gx TCPM driver to allow CONFIG_USB_PD_VBUS_DETECT_TCPC to still be defined on boards that also use the stm32gx TCPM driver. This is required for gingerbread which has a PPC on C0 for VBUS detection, but relies on the TCPC to detect VBUS on port C1. BUG=b:159330563 BRANCH=quiche TEST=validated that can attach as SRC/DFP on C1 > pd 1 state Port C1 CC2, Enable - Role: SRC-DFP-VC TC State: Attached.SRC, [10.435540 C1: PE_SRC_Ready] [10.436511 pin_mode: 4, mf: 0, mux: 2] [10.442645 C1: PE_VDM_Request_DPM] [10.470346 C1: Entered DP mode] [10.470480 C1: PE_SRC_Ready] Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I986d504b1306c02132869abe7cbd630a966e0acd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949954 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ps8805: Add driver method to set/get GPIO signalsScott Collyer2021-06-162-0/+90
| | | | | | | | | | | | | | | | | The PS8805 has 3 GPIO signals which can be controlled by the EC with I2C register accesses. This CL adds functions to both set and get a one of the 3 PS8805 GPIO signals. BUG=b:159330563 BRANCH=quiche TEST=verified on gingerbread that VBUS control is functioning. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I1ef688e713ea84d2b0c6a6c23385fe6afb4f96b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2953868 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* raa489000: vbus_mv should greater than 3900mvMike Lee2021-06-091-1/+1
| | | | | | | | | | | | | | | | We need to add a condition for vbusmv to avoid that when the vbus_mv value is small but not zero vbus_mv, it is still considered as an adapter and open asgate. BUG=b:189090988 BRANCH=dedede TEST=make BOARD=storo Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: Ic046e65ed69f8616d6bc7d8ca28fc27cf894ed07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2949627 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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