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* raa489000: Choose charge port if VBUS present @ initAseda Aboagye2020-03-121-0/+16
| | | | | | | | | | | | | | | | | | Per the vendor, we need to starting sinking VBUS before writing to the Role control register, otherwise the ASGATE turns off. This commit checks to see if VBUS is present on a port at init time and no other charge port has been selected in order to keep the ASGATE turned on. BUG=b:150702984 BRANCH=None TEST=build and flash waddledoo, verify that VSYS remains up. Change-Id: I00957f7588f503551223d16969785198e1a9fd48 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2097136 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* variant trembyle: use fw_config for mux initializationDenis Brockus2020-03-124-0/+5
| | | | | | | | | | | | | | | | Setup the usb_muxes table to the correct values based on fw_config instead of using probing. BUG=none BRANCH=none TEST=verify USB is still working Signed-off-by: Denis Brockus <dbrockus@chromium.org> Change-Id: I7550d15d563f987def4fe70d52a55e31b655b753 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094743 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* driver: bma2x2: Fix frequency precision errorGwendal Grignou2020-03-101-8/+10
| | | | | | | | | | | | | | | | | | | | | On nautilus, the max frequency is set to 62.5Hz (the EC max frequency is set to 100Hz). However, when setting frequency to 62500 (mHz), the EC would bump up the frequency to 125Hz. The problem was in the calculation of the true frequency. By using 7.81Hz instead of 7.8125Hz as the multiplier, the driver would calculate the true frequency as 62480mHz, so it would set the accelerometer frequency to the next data rate. BUG=chromium:1059456 BRANCH=poppy TEST=On nocturne, check frequency is set right and tast run <IP> hardware.SensorRing passes. Change-Id: I743201bc8cccc7d38f39d1e370d660f4f37b4d95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092911 Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org>
* driver: l3gd20h: Fix maximal ODRGwendal Grignou2020-03-101-1/+2
| | | | | | | | | | | | | | Be sure EC max frequency is taken into account. [The component does not seem to be used.] BUG=chromium:615059,chromium:1059318 BRANCH=none TEST=Compile Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I00afa72d1642e2a3237e842a73ecc8ed50ec4a69 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092215 Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org>
* driver: lis2dw12: Fix maximal ODRGwendal Grignou2020-03-101-1/+3
| | | | | | | | | | | | | | Be sure EC max frequency is taken into account. BUG=chromium:615059,chromium:1059318 BRANCH=hatch, grunt TEST=Check tast run <IP> hardware.SensorRing works on Akemi(hatch) with new firwmare. Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: I8c4bf1213c876ceec4b20a4dd87094aab79d7b0b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092214 Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org>
* driver: bmi160: Fix ODR to REG when rate is less than 100Hz properlyGwendal Grignou2020-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the ODr was the exact frequency, the calculation was not correct. For instance, 50Hz would return register 6 when 7 was expected. Fixes: 0e99e9763 ("bmi160: Fix ODR to REG when rate is less than 100Hz") BUG=b:120942904 BRANCH=none TEST=use: for (int i = 1600000 ; i > 1000 ; i >>= 1) { printf("%d mHZ : reg %d\n", i + 1, BMI160_ODR_TO_REG(i + 1)); printf("%d mHZ : reg %d\n", i, BMI160_ODR_TO_REG(i)); printf("%d mHZ : reg %d\n", i -1 , BMI160_ODR_TO_REG(i -1)); } To verify the code is correct: 1600001 mHZ : reg 12 1600000 mHZ : reg 12 1599999 mHZ : reg 11 800001 mHZ : reg 11 800000 mHZ : reg 11 799999 mHZ : reg 10 400001 mHZ : reg 10 400000 mHZ : reg 10 399999 mHZ : reg 9 200001 mHZ : reg 9 200000 mHZ : reg 9 199999 mHZ : reg 8 100001 mHZ : reg 8 100000 mHZ : reg 8 99999 mHZ : reg 7 50001 mHZ : reg 7 50000 mHZ : reg 7 49999 mHZ : reg 6 25001 mHZ : reg 6 25000 mHZ : reg 6 24999 mHZ : reg 5 12501 mHZ : reg 5 12500 mHZ : reg 5 12499 mHZ : reg 4 6251 mHZ : reg 4 6250 mHZ : reg 4 6249 mHZ : reg 3 3126 mHZ : reg 3 3125 mHZ : reg 3 3124 mHZ : reg 2 1563 mHZ : reg 2 1562 mHZ : reg 2 1561 mHZ : reg 1 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Change-Id: Iefd0e0c732b52fef02f5b048c083ea67a2da247c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2093289 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* driver/fingerprint: Clarify FPC 1145 hardware IDTom Hughes2020-03-091-1/+7
| | | | | | | | | | | | | BRANCH=none BUG=b:150407388 TEST=make buildall -j Change-Id: Id0e7b42affcabf90c94334603a40b87cbc9543a8 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092913 Commit-Queue: Craig Hesling <hesling@chromium.org> Reviewed-by: Andrey Perminov <andrey.perminov@fingerprints.com> Reviewed-by: Craig Hesling <hesling@chromium.org>
* bq25710: Do not soft reset when running out of RW imageScott Collyer2020-03-091-14/+19
| | | | | | | | | | | | | | | | | | | | | | | | The bq25710 does not have a reset pin and therefore it's only following a power on reset that its registers are reset. The driver's init function executes a soft reset of the bq25710 to ensure that register settings following either an EC reboot or power on reset are the same. However, this is happening when the EC is in RO or RW, and there is no need to do this in RW. This CL adds a check around the soft reset so that it's only done in R0. BUG=b:148189096 BRANCH=firmware-hatch-12672.B TEST=Verified that low power mode no longer gets reenabled following the jump to RW. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I78a7484d3e44147cf350b785889f0f913b03bd06 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092213 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
* Revert "Ampton: Set the PS8751 to source mode before enter low power mode"Matthew Blecker2020-03-074-34/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ca73139635261ee1273fbe1767dcf06886d2208. Reason for revert: Breaks CCD with AP off https://issuetracker.google.com/150822168 Will work on a solution to address the original CL need, i.e. applying Rp in LPM. Follow the above bug. Some merge conflict happens. Resolved. Also change the usb_mux driver of Trogdor, as ps8xxx_usb_mux_driver is removed. Original change's description: > Ampton: Set the PS8751 to source mode before enter low power mode > > BUG=b:113830171 > BRANCH=octopus > TEST=check the power consumption is lower > > Change-Id: I527cdc5d1e4dd5de137ab0927e66c171696758ce > Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> > Reviewed-on: https://chromium-review.googlesource.com/1426306 > Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> > Tested-by: James Chao <james_chao@asus.corp-partner.google.com> > Reviewed-by: Jett Rink <jettrink@chromium.org> BRANCH=None BUG=b:113830171,150822168 TEST=Build Trogdor, verified CCD with AP off working. Change-Id: I58c26e8466b70e035a1c396cfcba6a46da4bccc9 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2091519 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* driver/tcpm: fix incorrect pd message enum namesTing Shen2020-03-062-4/+4
| | | | | | | | | | | | | | | | CL:2001938 renamed SOPP/SOPPP to SOP_PRIME/SOP_PRIME_PRIME, but didn't change some affected code. This CL fixes the incorrect names. BUG=none TEST=`make BOARD=kappa` with TCPMV2 enabled BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I91526f5552a188e01338b72bc47125fb12ff53b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2088826 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* nb7v904m: Fix bug with CHIP_EN polarityAseda Aboagye2020-03-061-2/+2
| | | | | | | | | | | | | | | | | | | | The driver's set_low_power_mode() function had its logic inversed. If we want to enable low power mode, we need to clear the CHIP_EN bit. BUG=b:150822611,b:150875209 BRANCH=None TEST=Flash waddledoo with an AP FW that has the fixed VBT, flash the EC with an image that contains this patch, verify that external displays over USB-C are working and that hot plugging the displays are working as well. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: Idc3c4d663365d0898b3e7c869b9c6e2dd088fa78 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2090082 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* driver/tcpm/it8xxx2: fix incorrect function prototypeTing Shen2020-03-051-2/+6
| | | | | | | | | | | | | | | | Update prototype based on the tcpm_drv definition change in CL:1967932. BUG=none TEST=Verify this compiles with a WIP asurada board BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ib4640ad0d44261c431f6182352012465955e1b31 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2087099 Reviewed-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* pcal6408: add ioexpander driverPaul Ma2020-03-053-0/+397
| | | | | | | | | | | | | | | | Add NXP PCAL6408 io expander support. BUG=b:150385481 BRANCH=none TEST=Change dalboz board specific files and verify hdmi hpd status can be detected correctly. Other gpios can be initialized and can input or output correct value by console commands ioexget and ioexset. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: I94c63149bac4ecbac4078abfe375d3009c944079 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2082299 Reviewed-by: Edward Hill <ecgh@chromium.org>
* bb_retimer: Set Data_Connection_Present bit in Safe modeVijay Hiremath2020-03-051-0/+1
| | | | | | | | | | | BUG=b:150764332 BRANCH=none TEST=Data_Connection_Present is set in safe mode on Volteer Change-Id: Ib00ab10d2527636d9e6342de937477a72625f8bf Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2087902 Reviewed-by: Keith Short <keithshort@chromium.org>
* kodama: rewrite charger CHG_CTRL1 registerxiong.huang2020-03-021-0/+2
| | | | | | | | | | | | | | | | | | | USB2.0 device cannot be recognized probabilistically when the smart battery is activated with the adapter at the first time. It found charger register CHG_CTRL1(0x11) is changed to 0x02 when disconnecting the external device since the unstable Vbat. In fact, the normal value should be 0x10. Rewriting the charger CHG_CTRL1 register after jumping to RW. BUG=b:150515707 TEST=ensure USB2.0 device can be recognized after the smart battery is activated with the adapter at the first time. BRANCH=kukui Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Change-Id: Iccba1f81099575968faa26bd8686c5ede37a3f31 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2082291 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* PS8740: Allow 0xa or 0xb for REVISION_ID2Edward Hill2020-02-292-23/+30
| | | | | | | | | | | BUG=b:150384642 BRANCH=none TEST=ps874x_init succeeds on Dalboz Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I9213a1f12d2412db4d38eaf75daaa27507787e90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080644 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zork: Split mux/retimer for trembyle/dalbozEdward Hill2020-02-291-2/+2
| | | | | | | | | | | BUG=b:150099043 b:150384642 BRANCH=none TEST=none Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ica9eda3f9d6a1332319b5c7ba56c0881d05eeebd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2079353 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* usb_mux: retimer: mux as chained mux and retimerDenis Brockus2020-02-2827-455/+484
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes retimers appear as generic muxes. By allowing a chain of muxes they can be stacked up to the new configurations that zork requires and will continue to work as they did before on configurations that only have a single mux. The code used to have two different arrays, 1) muxes and 2) retimers. On one of the zork configurations the processor MUX stopped being the primary mux and the retimer took its place. In a different configuration of that same platform it left the primary and secondary alone but the mux_set FLIP operation had to be ignored. Since the same interfaces needed to be available for both it stopped making sense to have two different structures and two different methods of handling them. This consolodates the two into one. The platforms that do not have retimers, this change will not make any difference. For platforms like zork, it will remove the retimers and make them chained muxes. So testing on trembyle makes sense to verify, BUG=b:147593660 BRANCH=none TEST=verify USB still works on trembyle Change-Id: I286cf1e302f9bd3dd7e81098ec08514a2a009fe3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2066794 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* PS8xxx: Workaround of Connection Detection not restartedWai-Hong Tam2020-02-263-3/+44
| | | | | | | | | | | | | | | | | | When issuing the COMMAND.Look4Connection to enable PS8805/PS8815 to restart Connection Detection, PS8805/PS8815 doesn't do so if the partner already presents Rp. This is a workaround that changes the starting pull to the opposite when doing DRP auto-toggle. BRANCH=None BUG=b:149570002 TEST=Enabled TCPMv2 and verified a 20V charger detected properly. TEST=Enabled TCPMv2 and verified a Type-C dongle detected properly. Change-Id: Ic2f65bdd74d1825ae81fcd30fec5e72d29a51663 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067481 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* volteer: Update USB C1 reset for next buildstabilize-volteer-12931.B-masterKeith Short2020-02-261-4/+9
| | | | | | | | | | | | | | | | Update the GPIO assignment for the USB_C1_RT_RST_ODL signal for the next board build. BUG=b:144933528, b:148243971 BRANCH=none TEST=make buildall TEST=Check unassigned board ID or board ID=0 uses legacy GPIO setting. Otherwise new GPIO setting is used. Change-Id: I4621e039e4461a4e10ab87bc2d4e000b5dcaa885 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057496 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* TUSB544: Add driverDiana Z2020-02-253-0/+143
| | | | | | | | | | | | | Driver code for the TUSB544 redriver BRANCH=None BUG=b:149561847 TEST=builds Change-Id: I391d6d264ff9d326c2d45569124dd1366f892812 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062766 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* isl923x: Add isl923x_set_comparator_inversion()Aseda Aboagye2020-02-252-0/+34
| | | | | | | | | | | | | | | | | | This commit adds an API to set the general comparator output polarity inversion. BUG=b:149794574 BRANCH=None TEST=Add some code to waddledoo to exercise this API, build and flash, verify it behaves as expected. Change-Id: Ib412ce9ad0e44e974ee5fc59bc30a26de65c94c5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067169 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* ps8xxx: Only apply PS8751 DRP disabled CC status workaround to PS8751.Matthew Blecker2020-02-221-18/+24
| | | | | | | | | | | BRANCH=none BUG=b:147472779,b:147684491,b:148710467 TEST=make buildall Change-Id: I8eed7bf86fe7c3e135517aaa31c3315128ca74e1 Signed-off-by: Matthew Blecker <matthewb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2068803 Reviewed-by: caveh jalali <caveh@chromium.org>
* raa489000: Utilize VBUS auto dischargeAseda Aboagye2020-02-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Renesas RAA489000 has an issue where GoodCRC messages are not emitted unless the VBUS Auto Discharge Disconnect setting is enabled. This needs to occur after determining orientation. However, there appears to be another issue where the device will not DRP toggle while that VBUS Auto Discharge Disconnect setting is set. Luckily, our TCPMv2 state machine will enable/disable this setting at these times for us. Therefore, this commit leverages the TCPCI auto discharge disconnect function which allows DRP toggling to work. BUG=b:149337338 BRANCH=None TEST=Build and flash waddledoo, boot to S0, verify DUT DRP toggles. Plug in a PD port partner, verify that PD communication works. TEST=Repeat above test in both orientations. Change-Id: Ieb79392f3cd7c1939bb6fb3de0d6785cec0b24c4 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057847 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
* nct3807: potential connection cleanupDenis Brockus2020-02-203-93/+49
| | | | | | | | | | | | | | | | | | | | I changed TCPMv2 to call tcpm_set_new_connection instead of tcpm_set_cc when connecting at the parent state for a new connection type. This allows the NCT3807 to clear out DRP and set the correct connection instead of clobbering what the hardware determined to be correct and setting it to an open listen. BUG=b:149593609 BRANCH=none TEST=verify USB-C Change-Id: I7402d3417a14fdc4158636e4716ef7fbdf4fa4a3 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064184 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2Ruibin Chang2020-02-194-6/+945
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PD driver for chip it8xxx1/8xxx2 series. BRANCH=none BUG=none TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1 (set cc toggle by console cmd): 1.pin configuration console cmd "gpioget" check gpio settings. memory dump check cc pin alternate settings. 2.Tx data error handle Message discard, No GoodCRC, Tx not enable, Timeout errors happen, corresponding INT will be triggered then do properly handle. 3.basic pd connection SNK:connect with adaptor, request max power (15V,3A), state SNK_READY. SRC:enable DRP role, connect with dongle, provide power (5V,1.5A), source Vconn 5v, get ack of cable discover id, state SRC_READY. 4.pd module disable SNK:connect with adapter. console cmd "hibernate sec", driver disable pd module, check still connection with adapter via dead battery rd. And when resume from hibernate, pd init can re-enable pd module, re-connect with adapter. SRC:connect with dongle. console cmd "hibernate sec", driver disable pd module, check cc pin (not Vconn source pin) volt power down to ~0v. And when resume from hibernate, pd init can re-enable pd module, re-connect with dongle. 5.Tx hard reset console cmd "pd port hard", check hard reset message by lecroy analyzer. 6.Tx cable reset check cable reset message by lecroy analyzer. 7.SOP' enable SRC:connects to SNK via E-mark cable. Source Vconn successfully, and receives cable's ack of discover id request. Not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 8.power role swap console cmd "pd port swap power", check pd protocol by lecroy. Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538 Reviewed-by: Jett Rink <jettrink@chromium.org>
* raa489000: Allow TCPC to control VBUSAseda Aboagye2020-02-182-0/+4
| | | | | | | | | | | | | | | | | | | In order to use the TCPCI interface to source VBUS, we need to allow the TCPC to actually source VBUS. This commit simply sets that setting in the TCPC. BUG=b:149580374 BRANCH=None TEST=Boot to S0, plug in a sink, verify that VBUS is sourced. TEST=Repeat above test in other orientation. Change-Id: I086375293206fb4179be6160ee9fc566eb140583 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057843 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* driver/ioexpander_it8801: add I/O expander driver for GPIOtim2020-02-172-17/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IT8801 is an I/O expander with the gpio. Add api compatible with ioexpander_drv so the main io expander framework can make use of the pins on the it8801. BUG=b/138352732, b/146996723 BRANCH=none TEST=Use gpio.inc to declare the gpio state. The console command #ioexget can get as follows: 0 O L IT8801_G0_00 1 O H IT8801_G0_03 1 O H IT8801_G0_04 0 O L IT8801_G0_06 0 O L IT8801_G0_07 1 O H ODR IT8801_G1_10 1 O H ODR IT8801_G1_11 1 O H ODR IT8801_G1_12 1 I H IT8801_G1_13 1 I H IT8801_G1_14 1 I H IT8801_G1_15 1 O H ODR IT8801_G2_20 1 O H ODR IT8801_G2_21 0 O L ODR IT8801_G2_22 0 O L ODR IT8801_G2_23 TEST=jacuzzi, juniper and kappa still compile TEST=keyboard scanning still works TEST=keyboard scanning now uses fewer i2c packets due to caching of GPIO23 Change-Id: I7ad89058ccd43b073d648e93877b86d6f187b5df Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1712887 Reviewed-by: David Huang <David.Huang@quantatw.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: David Huang <David.Huang@quantatw.com>
* usbc: remove tri-state polarityDenis Brockus2020-02-155-54/+0
| | | | | | | | | | | | | | | | | | TCPCIr2 had an issue with setting CC coming out of DRP that if the polarity was not retained that the connection dropped back to OPEN. Unfortunately this change broke many of the other TCPCI implementations. I am working on a different method of dealing with coming out of DRP and this is no longer needed. BUG=none BRANCH=none TEST=verify USB-C is working Change-Id: Ifa8f26d417df2f5d5f41a23fbf7e6f9129031e94 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056968 Reviewed-by: Jett Rink <jettrink@chromium.org>
* nct38xx: auto-toggle exit cleanupDenis Brockus2020-02-152-23/+133
| | | | | | | | | | | | | | | | | | Don't set the polarity behind the back of the PD stack. Just clear the DRP and leave the CC lines so they look just as we found them. This will allow TRY to work and we will no go OPEN because we set the CC lines to something that was not expected. BUG=b:149415919 BRANCH=none TEST=verify USB-C connections are working Change-Id: I766514bd46922000ea8916d61d00265e7e5e4fd4 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2053461 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* tcpci: Rename TCPC_FLAGS_TCPCI_V2_0 to TCPC_FLAGS_TCPCI_REV2_0Edward Hill2020-02-142-11/+11
| | | | | | | | | | | | | | | | | | Align naming of TCPC_FLAGS_TCPCI_V2_0 to match spec: "USB Type-C Port Controller Interface Specification" "Revision 2.0, Version 1.0" BUG=none BRANCH=none TEST=none Change-Id: I27752847581e449c3a2f6be438704d3e514c937d Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2057375 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* tcpci: Don't set 1 CC to open based on polarityAseda Aboagye2020-02-141-11/+0
| | | | | | | | | | | | | | | | | | | | | This commit fixes an issue where the TCPCI driver was setting 1 CC line to open when the polarity was known. This was causing issues where a charger would only work in one orientation without a battery. Ideally, this behaviour should be done a bit higher up in the stack whenever we are sourcing VCONN. BUG=b:149496312,chromium:149496312 BRANCH=hatch TEST=Build and flash waddledoo, remove the battery, plug in a PD charger, verify that the EC does not brown out. Change-Id: Idbcb915c0bbd867cfafc1e32c0f6534b363a867b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055618 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* Kodama: delay to enable charger EOC and TE functionxiong.huang2020-02-141-0/+7
| | | | | | | | | | | | | | | | | | | | When the battery is activated in shutdown mode, the battery needs H/W Initialization and Cu Deposition Checking in 4.2 second. Meanwhile, if the charger EOC function is enabled, charger will close/open the charging path repeatedly and will pull PMIC's VSYSSNS power. It's a workaround to delay 4.5 second to enable charger EOC and TE function. BUG=b:148045048 TEST=The adapter can boot the DUT automatically when the battery enters shutdown mode or ship mode. BRANCH=kukui Change-Id: Ie00d0f7ad506a273dc1b51f03b5d28dfa582f14f Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2012102 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* syv682x: Don't turn off VBUS when disabling sink modeKeith Short2020-02-141-1/+8
| | | | | | | | | | | | | | | | | | When the last charger is removed from the system, boards call ppc_vbus_sink_enable() to disable sink mode on all PD ports. The SYV682 doesn't support turning of VBUS and VCHG independently, so do nothing if if the SYV682 is currently the VBUS source. BUG=b:149428774 BRANCH=none TEST=make buildall TEST=On volteer, connect a charger to C0, connect a SNK device to C1. Disconnect charger and C0 and verify VBUS stays up on C1. Change-Id: I1747b3b19f584b0069134c520bd0ef0453a0a06a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2053036 Reviewed-by: caveh jalali <caveh@chromium.org>
* syv682x: Enable smart discharge modeKeith Short2020-02-142-30/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | The SYV682A device provides a smart discharge mode that automatically discharges VBUS and VCHG when the channel is shutdown. This works better than the manual dicharge mode which must be explicitly cleared after the discharge completes. This change also adds BUSY detection to the driver and performs a register reset during initialization. BUG=b:148870148, b:148467221 BRANCH=none TEST=make buildall TEST=Verify connection of SRC devices start battery charging, including DRP devices. TEST=Verify SNK devices are detected and reported by the kernel TEST=Measture VBUS discharge times of 20 ms when disconnecting both SNK and SRC devices. TEST=Write non-default value in SYV682 register, reboot EC, verify register updates to default plus EC changes. Change-Id: I54a5367924f3ae5adc473cb4b0a11789476e7bc3 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051311 Reviewed-by: caveh jalali <caveh@chromium.org>
* tcpci: Handle alerts in tcpci_tcpm_init()Edward Hill2020-02-141-1/+5
| | | | | | | | | | | | | | | | | | | | tcpci_tcpm_init() was clearing all alerts without handling them. The nct38xx is combined TCPC and IO expander. IO expander interrupts (IOEX_INT) rely on TCPC_REG_ALERT_VENDOR_DEF. This alert was being lost because tcpci_tcpm_init() was clearing it when we came out of low power mode in response to the alert interrupt from the TCPC. BUG=b:146468190 BRANCH=none TEST=IOEX_INT works with TCPC exiting low power mode TEST=Init, source, sink, low power all still work with ANX3429, ANX7447, PS8751, NCT3807 TCPCs Change-Id: I8ea4907ff621c4f39284a400fc40f2a20bf3ce91 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031650 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* nct38xx: use tcpci rev 2 standard receive and transmitDenis Brockus2020-02-141-65/+2
| | | | | | | | | | | BUG=b:149418834 BRANCH=none TEST=verify charger is working Change-Id: I31f2fedd7afece8303113ca1e1e74bbaf91de666 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055763 Reviewed-by: Edward Hill <ecgh@chromium.org>
* tcpmv2: make connect after auto-toggle driver specificDenis Brockus2020-02-132-0/+40
| | | | | | | | | | | | | | | | | | | | | nct38xx needs to have the cached polarity set in order to leave DRP mode without going back to an OPEN line. Other TCPCI implementations break when this happens. So moved it to a driver specific function instead TODO(b/149415919): Consider trying to clear the DRP mode instead of changing the polarity BUG=b:149311437 BRANCH=none TEST=verify charger functions on Trogdor Change-Id: I5092a468d860b573a6e5acaf7c013b3425916efb Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2050336 Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* nx20p3483: vbus_source_enable failure correctionDenis Brockus2020-02-121-30/+32
| | | | | | | | | | | | | | The nx20p3483 can not use the switch status register because TCPCI was used to enable the switch control. BUG=none BRANCH=none TEST=verify on TCPMv2 that USB3.1 gen 2 functions Change-Id: I5681996640568d74b51fdfc2d5dac20a97e4908a Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051010 Reviewed-by: Edward Hill <ecgh@chromium.org>
* trembyle: adjust gain on USB-A ps8811 for gen2 speedsDenis Brockus2020-02-061-0/+50
| | | | | | | | | | | | | BUG=b:138600008 BRANCH=none TEST=verify gen2 speeds on ps8811 equipt USB-A connections Change-Id: I5226fccf2460009dd7f873ca6869b57048bd65fc Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2040096 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* ps8818: debug cleanupDenis Brockus2020-02-062-56/+49
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I54817e28b255fddece2f4911ebef1fdbb86af367 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039912 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8802: debug cleanup and make wake_up accessibleDenis Brockus2020-02-062-76/+104
| | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I4fe0ce5fa1996367dfeeb982077a498e164c9a59 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2039911 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* ps8xxx: Set I2CIDLE command to enter low power mode for ps8805/ps8815Wai-Hong Tam2020-02-061-1/+9
| | | | | | | | | | | | | | | | | PS8751 has the auto sleep function that enters low power mode on its own in ~2 seconds. But PS8805/PS8815 doesn't have this function. Need to explicitly set the I2CIDLE command, which is implemented in the tcpci driver. BRANCH=None BUG=b:147302697 TEST=Checked the TCPC enter low power mode, that uses less power. TEST=Checked PD negotiaion: sinking power, sourcing power, DP dongle. Change-Id: I9cc9d0a1b8081a8142728f74183bd910614e74b5 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037135 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv1: Don't turn off pd module clock if rx enabledRuibin Chang2020-02-051-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Plug in type-c adapter in G3 power state. Because the SLEEP_MASK_USB_PD won't be set before we receive the SRC_Cap from SRC in SNK_Discovery state, but at waiting SRC_Cap this period time we will enter deep sleep mode and turns pd module clock off. This will cause TCPC miss the SRC_Cap message from SRC, then our PD_T_SINK_WAIT_CAP timer timeout and tx hard reset. So I add a configuration: SLEEP_MASK_USB_PD is set only by it83xx driver, so that SLEEP_MASK_USB_PD value won't be overwritten by set_state() function in usb_pd_prtocol.c. If one of the port TCPC Rx is enabled, chip will not go to deep sleep, but chip can go to doze mode that pd module clock won't be turned off only mcu core clock off. if all ports are nothing plug-in, the chip can go to deep sleep. BUG=none BRANCH=none TEST=TCPC doesn't miss any message from partner: -in SNK_DISCOVERY and power G3 state on board ampton. -in SRC_DISCOVERY and power S0 state on board it8xxx2_evb. Change-Id: I9639523e2ca180809f0f74f24321d06e7b3a04c2 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1990935 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* TCPCIv2: Send i2c stop bit after control messagesDiana Z2020-02-051-2/+7
| | | | | | | | | | | | | | | | Control messages contain no data, so the i2cxfer call to transmit the message data and stop bit were being skipped. This change sends the stop bit when the message contains only the header. BRANCH=None BUG=None TEST=waddledoo sends control messages successfully to Apple 3-in-1 dongle Change-Id: Iaa6a55cf6279265ed26859925d16cb05baaa0a23 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036813 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* syv682x: disable VBUS discharge in sink modeCaveh Jalali2020-02-041-17/+26
| | | | | | | | | | | | | | | | | | | The syv682x needs to have FDSG (force discharge mode) disabled in order to allow charging. BRANCH=none BUG=b:148487130,b:148467221 TEST=verified PD charging works with USB3 daughterboard (crrev.com/c/2013656 needed to enable USB3 board). Change-Id: Ifff20576accf88822228b7bd7b9eeb6b6cff6a6b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037097 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org> Tested-by: Eric Herrmann <eherrmann@chromium.org>
* volteer: add USB3 daughterboard supportstabilize-12881.B-masterCaveh Jalali2020-02-041-0/+16
| | | | | | | | | | | | | | | | | The USB3 daughterboard uses a ps8815 TCPC. If the CBI FW_CONFIG tag indicates that such a daughterboard is present, set up the ps8815 as the 2nd TCPC in the system. BRANCH=none BUG=b:144397088 TEST=in combination with additional patches, was able to update TCPC firmware Change-Id: I50ee57f5aa2efa0b6dbc562f968587f4fe03236c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013656 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* driver: bmm150: Fix commentGwendal Grignou2020-02-041-1/+1
| | | | | | | | | | | | | | Fix cut and paste error. BRANCH=reef BUG=none TEST=compile (cherry picked from commit 7b2f6cffa2e9710fe8bf0e66e20fc70bf1fb2a7f) Change-Id: I60cc7bb7b08491927a7ac03c769dda03f8765b81 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2034676 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* PS8818: use read/modify/write for regs with reserved bitsDenis Brockus2020-02-012-15/+36
| | | | | | | | | | | | | | | | | | PS88xx has a tendency to document undocumented register bits as reserved. Some of these are reserved and others should not be reset to 0 and should remain the value they were previously. The gain control appears to be of the latter type on the PS8818 BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: Ia67824c9b2676ad9984e4a8535ddd37bb8f2190b Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2033304 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ps8802: fix redriver configurationDenis Brockus2020-01-312-23/+210
| | | | | | | | | | | | | | | | | | | | | | | | in driver Added software IN_HPD control Added compile time optional debug in board specific tune function in usb_retimer Added gain control Added display lane control NOTE: PS8802 has reserved register bits that are being used internally, so be cautious just hitting these with 0, i.e. use field update to set a value to retain the old reserved fields BUG=b:146394157 BRANCH=none TEST=verify USB-C1 DP and USB connections Change-Id: I0b539df15fade509058492d6ab73a7b3ca9181df Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2031646 Reviewed-by: Edward Hill <ecgh@chromium.org>
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