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* Update license boilerplate text in source code filesstabilize-quickfix-15278.72.B-ishstabilize-quickfix-15183.78.B-ishstabilize-15446.B-ishstabilize-15439.B-ishstabilize-15432.B-ishstabilize-15429.B-ishstabilize-15415.B-ishstabilize-15395.B-ishstabilize-15393.48.B-ishstabilize-15381.B-ishstabilize-15364.B-ishstabilize-15361.B-ishstabilize-15359.B-ishstabilize-15359.58.B-ishstabilize-15359.50.B-ishstabilize-15359.45.B-ishstabilize-15335.B-ishstabilize-15329.59.B-ishstabilize-15329.44.B-ishstabilize-15317.B-ishstabilize-15301.B-ishstabilize-15300.B-ishstabilize-15278.64.B-ishstabilize-15251.B-ishstabilize-15245.B-ishstabilize-15236.66.B-ishstabilize-15208.B-ishstabilize-15207.B-ishstabilize-15185.B-ishstabilize-15185.7.B-ishstabilize-15183.82.B-ishstabilize-15183.69.B-ishstabilize-15183.14.B-ishstabilize-15174.B-ishstabilize-15167.B-ishstabilize-15129.B-ishstabilize-15122.B-ishstabilize-15120.B-ishstabilize-15117.86.B-ishstabilize-15117.48.B-ishstabilize-15117.111.B-ishrelease-R114-15437.B-ishrelease-R113-15393.B-ishrelease-R112-15359.B-ishrelease-R111-15329.B-ishrelease-R110-15278.B-ishrelease-R109-15237.B-ishrelease-R109-15236.B-ishrelease-R108-15183.B-ishrelease-R107-15117.B-ishishfirmware-ti50-prepvt-15315.B-ishfirmware-skyrim-15390.B-ishfirmware-skyrim-15369.B-ishfirmware-nissa-15217.B-ishfirmware-nissa-15217.45.B-ishfirmware-nissa-15217.126.B-ishfirmware-duplo-15151.B-ishfirmware-corsola-15194.B-ishfactory-trogdor-15210.B-ishfactory-skyrim-15384.B-ishfactory-nissa-15199.B-ishfactory-corsola-15197.B-ishfactory-corsola-15196.B-ishfactory-brya-15231.B-ishMike Frysinger2022-09-141-1/+1
| | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/stm32: Factor family specific clock logic out of usb.cJes B. Klinke2021-09-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | | The register for enabling USB register clock appears to have been identical across F0, F3, and G4 families, but for L5 it is different. Rather than having #ifdef in usb.c (as I recently committed), this CL will move the clock logic into clock_enable_module() where it arguably belonged all the time. Additionally: Some of the chip families make use of a clock_mask in their implementation of clock_enable_module(), but since the module_id enum has more than 32 value, until now, some values (among those MODULE_USB) would result in overflow, causing new_mask to be identical to clock_mask, and the USB case could have never been reached. BUG=b:192262089 TEST=Compile servo_v4 without linker errors BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-1/+1
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-1/+16
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* lm4: Use low speed clock in deep sleep.Alec Berg2013-10-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Changed the low power idle task to use the low speed clock in deep sleep. The low power idle task is currently only enabled for Peppy, Slippy, and Falco. This change decreases power consumption when the AP is not running. Note that the low speed clock is slow enough that the JTAG cannot be used and the EC console UART cannot be used. To work around that, this commit detects when the JTAG is in use and when the EC console is in use, and will not use the low speed clock if either is in use. The JTAG in use never clears after being set and the console in use clears after a fixed timeout period. BUG=None BRANCH=None TEST=Passes all unit tests. Tested that the EC console works when in deep sleep. Tested that it is possible to run flash_ec when in deep sleep and using the low speed clock. Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-151-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* lm4: Modified clock gating to allow easy expansion to low power.Alec Berg2013-10-101-0/+26
| | | | | | | | | | | | | | | | | | | | | Created a new function to enable or disable clocks to various peripherals. This new function makes it easy to specify if you want the clock enabled in run mode, sleep mode, and/or deep sleep mode. Added infrastructure to specify which GPIOs should interrupt the EC from deep sleep. BUG=none BRANCH=none TEST=Passes all unit tests. Ran on a peppy and verified that the clock gate control registers in run mode (LM4_RCGC regs) were the same before and after this change. Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* STM32L ADC driverVic Yang2013-09-051-0/+16
| | | | | | | | | | | | | | | | | | | | ADC module on STM32L is clocked by HSI oscillator, and thus we need to switch to HSI if using MSI. After the conversion, if the system is not in S0, clock is switched back to MSI again. There are several register bits that can only be written when ADC is powered down. For now, let's just power down the ADC after each conversion. Currently ADC watchdog is not working and is disabled on STM32L. BUG=chrome-os-partner:22242 TEST=Try multiple all-channel and single-channel reads in S0 and S5. BRANCH=None Change-Id: I769dda8a9c69ac9de1eb22d6d259034eef8c1ac4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167454
* spring: Enable low power mode.Todd Broch2013-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | This mode was disabled initially to make sure it didn't side-effect things during early development. Now that branch is cut lets re-enable and backport when stability is proven. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=spring BUG=chrome-os-partner:17587 TEST=manual, install & run on Spring ... system functions. When device is plugged stays awake regardless of battery state. When device is unplugged sleeps and power is saved. When device is re-plugged awakes. Change-Id: I9a85fa7376d1a94c9864beed3d053e8b49480959 Reviewed-on: https://gerrit.chromium.org/gerrit/45594 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org>
* Clean up clock moduleRandall Spangler2012-10-301-2/+2
| | | | | | | | | | | | | | No functional changes; just code cleanup. On LM4 this also #ifdef's out the 'sleep' and 'pll' commands since they're big and we don't use them. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system Change-Id: I1b72d07d6cca2c783d7ac4c880119df3e88e356e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36799
* daisy: Modify charging flow to comply charging specificationRong Chang2012-08-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This change corrects charger interrupt event handling, charger enable gpio, battery full condition, EC deep sleep mode support when AC unplugged, and lid controlled power off. Signed-off-by: Rong Chang <rongchang@chromium.org> BRANCH=snow BUG=chrome-os-partner:12573,12574,12575 TEST=manual - ec console command 'gpioget': - SPI1_MISO should be 0 when AP off - CHARGER_EN should be 0 after AC unplugged - charging led should be off after AC unplugged - when battery remaining charge < 3%, system should be powered off without AC. - ec console command 'sleepmask 0', turn off AP: - deep sleep only when AC unplugged Change-Id: I0f63835dae67d90de7a8c8c6c3537ca9a16faed4 Reviewed-on: https://gerrit.chromium.org/gerrit/30316 Commit-Ready: Rong Chang <rongchang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Tested-by: Rong Chang <rongchang@chromium.org>
* Enable PLL only briefly during ADC initRandall Spangler2012-08-091-8/+24
| | | | | | | | | | | | | | | | | | It was previously only enabled for 1500us during boot, but in a way that triggered a needless round of notifications to other modules. This is cleaner. This also fixes adc_init() not initializing the task IDs to wake when interrupts come in, and removes some unneeded code from other init functions. BUG=chrome-os-partner:12472 TEST=boot system and run adc command. Should still provide reasonable data. Change-Id: I9ae5857d988c727caf5d53f551a2f12b30974c0f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29806 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32f100: implement low power modeVincent Palatin2012-08-091-0/+13
| | | | | | | | | | | | | | | | | | | | | When the AP is not running and we have enough time go to STOP mode instead of simple idle. The EC consumption should drop from 12mW to a few mW. This is currently not activated by default, you need to type "sleepmask 0" in the EC console to activate it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8866 TEST=on Snow, check the software is still working properly when STOP mode is activated and measure power consumption on 3v_alw rail. Change-Id: I231d76fe6494c07b198c41694755b82d87c00e75 Reviewed-on: https://gerrit.chromium.org/gerrit/29315 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Disable PLL at end of initRandall Spangler2012-04-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This saves power. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual Get a proto1 system modified with INA current sensor 1) From chroot: dut-control i2c_mux_en:on i2c_mux:rem dut-control pp3300_alw_mv pp3300_alw_ma 2) From EC console: pll (this should turn the PLL back on; it'll report clock frequency ~66MHz) 3) From chroot: dut-control i2c_mux_en:on i2c_mux:rem dut-control pp3300_alw_mv pp3300_alw_ma Current (ma) should be bigger than in step 1 Change-Id: I806953684c57fd60bf481acb01dddffe2f2ad0ed
* Support dynamically changing the system clockRandall Spangler2012-04-091-5/+14
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
* Initial sources import 3/3Vincent Palatin2011-12-071-0/+14
source files mainly done by Vincent. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Change-Id: Ic2d1becd400c9b4b4a14d4a243af1bdf77d9c1e2
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