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* common: Add hardware error codeGwendal Grignou2018-03-191-0/+2
| | | | | | | | | | | | Add error code to indicate a piece of hardware is not working properly. BUG=none TEST=compile BRANCH=none Change-Id: I34eca8073a359aec1c559241654a1d0a7075cd44 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753968
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* EFS: Add error codesDaisuke Nojiri2017-08-291-0/+20
| | | | | | | | | | | | | | | This patch defines more error codes to make the consle more descriptive. BUG=none BRANCH=none TEST=Boot Fizz. Change-Id: I84cc6cd7f309bb2f2e1f36dea6cf5a7f0f862f50 Reviewed-on: https://chromium-review.googlesource.com/639160 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix compilation with coreboot-sdkStefan Reinauer2017-08-041-0/+7
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=none TEST=The following sequence passes sudo emerge coreboot-sdk export CROSS_COMPILE_arm=/opt/coreboot-sdk/bin/arm-eabi- export CROSS_COMPILE_i386=/opt/coreboot-sdk/bin/i386-elf- export CROSS_COMPILE_nds=/opt/coreboot-sdk/bin/nds32le-elf- make buildall -j Change-Id: I4cafbcd70efd6bdf102f848f1cca4772b4ccd10e Reviewed-on: https://chromium-review.googlesource.com/595207 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* common: sensors: add extra sensor attributesNick Vaccaro2017-05-181-0/+3
| | | | | | | | | | | | | | | | | | | | | | Adds min_frequency and max_frequency to struct motion_sensor_t. New attributes min_frequency and max_frequency are now returned in ectool's MOTIONSENSE_CMD_INFO response. Incremented ectool's MOTIONSENSE_CMD_INFO version to version 3. Add constants for MIN_FREQUENCY and MAX_FREQUENCY to each sensor's header file. BRANCH=none BUG=chromium:615059 TEST=build/boot and verify MOTIONSENSE_CMD_INFO response on kevin, make buildall -j passes. Change-Id: I66db9715c122ef6bb4665ad5d086a9ecc9c7c93a Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/482703 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Reef: Reduce max battery charge voltage for 0.5% marginDaisuke Nojiri2017-01-251-0/+6
| | | | | | | | | | | | | | | | | | (From CL 431233) Limit battery charge voltage to prevent battery over-charge, due to regulation inaccuracy. Since RO FW may charge > 8656 mV, ensure the battery is not full before charging. BUG=chrome-os-partner:61906 BRANCH=none TEST=Manual on Electro, sysjump with battery @ 99%, verify battery discharges, then re-charges to 100%, before discharging once again. Change-Id: I28212c83057a442fd75e39f8ad51927a7a1f2817 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/432857 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* driver: als: Add error code UNCHANGEDGwendal Grignou2017-01-051-3/+6
| | | | | | | | | | | | | | This error code is used to indicates the data has not changed. Motion sense task will therefore not add any entry in the sensor FIFO. BUG=chrome-os-partner:59423 TEST=make -j buildall BRANCH=reef Change-Id: I58b9be5675d8949bd682d8c89dadea1dfff9bf2e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424856 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common.h: Create __bss_slow tag.Aseda Aboagye2015-11-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some ECs such as the MEC1322 have a data RAM optimized region as well as a code RAM optimized region. We discovered that we could save quite a bit more space by reusing the a portion of the code RAM region as an additional .bss section. However, this region resides in the code RAM region. If on the same cycle the processor fetches an instruction and does a load or store to this code RAM region, the data access will be delayed by one cycle. Hence, the naming of ``.bss.slow" section. For boards which do not define CONFIG_REUSE_LOADER_WITH_BSS_SLOW, all objects bearing this tag will be simply appended to the existing .bss section. BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=make -j buildall tests CQ-DEPEND=CL:306173 Change-Id: I126fbeee5255732a6dd6fea1d4557fc2b2c62c96 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311209 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: accel: Add error code for irq handlerGwendal Grignou2015-09-191-0/+2
| | | | | | | | | | | | | | | | | | When IRQ handler is not processing any event raised, return NOT_HANDLED. Without this change, any event would set the light sensor process timestamp and, if the light sensor frequency was lower than BM160 fifo interrupt frequency, we would never read from the light sensor. BRANCH=smaug BUG=chrome-os-partner:43800 TEST=Compile. Check that light sensor data get updated. Change-Id: I302f80c5cd9b4f3c926362fdafdc8b5074cabb60 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/298686
* nds32: remove macro "RO"Dino Li2015-07-011-8/+0
| | | | | | | | | | | | | | | | | | | "RO" is a workaround for GP base instructions. And now we have added "-mno-gp-direct" option in the NDS32 toolchain. So the compiler would not generate GP base instructions directly, and we can remove this "RO". Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:24378 TEST=console "version" and "gpioget" Change-Id: I23cb6374fb8eb57081d713bf5c70b80a87dd2fb5 Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/281862 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-191-0/+10
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cr50: Added macros for register read/writeSheng-Liang Song2015-03-201-3/+7
| | | | | | | | | | | | | | | | Added macros for register read/write. BRANCH=none BUG=chrome-os-partner:33815 TEST="make buildall -j; Verified on RevA1 chip" Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: I25c6f6b5865c7fdde002b2191b1f2eaaba15f589 Reviewed-on: https://chromium-review.googlesource.com/236402 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org> Tested-by: Sheng-liang Song <ssl@chromium.org>
* EC: Add smbus interface read & write APIsSheng-Liang Song2014-08-291-0/+2
| | | | | | | | | | | | | | | | | | Ref: http://smbus.org/specs/smbus20.pdf - Support software CRC8 generation and checking. - Support read/write word (2-bytes) - Support read/write blocks (up to 32 bytes) BUG=chrome-os-partner:24741 BRANCH=ToT,glimmer TEST=Verified with smart battery firmware update application on glimmer. Passed LGC & Simplo Battery. Change-Id: Ic2e7f759af80c06741ed49fee1826213429fbf8a Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209747 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* move stringify macro to common includestabilize-5899.BVincent Palatin2014-05-271-0/+9
| | | | | | | | | | | | | | | | | | We need to stringify macros arguments in various places in the code, avoid duplicating this definition. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: I03530c06139fad4c60711d041239b396d9ed321e Reviewed-on: https://chromium-review.googlesource.com/201576 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* nds32: WORKAROUND for toolchain bug on rodataVincent Palatin2013-12-101-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes the toolchain tries to put a relocation which is not suitable to access variables in a read-only section. The nds32 gcc uses GP-relative signed 17-bit relocation to access variables stored in .rodata (eg lwi.gp $r0, [ +gp ]) That's wrong since $gp is pointing in the middle of .data and .bss in the SRAM, while .rodata is sitting in flash. Since on IT8380, the flash is at 0x00000 and the SRAM is at 0x80000 (512kB further), the linker will fail trying to create the signed 17-bit relocation (it detect that it needs to truncate it) Force the compiler to put another relocation as a workaround for now. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24378 TEST=./util/make_all.sh ; make BOARD=it8380dev check "version" and "gpioget" on spring, link and it8380dev. Change-Id: Ife50adf3a26be28f113292f73a1a70e8d74b5d8c Reviewed-on: https://chromium-review.googlesource.com/176913 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+1
| | | | | | | | | | | | | | | | | | | | This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Consolidate module IDs into a single shared enumRandall Spangler2013-10-251-0/+3
| | | | | | | | | | | | | | | | | | This is tidier than every board defining its own module_id enum, and encourages standard naming of modules. A subsequent CL will do more cleanup (standardizing on MODULE_LED instead of MODULE_POWER_LED and MODULE_LED_KIRBY), but it's easier to do that as a separate CL than part of this one. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: If0fcef284fb3aa2fa145bc9ff3d1f3f2d25a2e47 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174382 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Use macros for C <-> K conversionsBill Richardson2013-08-071-0/+6
| | | | | | | | | | | | | | | This just replaces all the "X - 273", "Y + 273" stuff with a macro. BUG=none BRANCH=falco,peppy TEST=manual Run the EC console command "temps". It should print human-readable things. Change-Id: Icc4284c89fdbc0cd3b206a0faacf121973652a63 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65005 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Word-align the host memory mapRandall Spangler2013-08-011-2/+7
| | | | | | | | | | | | | | This fixes unaligned access exceptions when totally-unrelated code changes happen to move around host_command.c's global variables. BUG=chrome-os-partner:21578 BRANCH=none TEST=add a ccprintf() call to host_command.c; no longer causes an exception Change-Id: I5407e5631a08ea647dc40e5bd9c7bd101868ced0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64233 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Standardize concatenation macrosRandall Spangler2013-07-241-0/+17
| | | | | | | | | | | | | | | | | | To create a token by concatenating already-defined macros and new text, it's necessary to use multiple levels of macro. We'd already done that in several places in the code such as STM32_CAT; this now standardizes it into a single place. BUG=chrome-os-partner:18343 BRANCH=none TEST=Build all platforms; examine ec.RO.map to see that irq_*_handler and prio_* symbols evaluated the same as before. (Other macro evaluations would simply fail to compile if they were incorrect, since the concatenated tokens wouldn't fully expand.) Change-Id: Ic9bf11d27881a84507fe7b6096dab6217c6c6dc7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63231 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Make a top-level config.h file to include sub-configsRandall Spangler2013-07-161-7/+1
| | | | | | | | | | | | | | | | | This file will soon contain the exhaustive list of all CONFIG defines and their descriptions. Chip-level configs are renamed to config_chip.h to avoid naming conflicts. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I9e94146f5b4c016894bd3ae3d371c4b9f3f69afe Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62122 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Revert "Revert "Add thermal engine test""Vic Yang2013-05-171-0/+2
| | | | | | | | | | | | | | | This reverts commit 89e688a3325e91d3c59ac639f04f2c91019c9b10. Time-scaling is added back. We can run this test now. BUG=chrome-os-partner:19236 TEST=Pass the test. BRANCH=None Change-Id: Id3dcec6fc12489f5f0602de91c6560a8dfbef9af Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51551 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Revert "Add thermal engine test"Vic Yang2013-05-161-2/+0
| | | | | | | | | | | | | | | | Time-scale functionality is temporarily reverted and this test is now taking too long. Revert this test now. Will add it back when we solve the time-scale issue. This reverts commit d9cf88b35ad211d873f48b41fd985e22ff049b83 Change-Id: Id9ce1071eb2114dd6968d3df9f0bce395edaeef6 Reviewed-on: https://gerrit.chromium.org/gerrit/51482 Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Stéphane Marchesin <marcheu@chromium.org> Tested-by: Stéphane Marchesin <marcheu@chromium.org>
* Add thermal engine testVic Yang2013-05-151-0/+2
| | | | | | | | | | | BUG=chrome-os-partner:19236 TEST=Pass the test. BRANCH=None Change-Id: I1c96437e1fb3492faa5352383f852dc1d2718ace Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51248 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Move REG16 and REG32 macros to common.hRandall Spangler2013-04-101-1/+5
| | | | | | | | | | | | | | | And use them for LM4 as well as STM32. Consistency is good. No functional changes, just moving/renaming code. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I029a21fadb50726500255219dc38615874a369e7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47700 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add macros for mocking functionsVic Yang2013-04-081-0/+12
| | | | | | | | | | | | | | | This introduces two symbols for mocking functions in existing code: - test_mockable - test_mockable_static BUG=chrome-os-partner:18598 TEST=none BRANCH=none Change-Id: Ia7251a9b609136c8f3b155c221634bac7dcb1d68 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47540 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* link: Temp sensors can return not-powered error codeRandall Spangler2012-10-111-1/+5
| | | | | | | | | | | | | | | | | | | | | | | This removes the need for a separate method to check sensor power, and gets rid of temp_sensor.c knowledge of what powers each sensor. BUG=chrome-os-partner:15174 BRANCH=link TEST=manual - reboot - within a second, type 'temps'; I2C sensors should return error 1 - type 'temps' again; all sensors should return data - power off system - type 'temps' again; I2C sensors and PECI should return error 8 - 'gpioset enable_vs 1' - type 'temps' again; I2C sensors should return valid data; PECI should still return error 8. Change-Id: I17c353b3c483bc320769307c7715008ec729089b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/35287 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Include board and config headers in common.hRandall Spangler2012-06-291-0/+9
| | | | | | | | | | | | This ensures they get included everywhere, and fixes a common bug where we forget one of them and then code which is supposed to be BUG=none TEST=build the code Change-Id: Ic9208f946a3aea4b0b08f546f1919602befa76d4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26365
* Use __packed instead of __attribute__((packed))Randall Spangler2012-06-281-1/+9
| | | | | | | | | | | The presubmit script for linux kernel style prefers the former. BUG=none TEST=none Change-Id: I0a0a1eb039f45975ada075c1302d868071a7cfb1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26361
* Add system_is_locked() to prevent sysjump on consumer systemsRandall Spangler2012-05-251-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This returns true when both HW and SW write protect are enabled. Once WP is enabled, sysjump will be locked out. system_is_locked() can be used to gate other dangerous-ish commands too. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7468 TEST=manual sysinfo -> unlocked, copy A sysjump B -> works flashwp lock reboot (make sure flashinfo shows WP asserted and flash locked; note there is a HW bug on proto1 which makes this flaky) sysinfo -> locked, copy A sysjump B -> fails (remove WP screw) reboot hard flashwp unlock Change-Id: I849b573675c2c1cb4c44b9a05d6973e38247ca23
* Better help for console commandsRandall Spangler2012-05-251-0/+11
| | | | | | | | | | | | | | | | | | | | Additional help messages and usage are gated by CONFIG_CONSOLE_CMDHELP, so we can turn it on if there's space (adds about 3KB to image size) and turn it off when there isn't. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual 1) help 2) help list 3) help gpioset 4) gpioset -> wrong number of params 5) gpioset fred 0 -> param1 bad 6) gpioset cpu_prochot fred -> param2 bad Change-Id: Ibe99f37212020f763ebe65a068e6aa83a809a370
* Support reboot_ec command in ectool (temporarily).Louis Yung-Chieh Lo2012-03-091-0/+9
| | | | | | | | | | | | | | | Note that this is a big security hole and should be removed after we complete the EC autoupdate mechanism and vboot code. To full update EC firmware on proto 1.0, we need a manual way to switch EC running on RO/RW. This CL implements the LPC command. BUG=chrome-os-partner:8415 TEST=on proto 0.5. ectool reboot_ec RW_A # EC boots to RW A ectool reboot_ec RO # EC boots to RO Change-Id: Ibf050328bc4e3d2c6d72bfc478d6334f11f0eb46
* Initial sources import 1/3Randall Spangler2011-12-071-0/+35
source files mainly done by Randall. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
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