summaryrefslogtreecommitdiff
path: root/include/config.h
Commit message (Collapse)AuthorAgeFilesLines
* lucid: add support to detect BC1.2 suppliersMary Ruthven2016-02-261-0/+3
| | | | | | | | | | | | | | | | Use built-in USB periperal to detect BC1.2 suppliers and update the charge manager. BUG=chrome-os-partner:48658 BRANCH=None TEST=manual for lucid. Use a samus as the supplier, and insert the charger into Lucid. Verify that it identifies it as SDP. Use a wall charger and verify that Lucid identifies it as DCP. Change-Id: I7842e9f75874f727837df5bfc28690662caf821c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329236 Reviewed-by: Shawn N <shawnn@chromium.org>
* kunimitsu: hibernate: enable PseudoG3 support at board levelKevin K Wong2016-02-181-6/+0
| | | | | | | | | | | | | | this is to move the existing code from chipset level to board level since PseudoG3 is a board feature that required specific hardware. BUG=none BRANCH=glados TEST=use hibernate command to enter PseudoG3 Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327677 Reviewed-by: Shawn N <shawnn@chromium.org>
* config: it83xx: remove "CONFIG_IT83XX_PECI_WITH_INTERRUPT"Dino Li2016-02-171-3/+0
| | | | | | | | | | | | | | | | IT839x and the new series all support interrupt of PECI, so we remove it. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make -j buildall Change-Id: Ib126cb418a4ba5ef313ee93948bc2fbb96bc936d Reviewed-on: https://chromium-review.googlesource.com/327643 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driverEwout van Bekkum2016-01-281-0/+18
| | | | | | | | | | | | | | | | | | | | | Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tcpc: add support for TCPC with integrated high-speed muxesVincent Palatin2016-01-271-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The TCPCI specification defines ane optional register 18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way of steering the high-speed muxes. Implement the feature as a usb_mux_driver, under the conditional flag CONFIG_USB_PD_TCPM_MUX. The USB PD port index should be set in the port_addr field of the 'usb_mux' structure. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:49605 TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP muxing. Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5 Reviewed-on: https://chromium-review.googlesource.com/322956 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: update ec2i moduleDino Li2016-01-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The previous EC2I module does not meet section '7.17.5 EC2I Programming Guide'. We need to correct it to prevent conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps long wait states. NOTE: If EC is using EC2I internal bus to access PNPCFG registers while host accessing EC ram through H2RAM interface at the same time, the symptom will appear. 2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'. We don't allow the host access PNPCFG registers. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and there is no error code return. 2. To create a stress test for this change. - EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG registers per-10ms. - run ectool 'version' command per-100ms. Before the change was made, LPC will keep in long wait states immediately. After the change, we run the test of ectool 'version' command over 20000 times. Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da Reviewed-on: https://chromium-review.googlesource.com/323563 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: Add temporary secure storage for the host during bootDuncan Laurie2016-01-251-0/+6
| | | | | | | | | | | | | | | | | | | This adds a temporary secure storage interface for the EC to be able to store small amounts of data from the host that is locked until the chipset resets. This is used by pre-memory verified boot on x86 systems where we need to know which RW slot to boot and what the hash is to ensure that we can resume from S3 safely. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315222 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: hibernate: Don't reconfigure all GPIOsShawn Nematbakhsh2016-01-251-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good idea: - INPUT / PULL_UP is not necessarially the lowest-power state (for example, if there is an onboard pull-down). - Most GPIOs should already be in lowest-power state when we're in S5. - For the few GPIOs that need to be in a different state for hibernate, we can use a board-level callback. In addition, remove mec1322 code related to restoring from hibernate state, since we always reset coming out of hibernate. BUG=chrome-os-partner:49608 BRANCH=glados, strago TEST=`hibernate` on chell console when in S5 and AC removed. Verify that EC power is roughly equivalent to low-power idle power. Attach Zinger, verify that device wakes and boots, and charges from charger. Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322937 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* skylake: Add support for asserting RTCRST if power sequencing failsDuncan Laurie2016-01-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pulse RTC reset to the PCH when power sequencing exit fails we need to watch for SLP_S4 to deassert and if it does not then assert RTCRST using a board specific method. This is attempted up to 5 times before giving up and staying in G3. On skylake the RSMRST passthru needs to be honored when the task is woken up, so while waiting call handle_rsmrst() if woken up early. This is needed because it is RSMRST that actually tells the PCH to try and wake. This is all wrapped in a config option and board specific method because not all boards have a GPIO to control RTCRST and if they do they may not all use the same method to assert it. BUG=chrome-os-partner:49564 BRANCH=glados TEST=manually tested on chell EVT: First, ensure board sequences properly if everything is OK for a normal boot. Next, modify handle_rsmrst() to not pass through the signal in order to simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST and power up again 5 times before giving up and staying in G3. Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322724 Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: adc: Add support for DMA continuous modeShawn Nematbakhsh2015-12-211-1/+13
| | | | | | | | | | | | | | | | | | | Add support for continuously writing ADC samples to a circular buffer. CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an appropriate sized buffer must be passed to adc_read_all_channels(). BUG=chromium:569994 TEST=Manual on snoball. Verify 'adc' continues to function (single mode). With pending commit, verify that continuous conversion interrupt is called at appropriate frequency and values look consistent. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e Reviewed-on: https://chromium-review.googlesource.com/318505 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: adds the SPI master driverEwout van Bekkum2015-12-211-0/+4
| | | | | | | | | | | | | | | | | Adds the SPI master driver with support for both SPI masters with support for using GPIOs as chip selects or using the hardware's dedicated chip selects. Note this has not been enabled in the cr50 board. BRANCH=none BUG=none TEST=verified through use of the SPI_FLASH module on cr51 Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317329 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: add ability to include two identical RW sections in the EC imageVadim Bendebury2015-12-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical EC image includes two similar in their functionality subsections, RO and RW. CR50 has a small RO subsection, all it does - detects a proper RW image to run and starts it up. To provide for reliable firmware updates, the CR50 image needs to include two RW sections, while the code is running from one RW subsection, the other one can be upgraded. This patch adds the ability to generate two identical RW sections, mapped half flash size apart, and include them into the resulting EC image. To keep things simple the previously existing RW section's name is not being changed, while the new (identical) RW section is named RW_B. Two configuration options need to be defined to enable building of the new image type: CONFIG_RW_B to enable the feature and CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the flash. A new rule added to Makefile.rules allows to generate a different lds file from the same source (core/cortex-m/ec.lds.S) by defining a compile time variable to pick a different base address for the rewritable section, when RW_B is built. BRANCH=none BUG=chromium:43025 TEST=as follows: - make buildall -j still succeeds - verified that regular CR50 image starts successfully - modified chip/g/loader/main.c to launch RW_B first, re-built and re-run the image, observed on the console: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv cr50 bootloader, 20151118_11218@80881, no USB, full crypto Valid image found at 0x00084000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com] [0.001148 Inits done] This FPGA image has no USB support Console is enabled; type HELP for help. > [0.002212 task 2 waiting for events...] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (note that the image base address is 0x840000, which is RW_B). Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316703 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: reduce hash implementation stack requirementsVadim Bendebury2015-12-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack space is pretty tight on cr50, and since there is no need to support SHA digest sizes in excess of 256 bits, the digest buffer size should be reduced. This patch makes the maximum expected digest size dependent on the set of configured hash algorithms, moves hash size related asserts from run time to compile time, and passes compile time definition to the TPM2 library to increase its hash state container (it became too small when SHA384 was disabled). The sw context requirements should be reduced, but this is a task for another day. We also do not have to store a local digest copy if the API allowed reading a partial digest. CQ-DEPEND=CL:314883 BRANCH=none BUG=chrome-os-partner:43025, chromium:564862 TEST=all tests pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 SUCCESS: sha1:single 0 SUCCESS: sha256:single 0 /New max timeout: 1 s SUCCESS: sha256:finish 1 SUCCESS: sha1:finish 3 SUCCESS: sha256:finish 2 Change-Id: Iaef3a230469de129e72418814e1d113b447c0137 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314695 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* cr50: SHA1 and SHA256 implementation with hardware supportnagendra modadugu2015-11-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | This change includes hardware and software support for SHA1/256 on CR50. When running in the RO image, only hardware sha256 support is included. When running in the RW image, the code auto-selects between the software and hardware implementation. Software implementation path is taken if the hardware is currently in use by some other context. Refactor the CR50 loader to use this abstraction. The existing software implementation for SHA1 and SHA256 is used for the software path. CQ-DEPEND=CL:*239385 BRANCH=none TEST=EC shell boots fine (implies that SHA256 works) BUG=chrome-os-partner:43025 Change-Id: I7bcefc12fcef869dac2e48793bd0cb5ce8e80d5b Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313011
* Kunimitsu: Add S0ix on SLP_S0 assertionKyoung Kim2015-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep and EC is eligable to enter heavy sleep idle task. Wakeup from S0ix by lid open, any key press, power button or track pad will be done by PCH block by asserting SLP_S0. At S0ix, 1 msec pulse will be generated every 8sec and this signal should be ignored since this is NOT S0ix entry/exit related and defered interrupt for SLP_S0 were added. BRANCH=master BUG=none TEST=in OS shell, run following commands. Following command is valid with coreboot with S0ix patches. "echo freeze > /sys/power/state" then, Measure EC power consumption and compare it with one in S0. And on EC console, there should be NO periodic message, "power state 4 = S0ix, in 0x001d" every 8 sec. Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307947 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add power signal interrupt storm detectionShawn Nematbakhsh2015-11-191-0/+7
| | | | | | | | | | | | | | | | Power signal interrupt storms are difficult to detect without extensive debugging, so add a config option to help detect them in SW. BUG=chromium:557988 BRANCH=None TEST=None Change-Id: I590ac8883e7615d05fd326245abade212b79e297 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313170 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* add the 'extension' command frameworkVadim Bendebury2015-11-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a facility which would allow to compile in callbacks for arbitrary commands passed over various communication protocols. Typically this will be used for testing, when various test commands are multiplexed over an existing protocol. The callbacks are associated with 16 bit command codes. On input the callback receives a buffer, containing the command's argument, the size of the command argument and the maximum size of the buffer. On output the callback stores processing result in the same buffer and updates the size to the actual amount of returned data. Callback descriptors are stored in a dedicated read only section which is scanned by extension_route_command() to find a callback associated with a certain command code. A console channel is also being introduced to allow controlling console output generated by extension commands handlers. BRANCH=none BUG=chrome-os-partner:47524 TEST=none yet Change-Id: I8ae16a78ca7d72176a5e7f74dd7a232078e7c06c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312586 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* motion: minium interval between motion task now a variableGwendal Grignou2015-11-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | On Ryu EVT2, where sensors share a 100kb i2c bus with other device, when the sensors set to their maximal frequency and sampling interval set to 5ms, the power management task would wait forever for the i2c lock. Increase the minimal amount of time the task can wait from 3ms to 8ms in that case. This is not an issue for Ryu PVT where the sensors are on a separate SPI bus. However, on EVT, when setting the accelerometer/gyro over 125Hz, EC won't be able to deliver the data in non-batched mode. BRANCH=smaug BUG=b:25510300 TEST=Without this change, an evt2 board would crash when plugging/unplugging the charger while the sensors are set with: echo 200000 > iio:device0/frequency # Accel echo 5 > iio:device0/sampling_frequency echo 200000 > iio:device1/frequency # Gyro echo 25000 > iio:device2/frequency # Mag Change-Id: Idb30da9ab8da61284388db73365c37be3a250dec Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311755 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* console: Add support for using EC-3PO console.Aseda Aboagye2015-11-111-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new CONFIG_* option. To utilise the experimental console, simply define the following config option in the board's board.h file. #define CONFIG_EXPERIMENTAL_CONSOLE This is a temporary option which allows the EC console to be work with the EC-3PO interactive console interface. When this option is enabled, the EC expects commands to packed in a particular format. This is for command integrity and allows the interpreter to perform automatic command retrying in the event that a character is dropped from the sent command. It also removes a lot of the console editing methods since they are now being served by EC-3PO. Once the EC-3PO interpreter is pulled into servod, we can enable this feature by default and the config option can go away. BUG=chrome-os-partner:46054 BRANCH=None TEST=make -j buildall tests TEST=Enable CONFIG_EXPERIMENTAL_CONSOLE on GLaDOS; Flash EC and verify that console works via the EC-3PO interactive console interface. TEST=Build and flash on GLaDOS and verify normal console operation on standard EC UART. CQ-DEPEND=CL:308615 Change-Id: I5e66eb94e31299b27ce029b7f7ce6ba0a7fb6816 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/309991 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: make customized RO workVadim Bendebury2015-11-101-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes introduction of building of proper RO and RW images for cr50. A few small mods were required: - both RO and RW images have to be signed, using the same dedicated signer, but with different keys, dev_key.pem is not needed any more. - the RW image offset is not at the half of available flash, a chip specific value of 16K is used instead. The suggested new image layout is as follows: +----------------------------------------+ | 1KB RO signature header. | +----------------------------------------+ - - | 15KB RO image. | - - +========================================+ | 1KB RW-A signature header. | +----------------------------------------+ - - - - | 239K RW-A image. | - - - - +========================================+ - - | 16 KB NVRAM, shared | - - +========================================+ | 1KB RW-B signature header. | +----------------------------------------+ - - - - | 239K RW-B image. | - - - - +========================================+ BRANCH=none BUG=chrome-os-partner:43025 TEST=The combined image (build/cr50/ec.hex) is successfully loaded and started by the spiflash utility from the latest FPGA tarball. Corrupting a byte in the generated image in the RW section causes failure to verify. Change-Id: I41a05168b0d4e9f88efa1003f261b6dd03972a24 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311422 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tcpm: Add configuration struct for tcpc i2c paramsShawn Nematbakhsh2015-11-081-1/+1
| | | | | | | | | | | | | | | | | | | Add a new configuration struct tcpc_config_t that initially defines the i2c host port and i2c slave address of all TCPCs present on the board. This will allow us to create boards with multiple TCPCs on different i2c ports, with arbitrary i2c slave addresses. BUG=chromium:551078 TEST=Manual on glados. Verify PD communication / charging is still functional on both PD ports. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9b2bde85d7f1642e8727c052e064371be7967619 Reviewed-on: https://chromium-review.googlesource.com/311000 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Disable customized RO image by defaultBill Richardson2015-11-061-0/+7
| | | | | | | | | | | | | | | | | | | | | A previous commit caused ToT to use a not-yet-working bootloader. This disables that bootloader by default so that the rest of us can continue to work. ;-) A configuration option is added to be able to address this issue in the future with other boards as well. BRANCH=None BUG=chrome-os-partner:43025, chromium:551151 TEST=make buildall -j Also verified that both normal and customized cr50 RO images build and work as expected. Change-Id: Ie433b07860cb1b04c12b2609c6fa39025fc0e515 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310978
* chg: add narrow VDC power path supportRong Chang2015-11-051-0/+3
| | | | | | | | | | | | | | | | | | Under NVDC, BGATE natively has a body diode. Hence there's a discharging path if VSYS is lower than VBAT. This change keeps VSYS voltage when turning off charging. BRANCH=none BUG=chrome-os-partner:46698 TEST=manual make buildall -j load on boards with isl9237 charger. charge the battery to full, and check charging voltage and current. Change-Id: I8a6046444dd40a3b57f034be124b9e8fe281de40 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309289 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Initial commit of TCPM driver for FUSB302.Gabe Noblesmith2015-11-041-0/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=PD contract established with various devices Change-Id: I4b452befe9ccd9d67bd6ad5c8cf77ae58320f6af Signed-off-by: Gabe Noblesmith <gabe.noblesmith@fairchildsemi.com> Reviewed-on: https://chromium-review.googlesource.com/294924 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-031-2/+5
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* pd: turn on CONFIG_USB_PD_LOW_POWER by defaultAlec Berg2015-10-301-1/+1
| | | | | | | | | | | | | | Define CONFIG_USB_PD_LOW_POWER by default to save power on both TCPM and TCPC side by waking PD task less often when possible. BUG=none BRANCH=none TEST=test on glados and samus. Change-Id: I04441fb8339652cf073689177175a98f28807897 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309311 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charger: Add LIMIT_POWER charger param for low bat + weak chargerShawn Nematbakhsh2015-10-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for two new configs to specify critical energy battery percentage and critical external charger power. When we are under both thresholds, set the LIMIT_POWER charger parameter to inform the AP that it should conserve power to avoid brownout, and consider jumping to EC RW to negotiate PD. In addition, modify the existing CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON to allow power-up regardless of power level if a 15W+ charger is attached, since there is a reasonable chance it may speak PD and provide sufficient power to boot the AP. BUG=chromium:537269 TEST=Manual on Glados. Set CHG_MW thresh to 20000, BAT_PCT to 50. Verify that LIMIT_POWER charger param is set until Zinger negotiates to 20V. Also veify that system can boot with Donette. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic963c82fea4ad10e8a5d7e476c5ce3e5ae525dad Reviewed-on: https://chromium-review.googlesource.com/306774 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: get battery information from charge stateMary Ruthven2015-10-271-0/+1
| | | | | | | | | | | | | | | | | | ARM systems currently use SBS kernel driver which talks to the battery through I2C passthu in the EC. Instead when asking for battery information try getting it from the charge state machine first, and then try the battery if charge state does not have the information. This reduces latency by cutting out the battery response time. BUG=chromium:484841 BRANCH=none TEST=check that power_supply_info works properly on Jerry Change-Id: If4da15ccabe412adc31fc94b189089ebb3e9265c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307905 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* common: Add lightbar dimming based on outside light.Gwendal Grignou2015-10-201-0/+3
| | | | | | | | | | | | | | | | Unless the lid is closed, the ALS is used for lightbar dimming. Change the google colors depending on the light sensor result. BUG=chrome-os-partner:44400 BRANCH=smaug TEST=Check all 3 levels of brightness of the lightbar. Check value using "adb shell ectool lightbar" Check double tap color are not affected and is using full brightness. Change-Id: I7b5e2890c3557f1dd3ae719f5f82ffb5fe7b24fb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301216 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* driver: Add L3GD20H gyrometer basic driver supportBolat Dinc2015-10-201-0/+3
| | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:40465 BRANCH=None TEST=Added Gyro config to test L3GD20H Gyro sensor in Kunimitsu. Able to read the gyro data from "accelinfo" console command. Rotated the sensor in X,Y,Z axis, respective axis values change. Fits into the existing accel/gyro framework. Change-Id: I19369560ddad5160c2fc9c7ef9823bd37b5389fa Signed-off-by: Bolat Dinc <bolat.dinc@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/264650 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* port80: Remove HAS_TASK_PORT80.Aseda Aboagye2015-10-191-10/+0
| | | | | | | | | | | | | | | | | | | | | | The only boards that had a port 80 task were the ones using the MEC1322. Since that EC now has a dedicated timer interrupt configured for port80 writes, we can remove this code that was providing the port 80 task. Additionally, the config option CONFIG_PORT80_TASK_EN is removed. BUG=chrome-os-partner:46062 BRANCH=None TEST=make -j buildall tests CQ-DEPEND=CL:305591 Change-Id: I145d989b8872240e749ef77aabe0ae76fc94d443 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305791 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados_pd: oak_pd: add and enable option for i2c slave onlyAlec Berg2015-10-191-0/+3
| | | | | | | | | | | | | | Add CONFIG_I2C_SLAVE_ONLY for boards that only operate as a slave on i2c. BUG=chrome-os-partner:41959 BRANCH=none TEST=make BOARD=glados_pd and see 2kB flash savings Change-Id: I30831ce48b391d985c25e266229d5c6f2312042b Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306783 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add support to reclaim space from loader.Aseda Aboagye2015-10-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain ECs which cannot load both the RO and RW images into memory simultaneously have a little firmware (LFW) loader that is loaded into the beginning of the program memory. This loader is responsible for loading the RO/RW images, however once we begin executing code from main(), the loader has already completed it's purpose. We can reuse this space by allocating portions of the .bss section here. This currently saves us 3k for mec1322. This section is .bss.slow. To use this feature simply define the following config option in board.h. #define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW In some cases, such as the mec1322, this region of RAM is optimized for code and not data. Therefore, ideally infrequently used data should go into this region. BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro; Verify we are back in ro. TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow section. TEST=make -j buildall tests Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305254 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add magnetometer online calibration.Gwendal Grignou2015-10-131-0/+3
| | | | | | | | | | | | | | | | Code for hard iron calibration: Every seconds (or faster if enough samples), find a sphere that fit the compass data. Based on Android code. BRANCH=smaug BUG=chrome-os-partner:39900 TEST=Check hard-iron bias is removed. Works better outside. Change-Id: Iab479d5113b6560b4f01b0fd87373d2eecdb9b54 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299583 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* pd: Cleanup usb_pd low power idle sleep maskShawn Nematbakhsh2015-10-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Add a new define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED that indicates the chip should try to go to low power idle even when a PD connection is established -- this is the current behavior only for Zinger. Also, enable and disable the sleep mask bit from tcpc on rx enable / disable. BUG=chrome-os-partner:45010 TEST=Manual on glados / glados_pd. Insert Zinger, verify that glados_pd stays out of low power idle. Remove Zinger, verify that glados_pd resumes going into low power idle. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie763ae75f4459f56cad47d77d9c25d76358aa484 Reviewed-on: https://chromium-review.googlesource.com/303490 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mkbp_event: prevent AC power change events to wakeup AP.Ben Lok2015-10-061-0/+6
| | | | | | | | | | | | | | | | | | It may use MKBP event to send PD power change events to AP via interrupt. According to the spec, AC power change events do not be allowed to wake up AP. In order to avoid it, define a white list in board level, only allow those events to wakeup the AP during S3 power state. BRANCH=none BUG=chrome-os-partner:45127 TEST=manual Plug PD power adapter to oak, if system is in S3/S5 and it should starts charging, but should not wake up system/AP at all. Change-Id: I2f86697d5d3bd24d7de840e21064b91e8841f0eb Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/300360 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Allow EC to request PD hibernate via host commandShawn Nematbakhsh2015-10-051-0/+4
| | | | | | | | | | | | | | | | | | | On some systems, we may wish to have the PD follow the EC into hibernate. Add a status field to EC_CMD_PD_EXCHANGE_STATUS to support this. BUG=chrome-os-partner:45010 TEST=Manual on glados with subsequent commit. Run 'hibernate' on EC console, verify that both EC and PD go to hibernate. Plug zinger and verify that both EC and PD wake, AP boots, and battery begins charging. BRANCH=None Change-Id: I0476bc8a47ffb0fe113dccda9d4f8074105c1c84 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302712 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ryu: export board versionVincent Palatin2015-10-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Export the board version through the usual EC_CMD_GET_BOARD_VERSION. Add an option to use the board-specific board_get_version() callback rather than doing the generic GPIO binary decoding since here the version is ternary encoded. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=none TEST=execute 'ectool boardversion' on the AP and see the right number. Change-Id: I89c328573d09be02232756797ba3fdd5979b0292 Reviewed-on: https://chromium-review.googlesource.com/303368 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 6c620c51e5ab812b4e6751e4c630da2e6bee4b74) Reviewed-on: https://chromium-review.googlesource.com/303803 Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* charge_state_v2: add option to cut-off battery when level is criticalVincent Palatin2015-10-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | Add a build option CONFIG_BATTERY_CRITICAL_SHUTDOWN_CUT_OFF to perform a battery cut-off when we reach the battery critical low level. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=none TEST=Discharge a Ryu device down to the critical level, see the message and verify we cannot restart with the power button. Also check that plugging the charger revives the device and starts charging. Change-Id: Ic132a658de5c5131a6a1dd1ce343196b68d480f6 Reviewed-on: https://chromium-review.googlesource.com/303549 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 80b3c99319771312d5733b126b6b3eb839addde9) Reviewed-on: https://chromium-review.googlesource.com/303812 Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Driver: ISL9237: Monitor system power consumptionVijay Hiremath2015-10-021-0/+4
| | | | | | | | | | | | | | | | | | | Added code to enable the system power monitoring functionality to get the details of the system power consumption. And also added EC console command "psys" to get the system power consumption. BUG=none TEST=Manually tested on Kunimitsu. Power = Voltage * Current, reading is equal to the power readings from the psys command. BRANCH=none Change-Id: I62519ac96800363b67cab23cd9eb0dcac229cb47 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/302472 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: motion: Separate motion task interval from AP configurationGwendal Grignou2015-09-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | Some sensors are in forced mode, motion sense must be scheduled at their ODR. However the host may not want the data right away, so motion task may not wake up the host that often. Add a new variable motion_int_interval that defines the maximum interval between FIFO host event. BRANCH=smaug BUG=chrome-os-partner:43800 TEST=Check that light sensor is polled at ODR frequency. Check that when AP does not want any event, no FIFO host event are requested. Check CTS tests work as before. Reenable motion_lid unit test. Change-Id: Ie25e6cbe28fed899073856057855ffa03c0cd9fd Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301134 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Remove redundant CONFIG_RAM_* configsShawn Nematbakhsh2015-09-291-12/+0
| | | | | | | | | | | | | | | | | RAM need not be preserved between jumps from the loader to RO/RW images, so there is no need for a separate region of loader RAM. Remove redundant CONFIGs which define this unneeded region. BUG=None TEST=Verify glados boots and sysjumps successfully. BRANCH=None Change-Id: I2567f17a973c6f9f00bcfd97a4581d6c4b6fd6f0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302586 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Handle signed RW images a bit cleanerBill Richardson2015-09-251-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | For signed EC RW images (CONFIG_RWSIG), there's no point in embedding the public key or signature into the image itself since it will just be replaced by the signer (either as the next step in the build process, or after the fact for MP releases). This takes that out and just points to where the pubkey and signature will be placed. BUG=none BRANCH=none TEST=make buildall I also checked the signatures with futility show -t build/*/ec.bin They still look good, and the one signed image I booted (Cr50) works as before. Change-Id: Ib39b7c508914851f81a1bebb2450e08ef0def76c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302630 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CONFIG_FW_IMAGE_SIZEShawn Nematbakhsh2015-09-241-1/+0
| | | | | | | | | | | | | | | | | | Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may theoretically be different sizes), it is no longer useful to globally define the size of an image. BUG=chromium:535027 BRANCH=None TEST=`make buildall -j`. Also, verify glados / glados_pd continue to function as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8 Reviewed-on: https://chromium-review.googlesource.com/301743 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: add command spixferGwendal Grignou2015-09-231-0/+1
| | | | | | | | | | | | | | | | Similar to i2c_xfer: allow access to a SPI device registers. We assume the protocol use is set MSB bit to the offset for read operation. id is the index of the device in spi_devices. BRANCH=smaug TEST=Read/Write SPI registers. BUG=none Change-Id: Id4aaffbb6f514fd47086aee240b556ea23298d33 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289857 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* motion: Add Gesture InterfaceGwendal Grignou2015-09-181-2/+22
| | | | | | | | | | | | | | | Add an interface with the host to set up gesture recognition. Today, only significant motion is supported. Add a virtual sensor for concentrating gesture support from host. BRANCH=smaug BUG=b:23570481 TEST=On ryu, enable significant motion from host. Change-Id: I906fa2d2d7b4ca2771ea2f58b91de8d97bf4e2e3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296213
* common: motion: move gesture actions in motion task.Gwendal Grignou2015-09-181-1/+3
| | | | | | | | | | | | | | Change the IRQ interface to allow adding events. Move code to send the lightbar sequence from gesture.c to motion task. TEST=compile, works on Ryu. BRANCH=smaug BUG=chrome-os-partner:44754 Change-Id: I981ea123ebef0e8e3d6aa320eade89f10e83b6fc Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296822 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Add support for flash write & eraseBill Richardson2015-09-181-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds flash support for the SoC. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual Pick an unused section of flash and use the flasherase and flashwrite commands to test it. The flashwrite command fills a buffer with bytes, counting up (0x00, 0x01, 0x02, 0x03, ...), then writes that buffer to the address given. Note that the "md" command uses the absolute address, while the flash commands use the offset address within the flash memory. For example: Test bank 0: > md 0x7b000 16 0007B000: 00000000 00000000 00000000 00000000 0007B010: 00000000 00000000 00000000 00000000 0007B020: 00000000 00000000 00000000 00000000 0007B030: 00000000 00000000 00000000 00000000 > flasherase 0x3b000 0x800 Erasing 2048 bytes at 0x3b000... > md 0x7b000 16 0007B000: ffffffff ffffffff ffffffff ffffffff 0007B010: ffffffff ffffffff ffffffff ffffffff 0007B020: ffffffff ffffffff ffffffff ffffffff 0007B030: ffffffff ffffffff ffffffff ffffffff > > flashwrite 0x3b000 0x800 Writing 2048 bytes to 0x3b000... > md 0x7b000 16 0007B000: 03020100 07060504 0b0a0908 0f0e0d0c 0007B010: 13121110 17161514 1b1a1918 1f1e1d1c 0007B020: 23222120 27262524 2b2a2928 2f2e2d2c 0007B030: 33323130 37363534 3b3a3938 3f3e3d3c > md .b 0x7b000 16 0007B000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f Test bank 1: > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flasherase 0x7b000 0x800 Erasing 2048 bytes at 0x7b000... > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flashwrite 0x7b000 0x800 Writing 2048 bytes to 0x7b000... > md 0xbb000 16 000BB000: 03020100 07060504 0b0a0908 0f0e0d0c 000BB010: 13121110 17161514 1b1a1918 1f1e1d1c 000BB020: 23222120 27262524 2b2a2928 2f2e2d2c 000BB030: 33323130 37363534 3b3a3938 3f3e3d3c > md .b 0xbb000 16 000BB000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f > Change-Id: I956e813871949faed8d85ad9e46bdc64dee1a9e9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299757
* it8380dev: fix idle task and chip idDino Li2015-09-181-0/+3
| | | | | | | | | | | | | | | | | | | | | 1. Fix system_get_chip_name() and system_get_chip_revision(). 2. Fix EC doze mode. 3. Enable LPC cycle wake-up EC from doze / deep doze function. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console "version". Chip: ite it8390 cx 2. EC doze mode is normally. 3. ectool "version" command x 2000. Change-Id: I167dbfb965e557eb86ed83f45a945e4315f5fa9f Reviewed-on: https://chromium-review.googlesource.com/299110 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
View Lorry Controller Status