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* charger: add sy21612 buck-boost converter driverRong Chang2017-11-291-0/+1
| | | | | | | | | | | | | SY21612 is buck-boost converter with selectable source/sink mode. BRANCH=none BUG=none TEST=none Signed-off-by: Rong Chang <rongchang@chromium.org> Change-Id: I71248eedd9be775790d71010f69dfae41cd64a27 Reviewed-on: https://chromium-review.googlesource.com/673964 Reviewed-by: Benson Leung <bleung@chromium.org>
* sb_fw_update: Get rid of CONFIG_SB_FIRMWARE_UPDATEFurquan Shaikh2017-11-281-3/+0
| | | | | | | | | | | | | CONFIG_SB_FIRMWARE_UPDATE is dead on ToT. So, get rid it completely. BUG=b:69695376 BRANCH=None TEST=make -j buildall Change-Id: Ic1eedff21d82f729a73ec9a7c1d554b6b571e827 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/792013 Reviewed-by: Shawn N <shawnn@chromium.org>
* Separate VBUS detection and measurement mechanismsPhilip Chen2017-11-271-0/+11
| | | | | | | | | | | | | | | | | | | For now we guard charger-based VBUS voltage measurement behind CONFIG_USB_PD_VBUS_DETECT_CHARGER. But we should be able to measure VBUS voltage by charger while detecting VBUS presence by other methods. BUG=b:67991345 BRANCH=none TEST=plug in guppy on Scarlet rev2, 'ectool usbpdpower' on console, and see VBUS is measured as 4975mV Change-Id: I94cada81159ea4b097001997e2444873ec2d8763 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/789910 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hammer: enable large block reading on usb i2c passthru.Chun-Ta Lin2017-11-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Originally, i2c passthru is limited to use I2C_XFER_SINGLE flag where it can only read at most 255 bytes at a time. For application that requires larger i2c bus reading, we change the flag setting and the command protocol. TEST=old ./touchpad_updater still works (previous protocol) TEST=new ./touchpad_updater can get more than 500 bytes per transaction TEST=Debug message only print when -d assigned. ./touchpad_updater -d TEST=Manually change #define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 6) to #define CONFIG_USB_I2C_MAX_READ_COUNT (1024 - 4) and trigger POWER_OF_TWO assertion. BRANCH=none BUG=b:35587174, b:63993891 Change-Id: Id75b11ea49ba89bab8e18af24d47219030c778c5 Signed-off-by: Chun-Ta Lin <itspeter@google.com> Reviewed-on: https://chromium-review.googlesource.com/542716 Commit-Ready: Chun-ta Lin <itspeter@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-171-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add software CTZ implementation when needeedGwendal Grignou2017-11-161-0/+3
| | | | | | | | | | | | | | | | | CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or nds32. Used in ST sensor drivers. BUG=none BRANCH=none TEST=compile Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767609 Commit-Ready: Ely Vazquez <nadia198877@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* poppy: Lower sensor max ODRGwendal Grignou2017-11-151-2/+9
| | | | | | | | | | | | | | | | EC seems to miss sample while providing sensor data at 200Hz. Limit sensors ODR to 100Hz. BUG=b:67112751 BRANCH=none TEST=compile, tbd Change-Id: Ic324c3d989854ae8b7f6b27bf6338266ce01ceda Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/753434 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* gru: Remove `flashinfo` command for RAM savingsShawn Nematbakhsh2017-11-091-0/+1
| | | | | | | | | | | | | BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ibfbb6875327dfc13dcba57933d39fd207f382ac1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/761299 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* bd9995x: Use fixed PD-port-to-VBUS/VCC mappingShawn Nematbakhsh2017-11-071-7/+0
| | | | | | | | | | | | | | | | | The bd9995x driver was written to allow any PD port # to be VBUS or VCC, but the mapping is broken in a few places. Since all boards use VBUS = port 0, remove the conversion entirely. BUG=chromium:781849 BRANCH=kevin TEST=Verify PD and BC1.2 charging still works on kevin. Change-Id: I3687866835d1684342d9f746d91b3a6079ab5cc4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/755000 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charge_manager: Enter safe mode at bootShawn Nematbakhsh2017-11-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Charge port / current selection often needs to be significantly altered when a battery cannot provide sufficient charge, so have charge_manager initially enter safe mode. After a battery with sufficient capacity has been identified, charge manager will leave safe mode, and port / current selection will return to standard rules. BUG=chromium:777596 BRANCH=None TEST=Pass charge_manager unit tests. On kevin, remove battery, attach Apple PD charger, verify safe mode is not exited and device does not brown out. Hot-plug battery and verify safe mode is exited. Next, remove battery, attach to Samus, verify safe mode is not exited and device doesn't brown out. Hot-plug battery, verify that safe mode is exited and no active charge port, due to dual-role exclusion. Change-Id: I7784865750087a037aad8dbbac058b22c77ba6d4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/733954 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: add IT5205 mux driverDino Li2017-10-311-0/+3
| | | | | | | | | | | | | | | | Add support the ITE IT5205 Type-C USB alternate mode mux. BRANCH=none BUG=none TEST=1. Successfully verify chip ID. 2. Verify set_mux() and get_mux() functions set and return consistent values. 3. The mux control register setting as expected after set_mux(). Change-Id: I9ff066dc9e74683df1371b70290e2aeaa86cb96b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/741211 Reviewed-by: Shawn N <shawnn@chromium.org>
* port80: Clean up macrosFurquan Shaikh2017-10-311-0/+3
| | | | | | | | | | | | | | | | | 1. Add a new config option to define history buffer length. This allows boards to override this option if required. 2. Get rid of unused PORT80_POLL_PERIOD macro BUG=None BRANCH=None TEST=Verified that all port80 messages from a boot-up or S3 resume are present in port80 history buffer. Change-Id: Ie64680459f58358713a1b1445a0b99fcfe1c1cdc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745902 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* twinkie: clean-up disabled SNIFFER_HEADER_V2 codeVincent Palatin2017-10-311-8/+0
| | | | | | | | | | | | | | | | | Remove all the CONFIG_USBC_SNIFFER_HEADER_V2 code, it was not fully satisfactory and we have a better alternative. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=make BOARD=twinkie Change-Id: I26d3396b2933be5276f916e3ac60c96347cb67f6 Reviewed-on: https://chromium-review.googlesource.com/743015 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/npcx: Add support for pad-switching UARTNicolas Boichat2017-10-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NPCX5* only has one UART controller, which can be switched between 2 pads. We keep the default pad for EC console, however, we allow switching to the alternate pad for short, infrequent, transactions. Both pads are assumed to use the same baudrate and other line settings. When switching pad, we first configure the new pad, then switch off the old one, to avoid having no pad selected at a given time, see b/65526215#c26. Because of the added complexity of npcx_gpio2uart (and the fact that it uses the global variable "pad" define in uart.c), we move the implementation to uart.c (npcx_uart2gpio is also moved for consistency). When the pad is switched to alternate pad, characters input and output on the EC console (default pad) would be lost. To compensate for this, we: - Switch back to main pad in case of EC panic, so that output is shown on EC console. - Immediately abort current alternate pad transaction if a character is received on the default pad. Note, however, that the first character will be lost (this can be worked around by telling user to press enter, and have servod/FAFT always send 2 blank lines (instead of just one) before sending a command). - Inhibit pad switching for 500ms after receiving a character on default pad. Assuming a reasonable typing speed, this should allow developers to type console commands relatively comfortably, while not starving the alternate pad communication for too long. The logic above could be simplified significantly by implementing software flow control (XON/XOFF, see b/67026316). BRANCH=none BUG=b:65526215 TEST=While follow-up CL that writes long 1k buffers, the following works fine: - type 'uart' in EC console - Read battery power consumption from servod, which "types" in the EC console: while true; do dut-control ppvar_vbat_mw; sleep 1; done no failure is seen. TEST=Add this test code in uart_alt_pad_read_write, after the pad has been switched, and check that panic information is consistently printed correctly: { static int t; if (t++ > 20) t = t / ret; } Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/659458 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* PD: Make current USB PD Stack REV 3 compliantSam Hurst2017-10-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement the following required features in the USB PD Rev. 3.0 specification. Not_supported control message: Inform a port partner that a particular message is not supported. Battery capabilities extended message: Report battery design capacity and last full charge capacity. Battery status data message: Report battery state of charge Collision avoidance: New scheme to avoid collisions caused when both source and sink want to send messages. Cable communication: Only the VCONN source can communicate with the cable plug. This is NOT implemented because although the drivers have the capability of communicating with a cable plug, the PD stack doesn't currently need to talk to a cable plug. This is okay since the current PD design doesn't source or sink more than 3 amps and all Type-C cables are required to be 3 amp capable. BUG=b:64411727 BRANCH=None TEST=`make -j buildall` Passed relevant PD Rev 2.0 compliance tests Successful PD negotiation with PD Rev 2.0 and 3.0 chargers Tested with low power none PD charger. Modified a Kevin to operate as a PD 3.0 charger and sent all required messages and verified the return messages. Also tested collision avoidance by verifying that a sink only transmits when the source indicates it's okay. Used Twinkie to verify that PD was operating as v3.0. Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: Ifd77e92ec4e9106236f9221393d2bfb97263d979 Reviewed-on: https://chromium-review.googlesource.com/603003 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* driver: ppc: Add support for TI SN5S330.Aseda Aboagye2017-10-231-0/+4
| | | | | | | | | | | | | | | | | | | | This commit adds a basic driver for the TI SN5S330. This driver just sets up the IC and provides an API to turn on or off the PP2 FET. BUG=b:67663166, b:67663124 BRANCH=None TEST=Enable code for zoombini; Flash a board which has the SN5S330 stuffed; Verify that we're able to perform PD negotiation and negotiate all the way up to 20V. TEST=Boot only on AC. sysjump to RW, verify that board does not brownout. Change-Id: I9c147ee8465eed878843cf902db301d62e8f627e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/722104 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* power: Add task-safe API to control 5V rail.Aseda Aboagye2017-10-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For certain cannonlake designs, the 5V rail can be controlled by both the chipset task as well as other tasks such as the USB charger tasks to perform BC1.2 detection. This commit introduces an API that allows the tasks to enable/disable the 5V rail. Enable requests will immediately enable the rail, however, attempting to disable the rail will only result in a request. Once all tasks want to turn off the 5V rail, the rail will be turned off. A bitmask is introduced to keep track of the requests. Index 0 is for the chipset task. All of this is gated behind a config option: CONFIG_POWER_PP5000_CONTROL BUG=b:65991615 BRANCH=None TEST=With other zoombini code, verify that 5V can be enabled and disabled. Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/722322 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Remove ACCESSORY statesShawn Nematbakhsh2017-10-191-5/+0
| | | | | | | | | | | | | | | | | | | According to the USB-C spec, when a debug accessory is identified, we may optionally establish USB PD communication over CC. Some DTS partners (eg. servo_v4) expect us to speak PD, so let's make it so. There is no need for special ACCESSORY states, these do not exist in the PD spec. BRANCH=servo BUG=chromium:737755,b:65837068 TEST=On scarlet, attach servo_v4 and verify scarlet charges. Also verify EC and cr50 consoles are available through servo_v4. Change-Id: I59d1ca50b4766509eccf38562cdf926578138585 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/693294 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Add "freeze" dual-role policyShawn Nematbakhsh2017-10-191-0/+3
| | | | | | | | | | | | | | | | | Add a new DRP policy to "freeze" the power role of each port, never toggling automatically, though manual role swaps may still occur. BUG=chromium:769895 BRANCH=servo TEST=On servo_v4, verify DUT port stays in SRC role and POWER port stays in SNK role while disconnected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ibff3cd1ffaf0e884b030c231003763a57acbe02e Reviewed-on: https://chromium-review.googlesource.com/715276 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add CONFIG_IGNORE_G_UPDATE_CHECKSMarius Schilder2017-10-181-0/+5
| | | | | | | | | | | | | | | | In some scenarios we want to take RW updates w/o taking version numbers into consideration, much like the behavior we get w/ CR50_DEV. But then without the additional CR50_DEV features enabled for the rest of the code. BRANCH=none BUG=none TEST=compiles Change-Id: I7dd946ab77bbdc35850ed934cd53735418e13845 Reviewed-on: https://chromium-review.googlesource.com/724967 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Trybot-Ready: Marius Schilder <mschilder@chromium.org>
* [fan] Add CONFIG_FAN_SPEED option to override EC fan speedChris Ching2017-10-131-0/+3
| | | | | | | | | | | | | | | | Fans will be initialed at the given RPM, and not the max speed. Changed kahlee to use new method and set speed to ~50%, down from 75% BUG=b:67055475 TEST=run on kahlee board BRANCH=none Change-Id: Iad40a58b531f46ac80572b47aef9378b47222be1 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://chromium-review.googlesource.com/714386 Commit-Ready: Chris Ching <chingcodes@chromium.org> Tested-by: Chris Ching <chingcodes@chromium.org> Reviewed-by: Chris Ching <chingcodes@chromium.org>
* cleanup: Use CONFIG_BATTERY to indicate whether a board has a batteryShawn Nematbakhsh2017-10-131-1/+13
| | | | | | | | | | | | | BUG=b:35528297 BRANCH=None TEST=`make buildall -j` Change-Id: I9e4814b4172f20711f7edd691c9569f9130aec8e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/713395 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* motion_sense: Add CONFIG_DYNAMIC_MOTION_SENSOR_COUNT config optionScott Collyer2017-10-111-0/+2
| | | | | | | | | | | | | | | | | | | | | Some projects, such as Coral use a common image to support different SKUs. In this case the number of motion sensors supported may need to be determined at runtime. CONFIG_DYNAMIC_MOTION_SENSOR_COUNT removes the const assumption for the global variable motion_sensor_count. Based on CL https://chromium-review.googlesource.com/444587 BUG=b:38271876 BRANCH=None TEST=make -j buildall Change-Id: I4dd3384d245641136f3329b60d1d941927366387 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/711194 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* chip/stm32/clock: Optionally use LSE as RTCCLKPhilip Chen2017-10-111-0/+3
| | | | | | | | | | | | | | | | | | | | The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz. To use stm32 RTC for applications requiring accurate timing, let's setup LSE (a more accurate clock source) as RTCCLK. Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally. BUG=b:63908519 BRANCH=none TEST=boot scarlet rev1 and wait for an hour, confirm rtc time == kernel system time. Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/679601 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charge_ramp: Move ramp allowed / ilim callbacks to common codeShawn Nematbakhsh2017-10-061-3/+3
| | | | | | | | | | | | | | | | | | | | | The decision on whether to ramp (and how high) depends on the quirks of charger identification, so move the decision out of board, into the drivers that implement usb_charger. Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better contrast with the existing CONFIG_CHARGE_RAMP_HW. BUG=None TEST=Manual on kevin, verify ramp occurs when port plugged into Z840 workstation. BRANCH=None Change-Id: I5b395274133837a18a4f4ac34b59b623287be175 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/702681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mn50: add data signing capabilityNick Sanders2017-10-061-0/+8
| | | | | | | | | | | | | | | | | | | Add a PERSO_AUTH appid to sign data passed through the AUTH mn50. Add a signer command to start and generate signatures. Clean UART init to avoid spurious nonprinting characters that will contaminate the siugnature. BUG=b:36910757 BRANCH=None TEST=generates signature for uart and spi Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I5fc3c4ee34898421060b57b774a09734f6a1bae5 Reviewed-on: https://chromium-review.googlesource.com/670984 Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cleanup: pd: Remove CONFIG_CASE_CLOSED_DEBUGShawn Nematbakhsh2017-10-051-4/+0
| | | | | | | | | | | | | | | | | | CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the common routines are only used by one board. BUG=chromium:737755 BRANCH=None TEST=`make buildall -j` Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656315 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add WebUSB descriptor supportVincent Palatin2017-09-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | The WebUSB specification defines a specific Platform Descriptor in the Binary Object Store: https://wicg.github.io/webusb/#webusb-platform-capability-descriptor This descriptor provides a special 'Landing page' URL to the host browser and associated privileges for it. Bump the USB version for BOS descriptors to 2.1 to be compatible with Chrome implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=none BRANCH=twinkie TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6 Reviewed-on: https://chromium-review.googlesource.com/664813 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Makefile: Generate hashes for the touchpad FWNicolas Boichat2017-09-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the passed TOUCHPAD_FW parameter to the make command, the build system generates hashes for the touchpad FW. To generate the hashes, gen_touchpad_hash splits the touchpad FW in blocks of CONFIG_UPDATE_PDU_SIZE, that are hashed individually (SHA-256), and then stored in the EC image. This will allow the USB updater code to verify the integrity of the touchpad firmware being flashed. When no FW is provided, zeros are output, which do not match any valid data. BRANCH=none BUG=b:63993173 TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j TEST=Using variations of make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_4.0.bin \ BOARD=hammer -j make BOARD=hammer -j Check that TPHASH touchpad_fw_hash.h is only regenerated when the parameter changes. Change-Id: Ie347270aa9c00342de13489c9422e45e681b94c2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615321 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* port80: Disable default print of port80 messages in interrupt contextFurquan Shaikh2017-09-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add a new config option CONFIG_PORT80_PRINT_IN_INT which is disabled by default to disable printing of port80 messages in interrupt context. 2. If CONFIG_BRINGUP is defined, redefine CONFIG_PORT80_PRINT_IN_INT to enable printing of port80 messages in interrupt context for boards that are in bringup phase. 3. If print_in_int is disabled, add a deferred call to dump port80 buffer to EC console 4 seconds after the last port80 message is received. BUG=b:64196191 BRANCH=None TEST=Verified following: 1. make -j buildall 2. Port80 messages are not printed by default on Soraka 3. Port80 buffer is dumped 4 seconds after last port80 message, if BIOS is stuck for 4 seconds, in recovery mode and when reboot from AP console. 4. Boot time on soraka went down from ~1.59seconds to ~1.45 seconds in EC reboot case (savings of ~140ms). Change-Id: I9aee0987765f905b4ac49d04ffc54d71ee3a04f9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/661880 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common: add host command to push AP SKU ID to ecDevin Lu2017-09-111-0/+3
| | | | | | | | | | | | | add host command to set AP SKU ID to ec. BUG=b:65359225 BRANCH=reef TEST=make buildall -j Change-Id: I76ffa4485be4de996b001097fa3f5a371f3a92ce Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/650277 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cleanup: Remove 'ryu' boardShawn Nematbakhsh2017-09-111-3/+0
| | | | | | | | | | | | | | | Remove 'ryu' and related ryu-only code. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: I19b966ea6964a7ed083724f7de80ae192235a406 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Remove support for debug accessories that provide VBUS + RdShawn Nematbakhsh2017-09-111-3/+0
| | | | | | | | | | | | | | | | | | | Reworked suzy-q and suzy-qable all provide Rp, so there is no need for special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS is no longer relevant, since we no longer take special action when VBUS is seen without Rp. BUG=chromium:737755 BRANCH=None TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5. Also, verify zinger works in S5 on reef. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec Reviewed-on: https://chromium-review.googlesource.com/656067 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common/sha256: agressive SHA-256 unrolling as an optionNicolas Boichat2017-09-111-0/+3
| | | | | | | | | | | | | | | | Reduces "hash done" time from ~1.30 to ~1.15s on soraka. BRANCH=none BUG=chromium:702378 BUG=b:64196191 TEST=Boot soraka, looks at hash done time. TEST=make run-sha256 run-sha256_unrolled passes. Change-Id: Ia29ee27404d6e9aa615ff59755b59d3f26648e71 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/652327 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* charger: Add CONFIG_CHARGE_STATE_DEBUGRyan Zhang2017-09-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | Servo / Suzy-Q related debugging methods is a big challenge in factory especially after servo debug header is removed. Expose some information to OS from EC will do a great help for massive production. + expose charge/battery related state to ectool 1. chg_ctl_mode 2. manual_mode 3. battery_seems_to_be_dead 4. battery_seems_to_be_disconnected 5. battery_was_removed 6. disch_on_ac (learn mode state) BUG=b:65265543 BRANCH=master TEST=`ectool chargestate param 0x20000~0x20006 get correct state` Change-Id: Ic2ed38e2eb9def01be29729fa1fe1959eb73fe43 Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/646412 Reviewed-by: Shawn N <shawnn@chromium.org>
* ccd_config: Clean up help and config.hRandall Spangler2017-09-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | Minor cleanup to the 'ccd help' command. Add 'ccd get' as a clearer alias to print the config. Change CONFIG_CMD_CCDDISABLE to CONFIG_CMD_CCD_DISABLE to indicate that it's a sub-command for 'ccd'. BUG=b:65407395 BRANCH=cr50 TEST=manual ccd -> see clue for 'ccd help' ccd help -> see 'get' command ccd get -> prints config ccd disable -> error (config option isn't defined by default) Change-Id: Icbcaa178171ca948cfaae58ab1a1e73ab3d95243 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/654380 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* it83xx: clock: support e-flash clock up to 48MHzDino Li2017-09-071-0/+8
| | | | | | | | | | | | | | | | Default setting of embedded flash's clock is 24 or 32 MHz and PLL is 48 or 96 MHz correspondingly. And it8320 supports e-flash clock up to 48 MHz,so we add a new config option to support it. BRANCH=none BUG=none TEST=Run FAFT with e-flash 48MHz and test results are passed. Change-Id: I096ae3abc8fec9bd7e0556c57605e87a31ac3b07 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/645466 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove duplicate BD9995X CONFIGsShawn Nematbakhsh2017-09-021-2/+1
| | | | | | | | | | | | | BUG=chromium:700933 BRANCH=None TEST=`make buildall -j` Change-Id: Id76fe93612fcd1ef924d7fa94479c45a52db046b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648566 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/stm32/usb_hid_keyboard: implement keyboard backlight controlWei-Ning Huang2017-09-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Implement keyboard backlight control through HID output report. One could enable CONFIG_USB_HID_KEYBOARD_BACKLIGHT to enable keyboard backlight support for a given board. Target board must implement the `void board_set_backlight(int brightness)` function in order correctly set backlight. BRANCH=none BUG=b:37971411,b:63364143 TEST=with follow up CLs 1. `make BOARD=hammer -j` 2. `echo 10 > /sys/class/leds/hammer\:\:kbd_backlight/brightness` console shows 'Keyboard backlight set to 10%' Change-Id: Ibeff510a0d996ddebf61b54ed6b500b02c35564a Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/586348 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec_features / coral: Allow disabling keyboard backlight featurePatrick Georgi2017-08-301-0/+6
| | | | | | | | | | | | | | | | | Allow reporting that keyboard backlight doesn't exist even when the code is compiled in. Useful if there are multiple device models that should share firmware. BUG=b:64705535 BRANCH=none TEST=none Change-Id: I9c1fc370aedf66ef856a571f73831095d27e3d39 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/633926 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-0/+3
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb_port_power_smart: Add CDP/SDP only option.Aseda Aboagye2017-08-281-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | For some boards, the control lines to the charging port controller are all tied to a power rail. In essence, this leaves the ILIM_SEL as the only signal able to be controlled, which means that we only support CDP/SDP. This commit adds a new CONFIG_* option which describes this. CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY Additionally, some cleanup is made to not always assume the number of smart power ports. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/634274 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* core/minute-ia: add __image_sizeli feng2017-08-241-0/+2
| | | | | | | | | | | | | | | | | For system using core/minute-ia, build will fail since __image_size is not defined. If later this variable is used, should adjust its value properly. BUG=none BRANCH=None TEST=Build passed for Soarka ISH which uses core/minute-ia. Change-Id: I8e179e0bac551a46d93ca10ba8b61b4ebade74fc Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/595151 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* g: Move chip pre-init to chip_pre_init()Randall Spangler2017-08-241-0/+8
| | | | | | | | | | | | | | | | | | | | Currently, chip/g uses jtag_pre_init() to do some chip pre-initialization that isn't actually related to JTAG. This has been harmless, but it's currently the only chip which actually does "JTAG" pre-init, and we'd like to get rid of that. So, move that functionality to a new optional chip_pre_init() function. BUG=chromium:747629 BRANCH=cr50 TEST=make buildall boot cr50 make all dis; confirm chip_pre_init() is called early in <main> Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/629876 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpc: Move board level TCPC init to happen in pd_task initScott Collyer2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the board level TCPC run as an init hook it will frequently lead to an EC reset when we are trying to recovery a disconnected battery, potentially even a reboot loop with the most unlucky timing. If we instead call it from the pd_task before tcpc_init is called then the board init hook can stall the pd_task init until the battery is out of disconnect mode, or giving up after 2 seconds in case the battery never seems to recover. This accomplishes two goals: ensure the PD chips are not reset until the battery is out of disconnect and delay start of the pd_task (and PD negotiation) until the battery is out of disconnect state. This change was done in the Eve FW branch. Pulling it into TOT so it can be used for other boards that have the same issue. https://chromium-review.googlesource.com/c/592716. The change to wait for the battery to be out of disconnect mode is in the board specific board_tcpc_init() function and so will be in subsequent board specific CLs. BUG=b:63957122 BRANCH=none TEST=manual Verify that 'make buildall' is successful. Change-Id: I14c3dbb89cdc05fa9231fbe9db2e1de19fa941b6 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627114 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* battery: Check physical battery presence before inhibiting powerScott Collyer2017-08-231-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to satisfy factory testing requirements we need to boot a bare board with just an AC adapter without requiring a power button. However we also don't want to always allow booting of the battery is present but cut-off (which will indicate BP_NO so we can't use the existing battery_is_present function) or has critically low level as it may not immediately boot. To accomplish this add a function that allows the board to specify a custom "hardware presence" for the battery that is separate from the battery presence check. This CL is taking a change done for Eve and pulling into TOT so it can be used for other projects that have the same requirements. https://chromium-review.googlesource.com/c/582544 BUG=b:63957122 BRANCH=none TEST=manual Change-Id: Ib1dc4f659adbf0eebd3dc8c3c61b39b8fa36cb4a Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/627113 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* coral: Add host command to fetch SKU IDPatrick Georgi2017-08-151-0/+3
| | | | | | | | | | | | | | BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: Ibf307c6e46152b4b09e94d8dca6d49ae863cb3ad Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/608370 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usb_mux: Add driver support for PS8743 chipDivya Sasidharan2017-08-111-0/+3
| | | | | | | | | | | | | | | | | Initial patch for supporting PS8743 USB Type-C Redriving Switch for USB Host / DisplayPort. BUG=b:64598680 BRANCH=glkrvp TEST=On GLKRVP, verify mux setting is correct with Apple dongle (VGA + USB) and Pluggable adapter. Change-Id: Ib45e328fc9ef6ccc410cef4550086be95ef17e8a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/506810 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* tpm: Add optional event loggingShawn Nematbakhsh2017-08-101-0/+3
| | | | | | | | | | | | | | | | | | Allow TPM to log events in a circular buffer through tpm_log_event(). Logs can be retrieved through a new vendor command VENDOR_CC_POP_LOG_ENTRY. BUG=b:63760920 TEST=On eve, store TPM logs through 'logentry' cr50 console command, verify logs are fetched correctly through 'trunks_send --pop_logentry'. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idbc405728c0ba68078447fb59717d6115830e3d8 Reviewed-on: https://chromium-review.googlesource.com/599352 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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