| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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This adds the "i2cspeed port [speed]" console command. If only the port
number is given, then the current port bus speed is reported. With 2
arguments, the port bus speed is changed. Valid speeds are 100, 400,
1000 and the unit is kHz.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: I7ca6b2c7a8fd9abe8e8ec77e4d1702529b297fe8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181504
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Many platforms have requirements to support more than one charge
source (eg. pirika). It can't be supported by just enabling two
different CONFIGS as that can lead to conflicts.
Eg.USD_PD_VBUS_DETECT_TCPC vs USB_PD_VBUS_DETECT_DISCHARGE.
This change provides a framework that supports two different charger
sources in the same build. Please see the CL for relevant logs.
BRANCH=None
BUG=b:194375840
TEST=make -j buildall
Signed-off-by: Parth Malkan <parthmalkan@google.com>
Change-Id: I309cc5930233983e615d90a4290fc749abf7aa2d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3088232
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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If set, this option will prevent saving General Purpose Registers
during panic. When software panic occurs, R4 and R5 will be saved,
because they contain additional information about panic.
This should be enabled on boards which are processing sensitive data
and panic could cause the leak.
BUG=b:193408648
BRANCH=none
TEST=Trigger panic using 'crash' command. After reboot use 'panicinfo'
to check what was saved. When CPU exception occurred registers
R0-R12 should be set to 0. In case of software panic, R4 and R5 can
contain panic reason and additional information.
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I06f9c4bb07f936f0822f70a05e19c8d99c68abfb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114645
Commit-Queue: Marcin Wojtas <mwojtas@google.com>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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EC version does not follow the the AP and OS version. This causes
confusion during development. This change augments the EC version output
to include the CrOS FWID when available. The CrOS FWID will be missing
when the CrOS EC is built outside of cros_sdk. When CrOS FWID is missing
'CROS_FWID_MISSING' will be used.
Zephyr/zmake support will be added later, CROS_FWID32 is set to
'CROS_FWID_MISSING' in zephyr builds until then.
BUG=b:188073399
TEST=version
21-05-20 16:43:18.627 Chip: Nuvoton NPCX993F A.00160101
21-05-20 16:43:18.631 Board: 1
21-05-20 16:43:18.631 RO: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.634 guybrush_13983.0.21_05_20
21-05-20 16:43:18.639 RW_A: * guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.641 * guybrush_13983.0.21_05_20
21-05-20 16:43:18.644 RW_B: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.644 guybrush_13983.0.21_05_20
21-05-20 16:43:18.647 Build: guybrush_v2.0.8770+f47439f75
21-05-20 16:43:18.651 guybrush_13983.0.21_05_20 2021-05-20
21-05-20 16:43:18.657 16:31:19 robbarnes@robbarnes0
ectool version
RO version: guybrush_v2.0.8770+f47439f75
RO cros fwid: guybrush_13983.0.21_05_20
RW version: guybrush_v2.0.8770+f47439f75
RW cros fwid: guybrush_13983.0.21_05_20
Firmware copy: RO
Build info: guybrush_v2.0.8770+f47439f75
guybrush_13983.0.21_05_20 2021-05-20 16:31:19 robbarnes@robbarnes0
Tool version: 1.1.9999-f47439f @robbarnes0
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ief0a0c6e9d35edc72ac2d4780ee203be41d7305f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2894145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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To avoid the I2C address contention between multiple I2C devices
on same bus, added code to support multiple I2C addresses for
it8801 I/O expander.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I6985973f9ae3ce91383d3b568a851169e6a308af
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3115426
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Li Feng <li1.feng@intel.com>
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MECC1.1 is defined for ADL+ platforms. To simplify the the BOM
stuffing options and also to remove dependency on H1 by MECC vendors,
H1 is added on RVP as AIC.
BUG=b:197659347
BRANCH=none
TEST=make buildall -j
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Change-Id: I5c3b4b2b2a116ec8dc5a7448c71a6b8654a78bba
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3114218
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Li Feng <li1.feng@intel.com>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Support dynamic PDO selection CONFIG_USB_PD_DPS.
This config controls the charging voltage and power according to the
input power and battery configuration.
DPS would continuously evaluate the system load and current charging
voltage, and decide a new one by below:
1. If the PDO can fulfill system desired power.
2. If the PDO is efficient for the battery configuration.
To detect if the system load cannot be fulfilled by the current PDO,
it checks:
1. if the input current closes to the PDO current limit.
2. if the input power closes to the PDO maximum power.
To detect if the system load can be fulfilled by a more efficient PDO,
it checks:
- if the voltage of a new PDO is closer to the battery voltage than the
current PDO, and the power is able fulfill the system load.
BUG=b:169532537
TEST=1. tested on asurada, the charging voltage is able to switch to
different PDOs under different system loads
2. tested that the DPS is able to switch charge port
(e.g. C1 12V -> C0 9V) based on the provided PDOs.
BRANCH=asurada
Change-Id: I7c7706b331dc0d4f8ac68569dc7ed852fc9308e3
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2897064
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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Add board_get_vbus_voltage to get vbus voltage by board, for
ADC_VBUS maybe is only for one typec port when the DUT supports
multiple typec.
BUG=b:196001868
BRANCH=none
TEST=show correct C1 vbus voltage on tomato
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: Ia567ec3bddf4f62a08c9902b4f0721783f2c07ff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3084403
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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This adds the CONFIG_ADC_CHANNELS_RUNTIME_CONFIG config option to allow
the adc_channels array to be tweaked at runtime.
BRANCH=none
BUG=b:183452273,b:181271666
TEST=buildall passes
Change-Id: I1241012b6e36c19baa7fe80853a6c6de4affeefa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3116990
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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Some platforms (e.g. servo_v4(p1)) are designed to act only as a
UFP considering superspeed terminations. Add config option to properly
manage usb superspeed muxer for such.
BUG=b:137887386,b:182419010
BRANCH=main
TEST=With servo_v4p1 connected to the DUT, unplug and replug CHG couple
of times in order to force PR_SWAP on DUT port. Each time verify
on the DUT console, whether all USB3 devices are visible. They
should be, since servo is trying to perform DR_SWAP when it acts
as a SRC.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0a7756f0bb2192795b7489334ed01d317d3e54ee
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3094246
Reviewed-by: Michał Barnaś <mb@semihalf.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
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Add a driver for writing Skin Temperature Tracking (STT) sensor
readings to the SB-RMI interface. STT readings are used to maximize
the SOc performance while keeping the skin temperature within
specification.
BUG=b:176994331
TEST=Build and run on guybrush
BRANCH=None
Change-Id: If655545158e7dc05946bc67686b1b0b40a40a713
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078050
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
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Add Side-Band Remote Management Interface driver. SB-RMI can be used to
manage power limits of the SOC. SB-RMI uses a soft mail box for
executing transactions.
BUG=b:176994331
TEST=Build
BRANCH=None
Change-Id: Ie185985e4c8d2c2d915b2ae2447709ddc16adda6
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3078049
Tested-by: Rob Barnes <robcb85@gmail.com>
Commit-Queue: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Fanli Zhou <fanliccc@gmail.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
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Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
by hardware, it will add several system clock cycles delay between CS
deassertion to CS assertion at the start of the next transaction, this
guarantees SPI back to back transactions, so 1ms delay can be removed
to optimze timing.
BUG=none
BRANCH=none
TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job
save 720ms as EC performs 180KB RW code's SHA256 hash computation
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Update SPI host interface config option for inclusive language.
BUG=b:163885307
BRANCH=none
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Add config option for the ps8805 to override the TCPCI Device
ID field based on the page 0 register 0x62 bit 7-4.
A2 chip: reg 0x62 bit7-4 = 0x0
A3 chip: reg 0x62 bit7-4 = 0xA
BUG=b:193099851
BRANCH=trogdor
TEST=ectool pdchipinfo can show overridden DID for both A2
and A3 chip on Lazor DUTs
Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com>
Change-Id: I99767c92a97c2fcefd3bbe03e3cd2b90de192ff3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3056225
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Delete the following configs which are no longer referenced by any
source files:
CONFIG_CMD_FLASH_LOG
CONFIG_CMD_GSV
CONFIG_CMD_GSV
CONFIG_CMD_LID_ANGLE
CONFIG_CMD_PMU
CONFIG_CMD_USBMUX
BUG=none
BRANCH=none
TEST=make buildall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ia304f0579d991a0fccc7bbc7ca7427fe0ed661a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061902
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This commit adds the config option, CONFIG_EEPROM_CBI_WP. It is to be
defined when the EC directly controls the CBI EEPROM WP signal. The EC
will set the WP according to the result of `system_is_locked()`. Note
that once the WP is set, the EC must be reset via EC_RST_ODL in order
for the WP to become unset. This is enabled by the accompanying
hardware.
BUG=b:181769483
BRANCH=None
TEST=`make -j buildall`
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: If490594ab4dd24af98119b01299215b997913b66
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046412
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This CL adds CONFIG_KEYBOARD_STRICT_DEBOUNCE. It makes the keyboard
debouncer register a key stroke after deounce is done.
This CL also adds a unit test.
BUG=b:193505909
BRANCH=Dedede
TEST=make run-kb_scan_strict
TEST=Blipper
Change-Id: Ia380657021035930afab5cafffa8cc2edd7ff475
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044405
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Currently keyboard_scan_config is defined by each board using
CONFIG_KEYBOARD_BOARD_CONFIG. This patch makes it defined as
__override hence removes CONFIG_KEYBOARD_BOARD_CONFIG.
BUG=None
BRANCH=None
TEST=buildall
Change-Id: I53a356741ba4d00e829ca59b74ee6dc704188728
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3044403
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
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For the boards where SKU_ID/BRD_ID comes from the strapping pins on EC,
this new config enables AP to ask EC for those hardware configs using
the CBI host command `EC_CMD_GET_CROS_BOARD_INFO`.
BRANCH=None
BUG=b:186264627
TEST=make buildall -j
TEST=Enabled CONFIG_CBI_GPIO for lazor and manually verified with
`ectool cbi get`.
Change-Id: I7ec9097bab96d2076d9d42db2d003460db000113
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3002452
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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Add Kconfig options for the InvenSense sensor drivers ICM426xx and
ICM42607. This also creates config option for CONFIG_ACCELGYRO_ICM42607
which was missed when the driver was first created (CL:2822268).
BUG=b:193195946
BRANCH=none
TEST=zmake testall
TEST=make buildall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I422071e749ee2e8ed3ac1997aa886ee78395d37e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3015867
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Change the name to disable CC passthrough on the SVY682x PPC from
CONFIG_SYV682X_NO_CC to CONFIG_USBC_PPC_SYV682X_NO_CC to match the
naming convention of other PPC options.
This also corrects a non-fatal error in the firmware-eq CQ about a new
ad-hoc EC config option.
BUG=b:193195946
BRANCH=none
TEST=zmake testall
TEST=make buildall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I66abcdddb7735f210fa25ed7c8b5760d8d626026
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3015866
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
Commit-Queue: Yuval Peress <peress@chromium.org>
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BMI323 is one of BMI3XX series accel sensor series.
Adding defines, driver from Bosch APIs based initial patches
submitted by Bosch team members in crrev/c/2966530.
BRANCH=none
BUG=b:178398789
TEST=Accel implementation tested on Guybrush
EC commands:
> accelinfo
> acceldata
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Change-Id: I9fa9d80aa25231261994adb4ef0ac5d71ac2f81a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984740
Reviewed-by: Diana Z <dzigterman@chromium.org>
Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com>
Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@google.com>
Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
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Refactor system_get_board_version() a bit so that we can remove
CONFIG_BOARD_VERSION_CUSTOM and CONFIG_BOARD_VERSION from config.h.
BRANCH=None
BUG=b:186264627
TEST=make buildall -j
TEST=zmake testall
Cq-Depend: chromium:3015243
Change-Id: Id5ab809493c297b7d330ea13dcd6934ec00042a6
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3004112
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The USB Type-C Altmode allows for protocols other than USB to be
transferred over a USB connection. Chromebooks use this functionality to
transfer DisplayPort on USB signals. This is achieved through USB-PD
handshake through SVDMs to discover, configure, and to enter or exit Alt
modes. When DisplayPort as an Alt Mode is enabled, allowable
functionalities are:
-- SS and high speed USB functionality and two-lane DP.
-- HS USB functionality and 4-lane DP.
Chromebooks honor Multifunction bit set in the DPStatus message sent by
a dock. However, for development purposes we would like to have control
to honor the MF bit or ignore it, there by achieving 2-lane DP vs 4-lane
DP functionality. 4-lane DP functionality is required to test higher
resolution monitors such as 4k60.
BUG=b:181365633
BRANCH=none
TEST=make BOARD, tested on G5 dock with kindred.
Signed-off-by: udaykiran <udaykiran@google.com>
Change-Id: Icc25f339a78d1423b094d2acf9d586721ec2df46
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939383
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Currently, the host's low battery shutdown SoC is 3% by default but
most boards are configured to 4%. This patch changes the default value
to 4% so that we require only minority boards to customize it.
BUG=b:191837893, b:189737806
BRANCH=None
TEST=Storo using battfake EC command.
Change-Id: I69ed5d8cc8c0d1e321d79c5eae26a9c21624a4ea
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2998509
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Currently, the host's low battery shutdown SoC is 2%. This is the
same as EC's low battery shutdown threshold. The EC waits for 30 secs
before it triggers the low battery shutdown and powerd reads the SoC
every 30 secs. Thus, in most cases powerd can shut down the system
gracefully but these delays can be configured differently and the
system may be too busy to process all shutdown tasks within 30 secs.
This patch increases the host's shutdown SoC to 3%. This will further
guarantee that powerd will be given enough time to do everything for
a proper shutdown. It also avoids deeply discharging the battery,
which is bad for the battery health.
BUG=b:191837893
BRANCH=None
TEST=Altas using battfake EC command.
Change-Id: I3ab23205b400a1a326a60b8f9501611c027183b2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2994747
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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BMA422 is one of BMA4XX series accel sensor series.
Adding defines, driver from Bosch APIs based initial patches
submitted by Bosch team members in crrev/c/2894333.
Reference code can be found on
https://github.com/BoschSensortec/BMA423-Sensor-API.
BRANCH=none
BUG=b:178400750
TEST=Accel implementation tested on Guybrush
EC commands:
> accelinfo
> acceldata
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
Change-Id: I8117283e54980379989fb01f68c29b7d6c501eca
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981465
Tested-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@google.com>
Commit-Queue: Rob Barnes <robbarnes@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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In line with OSHWA terminology.
BUG=b:181607131
TEST=make -j BOARD=hammer
BRANCH=none
Change-Id: I6d212e60d5aceb8497f00520b693006cc1af2d45
Signed-off-by: Harry Cutts <hcutts@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981123
Reviewed-by: caveh jalali <caveh@chromium.org>
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Currently, power-on battery SoC and shutdown battery SoC are
independently configured by each board. This patch will unify the
setting as follows:
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 2 (don't boot if soc < 2%)
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2 (shutdown if soc <= 2%)
BATTERY_LEVEL_SHUTDOWN = 3 (shutdown if soc < 3%)
CONFIG_BATTERY_EXPORT_DISPLAY_SOC = Y (removed)
CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON_WITH_AC = 1
This allows us to show the low battery alert whenever we can because
EC doesn't inhibit power-on even if it knows the host would
immediately shut down.
With CONFIG_BATTERY_EXPORT_DISPLAY_SOC, boards will start using the
CONFIG_BATT_HOST_SHUTDOWN_PERCENTAGE = 2% as the low battery
threshold (and the SoC will be agreed between the EC and Powerd).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON = 1 will keep the
same threshold. This is for avoiding degrading the UX by increasing
the power-on threshold (even though a question that 1% may not be
enough for soft sync to finish consistently remains to be answered).
Boards with CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON > 2 will have a
lower threshold but we think 2% is enough to finish the software sync.
A lower threshold also improves the UX by showing the low battery
alert in the situation where otherwise the system would leave the user
uninformed by not responding to a power button press.
BUG=b:191837893
BRANCH=None
TEST=buildall
Change-Id: If6ff733bc181f929561a3fffb8a84e760668ce37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981468
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Add KB800x driver. Add config options to Kconfig.
BUG=b:168930682
TEST=On Volteer, check USB4, TBT3, DPMF, DP, and USB3 functionality
BRANCH=none
Signed-off-by: Eric Herrmann <eherrmann@chromium.org>
Change-Id: Ic71b0d4236037522455a0561ba87fd9a874a4968
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2930581
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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Rename CONFIG_CROS_BOARD_INFO to CONFIG_CBI_EEPROM to make it clear
that the information comes from on-board EEPROM.
It sets up the groundwork for adding more options of CBI sources later.
BRANCH=None
BUG=b:186264627
TEST=make buildall -j
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I9a6feee0a8b35bbf29e445544243485507767ad8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2945792
Reviewed-by: Philip Chen <philipchen@chromium.org>
Commit-Queue: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
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Add PS8811 USB A retimer driver. Reusing USB mux structure even though
the retimer does not have a mux.
BUG=b:176987937
TEST=Build and run
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ie11a105f344e6acc1312cda517fdfe54ecb8c8ea
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2946307
Commit-Queue: Diana Z <dzigterman@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This patch enables the uart command, chargen by default. It generates
a series of alphanumeric chractecters, and is useful in testing UART
related modules with a stress workload.
This patch occupies 400 bytes or so in flash memory of RW image.
BUG=b:158477297
BRANCH=all
TEST=ran it on Atlas, Puff, and Volteer.
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Cq-Depend: chromium:1679710,chromium:1554198,chromium:2080933,chromium:2217112
Change-Id: I3c0407e7a4a6d3bb8d998e3e5618be5769192a8c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2951863
Reviewed-by: Craig Hesling <hesling@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The TCPCI interface can report OCP conditions, so enable the OCP
module automatically for all TCPCI TCPCs.
BRANCH=None
BUG=b:174334068
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I5af9c3fb18cecbea33bec65fad26387ea09a2e71
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2923238
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This replaces the CONFIG_SPI_MASTERR config option with
CONFIG_SPI_CONTROLLER.
BRANCH=none
BUG=b:181607131
TEST=make buildall passes;
"compare_build.sh -b all" shows no difference
Change-Id: I3c921085179294765baadf7074652978fe04a4ed
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932465
Reviewed-by: Craig Hesling <hesling@chromium.org>
Commit-Queue: Craig Hesling <hesling@chromium.org>
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This removes the CONFIG_SPI_MASTER_NO_CS_GPIOS config option as no code
actually uses it.
BRANCH=none
BUG=b:181607131
TEST=make buildall passes;
"compare_build.sh -b all" shows no difference
Change-Id: Iab1c7a79ee0ad973605c768f87ad8e19ed6ef4e7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932470
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This removes the CONFIG_SPI_MASTER_CONFIGURE_GPIOS config option as no
code actually uses it.
BRANCH=none
BUG=b:181607131
TEST=make buildall passes;
"compare_build.sh -b all" shows no difference
Change-Id: I4083a0ed1b106f9dcf0534625da5286dc0c34552
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932469
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BUG=none
BRANCH=none
TEST=buildall
Change-Id: Iebf0817c1b605d74348c9b20c01df74bd69468d2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2929338
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BUG=b:177391887
TEST=none
BRANCH=main
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I8f017e21b74c1e27ca7f257b76b0ef74fd0343f2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2639734
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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IT83XX and IT8XXX2 drivers are not compiled if the flag
CONFIG_USB_PD_TCPM_ITE_ON_CHIP is not defined. So instead
of the first two flags, the ITE_ON_CHIP is used in expression
that undefines CONFIG_USB_PD_TCPC_VCONN
BUG=b:182500469
BRANCH=none
TEST=Use util/compare_build.sh to verify if firmware wasn't changed
with this commit. Boards tested:
"icarus kracko haboki cozmo drawcia lantis wheelie volteer delbin"
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Change-Id: If26e855186c56c9cf118e727b8bafe5e3d1ea734
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919908
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Drive CCD_MODE_ODL from EC when EC sees DTS connected to CCD port.
This will fix some cases where the Cr50 is not able to detect that
a CCD debug cable has been connected.
BUG=b:175056327
TEST=Connect/disconnect SuzyQ cable, see assert/unassert in log
Check gpioget on CR50 and ec, confirm CCD_MODE_ODL is correct
Connect/disconnect charger, do not see assert/unassert in log
Repeat with ServoV4
BRANCH=None
Change-Id: I411e75a47f2e1303ddbd9caa63a9417630c99b46
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659282
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Initial driver for the TDP142, a DisplayPort redriver chip. The initial
implementation simply provides access to the chip's control selection
since it must be explicitly enabled after the chip powers on.
BRANCH=None
BUG=b:187856682
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I4afe4b0453ef49154b766166f608bd3d0fb8848f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2915823
Reviewed-by: Rob Barnes <robbarnes@google.com>
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On Asurada, some Sandisk stickers would enter fault status
(down-train to USB2 or not detected) if Vbus is applied before xhci
initialization. The defauilt S3 hooks does not work in this case.
This CL adds a config option to allow board to control the timing to
enable/disable port power.
BUG=b:187149602
TEST=manually test with CL:2909972
BRANCH=asurada
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I2ac4689182f22f4fa81d34bff8b5797e5fe222d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914482
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
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Commands that are send peridically or in high number are not
reported on the console through CONFIG_SUPPRESSED_HOST_COMMANDS
variable.
Use the same set of commands throughout to avoid misses like
newer command EC_CMD_GET_UPTIME_INFO.
BUG=none
BRANCH=none
TEST=buildall
Signed-off-by: Gwendal Grignou <gwendal@google.com>
Change-Id: I0041576538a8cc659c262118b1503777b9ea8578
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2851452
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Craig Hesling <hesling@chromium.org>
Tested-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
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Create new configs (Chromium EC namespace and Zephyr namespace) for
SC7280. In this state, SC7280 power sequence has no difference
from SC7180.
BRANCH=None
BUG=b:187980397
TEST=Built all the Chromium EC images and Zephyr EC images.
TEST=Modify a board to use the new CONFIG.
Change-Id: I178b8ffa5d79d3828baf222ac77906ab2262cf76
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893069
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This reverts commit 0e5fa530e2f1eba6e16188be65ac39974a151a17.
After commit 97e22d467 it is no longer needed to reload
watchdog during hash calculation.
BUG=b:182499153
BRANCH=none
TEST=Flash EC and verify that hash calculation is correctly
done without rebooting by watchdog. Reading watchdog value
shows that there is enough remaining time.
Change-Id: Ia7bb6452a6ac42cda88d8b5e1203876cd0465b31
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2897239
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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Allowing EC buttons and switches to be signaled via MKBP protocol, using
CONFIG_MKBP_INPUT_DEVICES. Default behaviour is unchanged.
BUG=b:170966461
BRANCH=main,firmware-dedede-13606.B,firmware-volteer-13672.B-main
TEST=None
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Cq-Depend: chromium:2824044
Change-Id: Ib96f98ecb3717a8ee8963be69fb7d7eb72e6d132
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2796382
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Cypress CCGXXF PD has built-in I/O Expander, added driver to enable
GPIO functionality.
BUG=none
BRANCH=none
TEST=Tested on ADLRVP, ioexget & ioexset works as expected
Change-Id: I8503178703ad166ac77e96d1990133c88169d23a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2853143
Tested-by: Svyatoslav Paliy <svpaliy@gmail.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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