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* I/O Expander: Add CCG6XX driverVijay Hiremath2021-05-051-0/+3
| | | | | | | | | | | | | | | Cypress CCGXXF PD has built-in I/O Expander, added driver to enable GPIO functionality. BUG=none BRANCH=none TEST=Tested on ADLRVP, ioexget & ioexset works as expected Change-Id: I8503178703ad166ac77e96d1990133c88169d23a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2853143 Tested-by: Svyatoslav Paliy <svpaliy@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Port80: allow to accept 4-byte Port80 codeJun Lin2021-05-041-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | The original Port80 implementation assumes that the Port80 code is only 2-byte wide and is less than 0x100. In the recent AMD chipset (CEZANNE), AP will send a 4-byte Port80 code via a single PUT_IOWR_SHORT eSPI transaction in PSP. This CL adds a config option to allow the Port80 to print 4-byte code when the config is defined. BRANCH=none BUG=b:184872297 TEST=build the image with "#define CONFIG_PORT80_4_BYTE"; connect npcx9_evb to the eSPI host emulator; the host sends a PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code "0xEEE20400"; the EC console shows: Port 80 writes: eee20400 <--new Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I3b93d9fc41e1875bb628a15c58231005e9555cfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2858296 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* usb-ep: Add config option to define VIDScott Collyer2021-05-021-0/+5
| | | | | | | | | | | | | | | | | This value was previously hardcoded to Google's VID. However, some products with USB-EP support may require a different VID to correctly support fwupd. BUG=b:181920029 BRANCH=quiche TEST=verified that fwupd works on baklava Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I23c36507a90428ab46cd5efde7d79581207bde74 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848424 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* Battery: Add command to export display SoCDaisuke Nojiri2021-05-011-0/+38
| | | | | | | | | | | | | | | | | | | | | | Currently, CrOS EC passes the battery remaining capacity (mAh) and the full capacity (mAh) through ACPI to the AP so that the host can calculate the battery SoC. The host further manipulates the SoC to get the display SoC, which is used to determine user visible behaviors. To get consistent behaviors in all power states, this change enables the EC to send the display SoC to the host via EC_CMD_DISPLAY_SOC command. The Powerd's part is I5bd1371f2569d21d55df1b50a3d709b98bbf0325. BUG=b:174433637, b:181506409, b:80270446, b:109954565 BRANCH=dedede, trogdor, nami, hatch TEST=Storo, CoachZ Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Idc6992625d992a73be141987d02ed220508d3b74 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2853142 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cherry: Add ANX3443 mux/retimer driverParker Lin2021-04-291-0/+6
| | | | | | | | | | | | | | | Add basic support for ANX3443. Datasheets available in bug. BUG=b:181282482 BRANCH=None TEST=Build Signed-off-by: Parker Lin <parkerlin@google.com> Change-Id: Id779547704408b9563f803885cd755ae96d38ef7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2728001 Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSJeremy Bettis2021-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac1d81e1430dbfbfba1376a23ab19dfa845d7ef. The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=chromium:1202406,b:180980668 TEST=make -j16 runhosttests buildall && zmake testall && \ /mnt/host/source/src/platform/ec/zephyr/firmware_builder.py --metrics \ /tmp/tmplt8ty8ci test ; echo $? BRANCH=none Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I5b5e58b30d936b5232e049827f458d9a2ed06340 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855320 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "config: rename CONFIG_FLASH to CONFIG_FLASH_CROS"stabilize-13935.B-mainJack Rosenthal2021-04-241-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a. Reason for revert: responsible for CQ failures (crbug.com/1202406) BUG=chromium:1202406 BRANCH=none TEST=CQ Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Original change's description: > config: rename CONFIG_FLASH to CONFIG_FLASH_CROS > > The config name collides with the same config name in zephyr. > > Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to > CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig > side. > > BUG=b:180980668 > TEST=make buildall > BRANCH=none > > Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 > Signed-off-by: Eric Yilun Lin <yllin@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 > Tested-by: Eric Yilun Lin <yllin@google.com> > Reviewed-by: Keith Short <keithshort@chromium.org> > Commit-Queue: Keith Short <keithshort@chromium.org> Bug: b:180980668 Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274 Auto-Submit: Jack Rosenthal <jrosenth@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-231-3/+3
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* LED On/Off: Remove power LED configDiana Z2021-04-221-6/+0
| | | | | | | | | | | | | | | | | | | | | | Move the LED on/off module towards using a more flexible LED support approach. Define a weak power LED table and setter for boards to override when needed. Note that during run-time these functions will not get called since led_auto_control_is_enabled() will return false for nonexistent LEDs. This consumes an average of 165 additional bytes of flash space on boards which do not use a power LED. BRANCH=None BUG=b:185508707 TEST=make -j buildall, load on guybrush (battery LED only) and confirm no errors are seen. Load on Boten (both LEDs) and confirm behavior appears normal Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Iaa1e22a7f5d8be39eb8792ee13d358087d7f7482 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2832691 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC/PPC: Add code for Cypress EZ-PD CCG6DF, CCG6SFVijay Hiremath2021-04-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | CCG6DF and CCG6SF are dual-port and single-port USB Type-C controllers respectively. These can act as either PD or TCPC based on the Phy firmware flashed on the internal flash. These chips use standard TCPCI driver. BUG=none BRANCH=none TEST=With the initial Phy F/W able to test following on ADL RVP 1. Single port Type-C is validated 2. Dead battery boot 3. Source & Sink path 4. SOP* 5. USB, DP, TBT 6. 100K, 400K, 1MHz I2C Change-Id: I1b1a2f759139ac1c7aab42d851b8a7866664e28a Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2551653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Cleanup: Enable PPC from PD or Power MUXVijay Hiremath2021-04-201-0/+10
| | | | | | | | | | | | | | | Some PD chips have integrated SRC FET and control the SRC/SINK FET from GPIOs hence cleaned up the code to enable Power Path Control from either from PD or from Power MUX. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I77f96b681fd2e5fca35bce425e4bd5ec87d5ccfd Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2828980 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver: bmi: fix use of I2C_PORT_ACCELYuval Peress2021-04-161-0/+19
| | | | | | | | | | | | | | | | | | | | | The BMI driver is currently using I2C_PORT_ACCEL incorrectly as a CONFIG_ value. Update the use cases to a new config option that selects between SPI and I2C communication specifically for the chip. To avoid a lot of device.h changes, the value of the config value is automatically inferred if not explicitly set. BRANCH=none BUG=b:185392974, b:146065507 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I6196cc595dc61877ab2b8ed5416bebee51276927 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2829010 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* driver: icm: fix use of I2C_PORT_ACCELYuval Peress2021-04-161-0/+19
| | | | | | | | | | | | | | | | | | | | | The ICM driver is currently using I2C_PORT_ACCEL incorrectly as a CONFIG_ value. Update the use cases to a new config option that selects between SPI and I2C communication specifically for the chip. To avoid a lot of device.h changes, the value of the config value is automatically inferred if not explicitly set. BRANCH=none BUG=b:185392974, b:146065507 TEST=zmake testall TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I8b1a507a76031c2bb1aaf4ca7b14b92252a941f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2826920 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* mp2964: Add PMIC driverCaveh Jalali2021-04-161-0/+3
| | | | | | | | | | | | | | | | | This adds a driver for the mp2964 IMVP9.1 PMIC. This driver enables programming control registers within the PMIC. BRANCH=none BUG=b:185424011 TEST=buildall passes. functional testing was done with the follow-on patch. Change-Id: I9b2d89007b5f6933ceeb9a1bcd3bbefb819888a3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2827950 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* zephyr: Adjust watchdog warning timer value and delay timeMulin Chao2021-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjusts the watchdog warning timer value and its delay time definitions to meet original chromium ec behavior. The system handles the warning event at CONFIG_AUX_TIMER_PERIOD_MS & issues the watchdog reset event at CONFIG_WATCHDOG_PERIOD_MS. Zephyr NPCX watchdog provides a config WDT_NPCX_DELAY_CYCLES for watchdog timeout delay. Set the zephyr timeout to CONFIG_AUX_TIMER_PERIOD_MS as warning time. So the NPCX watchdog hardware issue reset event at CONFIG_AUX_TIMER_PERIOD_MS + WDT_NPCX_DELAY_CYCLES. BUG=b:184683548 BRANCH=none TEST=Build & boot ec on volteer. TEST= `waitms 1000` warning doesn't issue & ec doesn't reboot `waitms 1200` warning issue & ec doesn't reboot `waitms 1500` warning issue & ec doesn't reboot `waitms 1700` warning issue & ec reboot Cq-Depend: chromium:2813911 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Ibee9c18cd9d2bae6d34ee9366755dec99687c3d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2814728 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* cbi: fix documentTing Shen2021-04-141-2/+2
| | | | | | | | | | | | | | | | The macro name does not match the implementation in common/cbi.c. BUG=none TEST=make BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I3c51d1e6030a6a9d2d058bc5bfb2b12c8d78a0af Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2823470 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* watchdog: Add config for the leading time of warning timerWealian Liao2021-04-141-3/+7
| | | | | | | | | | | | | | | | Originally, the config CONFIG_AUX_TIMER_PERIOD_MS uses hard-coded for the leading time of the warning timer. Add config for the leading time. BUG=none BRANCH=none TEST=ALLOW_CONFIG=1 make buildall Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: If4b15ffc12dbb11d3782c875eaa6c35b51105901 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2821109 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* ec: Filter non-FIXED PDOs in servo_v4{p1}Jeremy Bettis2021-04-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | Add a new config CONFIG_USB_PD_ONLY_FIXED_PDOS. If that config is enabled, ignore non-FIXED PDOs in both the console command `ada_srccaps` and also when selecting the preferred PDO for a voltage. Enable CONFIG_USB_PD_ONLY_FIXED_PDOS for servo_v4 and servo_v4p1, since they don't expose non-fixed PDO in their srccaps. Without this change, there is a risk that the "best" PDO for a given voltage will be non-FIXED and then that voltage just won't be supported at all. BRANCH=none BUG=b:178484932 TEST=added Change-Id: I0d1187ca372120c7fe21d627e1b82b59f6334add Signed-off-by: Jeremy Bettis <jbettis@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2809353 Tested-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Power: Add configurable S5 timeoutDiana Z2021-04-101-0/+1
| | | | | | | | | | | | | | | | Similar to the hibdelay command, allow the time we spend in S5 to be configurable for the sake of power testing in this state. It may be set to 0 for an immediate drop, or -1 to stay in S5 forever. BRANCH=None BUG=b:184941436 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If2f8cf91ba982822e2e33cb17f84f38c40907d2e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2818526 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* bq25720: Add VSYS_TH2 tuning supportCaveh Jalali2021-04-061-0/+10
| | | | | | | | | | | | | | | | | | This adds support for tuning the bq25720 VSYS_TH2 threshold so that a custom threshold voltage can be specified. The default 3.2v for 1S batteries and 5.9v for 2S (or more) batteries may need to be adjusted to improve system stability. When VSYS droops to this threshold, PROCHOT is asserted to reduce system power demand. BRANCH=none BUG=b:183474163 TEST=with rest of patch stack, booted brya to the OS without a battery Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I7f52a369371eb93860b14ad8438b790af231c450 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2798979 Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* ppc/syv682x: support C versionEric Yilun Lin2021-04-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | C version won't block I2C accessing to CONTROL4(to on/off Vconn) reg when smart discahrge enabled. This allows us to re-enable the smart discahrge on boards using SYV682C. This CL support the feature by adding: 1. CONFIG_USBC_PPC_SYV682C 2. CONFIG_USBC_PPC_SYV682X_SMART_DISCHARGE also, hayato uses different SYV682 versions across revisions, add a overridable function syv682x_board_is_syv682c() for handling board revision issue. BUG=b:160548079 b:176876036 TEST=Hayato meets tVconnOff, and tVbusDischarge BRANCH=asurada Change-Id: I89b57b8c20907249d5d97140289fb0570bd58b46 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738506 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* common/battery: Provide function to lower input voltagePatryk Duda2021-03-291-0/+6
| | | | | | | | | | | | | | This patch introduces generic version of function that sets voltage limit when chipset is off and battery is fully charged. BUG=b:182546058 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ib7606c8d1ab3fe1dc650a3abcef9ebc207335ab5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2773218 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "ps8815: delete CONFIG_USB_PD_TCPM_PS8815_FORCE_DID"Zhuohao Lee2021-03-251-0/+6
| | | | | | | | | | | | | | | | | This reverts commit e2761c8be4571adcfc425a9187290872ffa9d02d. In order to support the old TCPC chip which bcd revision is smaller than 0x7, we need to bring back the CONFIG_USB_PD_TCPM_PS8815_FORCE_DID and force the TCPC firmware be updated in the factory line. BUG=b:177251013, b:159289062, b:182018599, b:178978970 BRANCH=firmware-volteer-13672.B TEST=the old TCPC chip can update its firmware. Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: I66d12aee569137cc7823a186e3251ca8b187e767 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784327 Reviewed-by: Keith Short <keithshort@chromium.org>
* bq25710: Consolidate NARROW_VDC definitionCaveh Jalali2021-03-231-1/+2
| | | | | | | | | | | | | | | | | This consolidates the selection of CONFIG_CHARGER_NARROW_VDC to config.h for the bq25710 and bq25720 charger chips. The driver requires NARROW_VDC to be enabled, so move this setting to config.h similar to other chargers. BRANCH=none BUG=b:173575131 TEST=buildall passes Change-Id: I6c1768aff5d581544c4b7182f32ec45851a3a243 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2780831 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* charger: Update BQ25720 configsCaveh Jalali2021-03-221-5/+1
| | | | | | | | | | | | | | | | | This updates how we select between the BQ25720 and BQ25710 charger chips. The BQ25720 charger chip can now be enabled without enabling the BQ25710 charger chip. Both chips are still supported by the same driver and the choice of BQ25720 vs. BQ25710 remains a compile time configuration. BRANCH=none BUG=b:180980490 TEST=buildall passes Change-Id: If632af0b68d8cf73e5c2436a05b1641e4467d8f8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2774701 Reviewed-by: Keith Short <keithshort@chromium.org>
* npcx: eSPI: add a config to reset SLP_Sx VW when eSPI_RST assertsJun Lin2021-03-171-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | It was observed that in byra, when the "apshutdown" console command is executed, the power state of EC is messed up. This was caused by the SLP_Sx virtual wire is not updated due to the ungraceful global reset. This CL adds a config option to let npcx EC reset SLP_Sx VW when eSPI_RST is asserted. Note: don't enable this config if the platform implements deep Sx entry (e.g. KBL) for the reason per Intel eSPI spec. (scenario 3 in Table 7): These pins retain state (0 or 1) until PCH/SoC exits Deep-Sx and PMC sends a VW message to the EC with the new states for these pins. BRANCH=none BUG=b:179977907 TEST=pass "make buildall" TEST=With the config defined, see the SLP_S4 virtual wire reset when eSPI_RST is asserted. Signed-off-by: Furquan Shaikh <furquan@google.com> Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I413b3d211537295b32c49b6e4a1797e48a26ec5f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2766428 Tested-by: CH Lin <chlin56@nuvoton.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* vboot_hash: Add watchdog reloadsKeith Short2021-03-091-0/+25
| | | | | | | | | | | | | | | | | | | | When neither CONFIG_SHA256_HW_ACCELERATE nor CONFIG_SHA256_UNROLLED are enabled, calculating the hash can trip the watchdog. Add watchdog reloads at a rate of 1/2 the watchdog period when both these options are disabled. BUG=b:182208446 BRANCH=none TEST=zmake testall TEST=Boot zephyr-ec on Volteer, powerdown AP and observe watchdog timeouts are fixed Signed-off-by: Keith Short <keithshort@chromium.org> Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I6170b457c91f3247adf9ad47cd7e93b128a1d13b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2744356 Reviewed-by: Yuval Peress <peress@chromium.org>
* dedede/metaknight: delay thermal sensor read in the first timeYu-An Chen2021-03-081-0/+9
| | | | | | | | | | | | | | | | Add CONFIG_TEMP_SENSOR_FIRST_READ_DELAY_MS to adjustment delay time of thermal sensor first read. Add 500 ms delay of thermal sensor first read in metaknight. BUG=b:181202521 BRANCH=dedede TEST=DUT do [ec reset|boot from G3] 20 time pass Signed-off-by: yu-an.chen@quanta.corp-partner.google.com Change-Id: I12f5411c8ac3866d7a52807c4eface9e6bdfd5a7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738505 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* delbin: Setting charger switching frequency to 724kHz.Michael5 Chen12021-03-081-0/+7
| | | | | | | | | | | | | | | Setting charger switching frequency to 724kHz. BUG=b:180779740 BRANCH=volteer TEST=manual 1. Check charger register 0x3C 2. Check waveform Signed-off-by: Michael5 Chen1 <michael5_chen1@pegatron.corp-partner.google.com> Change-Id: I97512742dfc778c22615f8385fbe1fecf5ff2d7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719786 Reviewed-by: Keith Short <keithshort@chromium.org>
* cbi: Add CONFIG_BYPASS_CBI_EEPROM_WP_CHECKZhuohao Lee2021-03-041-0/+12
| | | | | | | | | | | | | | | | | | | | | | | In some projects, we modify the cbi eeprom write protection via the hardware design. So, the gpio pin GPIO_WP is decoupled from the cbi eeprom write protection status. With this change, we can update the cbi eeprom data on the fly for the dogfood device during the development. In order to bypass the cbi eeprom write protection check, we add a CONFIG_BYPASS_CBI_EEPROM_WP_CHECK to skip the gpio value. Since this modification is only for the developing device, we add the CONFIG_SYSTEM_UNLOCKED check to avoid someone mis-use this config. BUG=b:169034911 BRANCH=volteer TEST=`ectool cbi set` is working in drobit/copano Change-Id: I3f35159883f75965b1009c45c25ac2cd1c6e7c0d Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2719724 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* charger: Add support for the TI BQ25720Caveh Jalali2021-03-041-0/+6
| | | | | | | | | | | | | | | | This adds support for the BQ25720 charger using the BQ25710 driver. The only significant difference between the two chips is that the VBUS voltage register encoding has changed. The scale changed from 64mV to 96mV and there is no DC offset. BRANCH=none BUG=b:180980490 TEST=buildall passes Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I9ab6e066a4dec93a0ede0c22ff21b240a5021cbf Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717805 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Octopus: Re-enable VCONN sourcing from TCPCEric Herrmann2021-03-031-1/+5
| | | | | | | | | | | | | | | | | | | The SYV682 shouldn't have VCONN supplied to its host side CC pins, but on Octopus these pins aren't used and the TCPC must provide VCONN. Since this is a non-standard configuration, make an exception for these Octopus boards by defining a new SYV682 flag to indicate that it does not pass through CC. BUG=b:180973460 TEST=make buildall BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I043b6025abbeeaaf9e261d2721da3aed5483e177 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721234 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Marco Chen <marcochen@chromium.org>
* TCPMv2: PD Timers - Base Timer frameworkDenis Brockus2021-03-011-0/+1
| | | | | | | | | | | | | | | | | Add in the basic framework. There are optimizations for using less timers but want to get the basics working before I invest more time in this. BUG=b:178029034 BRANCH=none TEST=make-runtests Signed-off-by: Denis Brockus <dbrockus@google.com> Change-Id: Icf93e3074b02cc3e0f7ee62e026b0d8ba10c7709 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2707804 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org> Tested-by: Denis Brockus <dbrockus@chromium.org>
* TCPMv1/v2: Add config option to disable TCPC VCONNEric Herrmann2021-02-261-1/+15
| | | | | | | | | | | | | | | | | | | | | Currently we always source VCONN from the TCPC, and also the PPC if present. However the SYV682 can't handle 5V on its host-side CC pins, so we shouldn't source VCONN in that case. For those TCPCs which will trigger OVP if VCONN isn't enabled, this will not happen with the SYV682, since it isolates VCONN from the TCPC CC signals. BUG=b:180973460 TEST=On delbin, make sure the host-side CC pins are <3.3V when sourcing VCONN BRANCH=None Signed-off-by: Eric Herrmann <eherrmann@chromium.org> Change-Id: I8929a44fc23f93c44559229f1b0d024fd7fbc7db Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721086 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* tca64xxa: Add new ioexpander driver for TI TCA64xxA modulesMichał Barnaś2021-02-231-0/+3
| | | | | | | | | | | | | | | | | | | Add TI TCA64xxA (TCA6416A, TCA6424A) series driver that conforms to ioexpander_drv interface. Driver supports 16- and 24-bits versions and is configured by flags field in ioex_config (TCA64XXA_FLAG_VER_TCA6416A, TCA64XXA_FLAG_VER_TCA6424A). BUG=b:168385201 BRANCH=main TEST=Add 'CONFIG_IO_EXPANDER_TCA64XXA' to any board.h Execute make to any board, ioexpander/tca64xxa.c should be visible in compiled files list Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: I5ca27df3802d900c9967684403f29c33abd96f18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2700296 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ioexpander: Add support to read levels on whole IOEX portMichał Barnaś2021-02-231-0/+7
| | | | | | | | | | | | | | | | In some cases it's needed to read many pins on the same IOEX port. To improve performance and remove redundant calls, it will be easier to read levels on whole IOEX port. To enable this functionality, CONFIG_IO_EXPANDER_SUPPORT_GET_PORT must be defined and driver must support it. BUG=b:168385201 BRANCH=main Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: I472385a4ef4f5db23ce92d017194f8c737b7607e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2700295 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* guybrush: Add ANX7451 mux/retimer driverRob Barnes2021-02-231-0/+6
| | | | | | | | | | | | | | Add basic support for ANX7451. Datasheets available in bug. Support for tuning can be added later if needed. BUG=b:179065240 BRANCH=None TEST=Build Change-Id: Ifafdec4412b73b0fd3f7de2131a8617bbfde6426 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2699667 Reviewed-by: Diana Z <dzigterman@chromium.org>
* zephyr: add watchdogWealian Liao2021-02-221-0/+9
| | | | | | | | | | | | | | | | | | | In npcx7 series, the Timer and Watchdog module (TWD) generates the clocks and interrupts used for timing periodic functions in the system. It also provides watchdog reset signal generation in response to a failure detection. This CL enables the watchdog functionality in zephyr system. BUG=b:176523207, b:177604307 BRANCH=None. TEST=add stall function to check the system can reset by the watchdog Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Iee0312dd6132ce76e622178b3a666aa415bc735a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659135 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Commit-Queue: Simon Glass <sjg@chromium.org>
* TCPMv2: Clarify how to opt out of DPM source-out policyDiana Z2021-02-191-0/+3
| | | | | | | | | | | | | | | | Add clarification for how a board can turn off the 3.0 A source-out policy. This can be either because it doesn't support sourcing that much current, or because it is implementing a board-specific PDO selection. BRANCH=None BUG=b:141690755 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I5a9d23c115470063a84170cf222845086d86955b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2701891 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: remove unused CONFIG_SAVE_VBOOT_HASHYuval Peress2021-02-181-6/+0
| | | | | | | | | | | | | | | | No boards or baseboards enable this config option. Removing this simplifies verifying efs2/vboot on the zephyr project. BRANCH=none BUG=b:164421798 TEST=make buildall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I10e81f9d3b3829dd8a07992ee805f37d88d9ea84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2705178 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* nb7v904m : add config to disable LPMYongBeum.Ha2021-02-171-0/+3
| | | | | | | | | | | | | | Add config to disable LPM BUG=b:179624712 BRANCH=none TEST=make -j BOARD=sasuke Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Change-Id: I6ae0d08709fe0799843b6e225b480ffa617dfe84 Signed-off-by: YongBeum.Ha <ybha@samsung.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2684075 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPMv2: Add common hpd->dp_atten converterScott Collyer2021-02-171-2/+5
| | | | | | | | | | | | | | | | | | | | | | | This CL adds a new file for UFP_D ports. The inclusion of this file is controlled via a new config option CONFIG_USB_PD_ALT_MODE_UFP. Note that this is not intended to be used with TCPMv1 UFP_D legacy devices. The initial version of this file includes the hpd to usb pd DP_ATTENTION message converter. The implementation follows the spec in terms of both states and hpd event queueing rules. BUG=b:175660576 BRANCH=None TEST=Tested further down the CL stack. But verified that this CL fixes the issue where too many hpd_irq messages are sent with gingerbread which was causing a port part reset for chromebook ports. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5c7f4a3d226eb7b33553c90f04c69c3d80bd8672 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598028 Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* include/panic: Add config to remove RV32I from panic data structurePatryk Duda2021-02-161-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | RISC-V core specific panic data is bigger than Cortex-M core specific panic data. Including this into union in a panic_data structure causes the whole to grow by 28 bytes. In many boards EC RO is still obtaining pointer to beginning of panic data by subtracting its panic data structure size from the end of RAM. When EC RW saves panic data it will be corrupted by EC RO. Moreover, during next boot EC RW won't be able to find jump data (see b/165773837 for more details). This config allows boards to not include RV32I panic data if their EC RO doesn't include it to keep panic data structure in sync. Default behaviour is that RV32I core specific panic data is included. BUG=b:165773837 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I01efd63ce67b08c6991d4d52a40f0818b0d70a62 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673416 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* zephyr: clean up CONFIG_ZEPHYR thingJack Rosenthal2021-02-111-0/+4
| | | | | | | | | | | | | | | | Move CONFIG_ZEPHYR from Kconfig to CMakeLists.txt since it really makes no sense in Kconfig (should always be set to y). This allows us to pluck it out of config_chip.h as well. BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Iafb20c4b373e2c344e7c856d454080b7f008f1d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2690987 Reviewed-by: Simon Glass <sjg@chromium.org>
* power: Rename stoney.c to amd_x86.cRob Barnes2021-02-101-0/+2
| | | | | | | | | | | | | | | | | Rename stoney.c to amd_x86.c since it covers all currently supported AMD chipsets. Add CHIPSET_CEZANNE to guard any differences between STONEY and CEZANNE chipsets. BUG=b:175234270 BRANCH=None TEST=Build for zork and guybrush Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I96f82127729d64970b8d46fc8ef4ddba6489dd8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2683923 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* usb_mux: ps8822: Initial version of driverScott Collyer2021-02-091-0/+3
| | | | | | | | | | | | | | | | | | | | This CL adds the driver for the PS8822 usb demux. Currently, the driver only supports the expected usb mux driver methods. It is expected that any EQ setting functions would be board specific, though more register definitions would need to be added to the .h file. BUG=b:175660576 BRANCH=None TEST=Connect on host port and then read back mode register to confirm that it's been set as expected. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ic425ffe41f4653cee7f5500b081d7b5f6ad1a3df Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2247361 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* alderlake: Implement chipset supportCaveh Jalali2021-02-071-2/+9
| | | | | | | | | | | | | | | | | | | | | | | This provides support for the Intel Alder Lake SoC in conjunction with the Silergy SLG4BD44540 power sequencer. A new config option (CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) is provided to enable this setup. This is intended to be used by brya and its variants. Other Alder Lake boards that use the Ice Lake style power sequencing are not affected by this new config option. BRANCH=none BUG=b:173575131,b:177275055,b:177277633 TEST=buildall passes Change-Id: I74c36f06fc8ad26c163093753140a5ca242d75c7 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675309 Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* config.h: fix comment of CONFIG_BOARD_RESET_AFTER_POWER_ONEric Yilun Lin2021-02-051-1/+1
| | | | | | | | | | | | | | The config is supported by ITE chips as well. BUG=none TEST=none BRANCH=none Change-Id: Ib5e4ea4bee8bdc63bb451e4cc8a1133c35bf3dfc Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675327 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* retimer: support retimer firmware updateli feng2021-02-051-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To support AP to update firmware during boot up, one byte EC RAM is allocated for AP <-> EC communication. AP queries PD port/requests EC to perform operations via EC_CMD_ACPI_WRITE; and fetches result from EC via EC_CMD_ACPI_READ. The flow is: 1. AP queries EC PD ports which port supports retimer firmware update. 2. AP queries current MUX. 3. a) If no device attached, AP requests EC to suspend PD task of the port. Then AP requests EC to set MUX to USB mode, Safe mode, TBT mode. After entering TBT mode, the OS can either enumerate the retimers or do firmware update on the enumerated retimers. Once done, AP requests EC to disconnect MUX and resume PD task. 3. b) If device attached, AP moves on as usual. Retimer firmware update is not performed. BUG=b:162528867 BRANCH=none TEST=Tested NDA case on Voxel board, together with coreboot and kernel changes. Coreboot changes are merged. Kernel patches list is: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2670719 After power up, host scans retimers, in sysfs localhost ~ # ls /sys/bus/thunderbolt/devices/ 0-0 0-0:1.1 0-0:3.1 domain0 On PD port 1, manually update retimer firmware. Copy firmware to nvm_non_active1/nvmem, then authenticate it. Host starts flow to update firmware. After it's done, PD port 1 resumes. Hotplug DP dongle/TBT device, devices should function fully. TEST=Tested DA cases on Voxel board, together with coreboot and kernel changes. USB4/TBT devices function as usual. Signed-off-by: li feng <li1.feng@intel.com> Change-Id: Ie976e75f892d5caf48a948598a058a4f42e07eb3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2594492 Reviewed-by: Keith Short <keithshort@chromium.org>
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