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* cleanup: Don't shadow NULL with an enumBill Richardson2015-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | For the few platforms without gpio.inc, use this enum gpio_signal { GPIO_COUNT }; instead of this enum gpio_signal { NULL }; The only reason this worked at all is that the headers are included in a particular order. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I81533f3614d0b4c7389f9edd42cd8ac018581f46 Reviewed-on: https://chromium-review.googlesource.com/278120 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* gpio: Refactor IRQ handler pointer out of gpio_listAseda Aboagye2015-04-101-7/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the gpio_info struct, we had a irq_handler pointer defined even though a majority of the GPIOs did not have irq handlers associated. By removing the irq_handler pointer out of the struct, we can save some space with some targets saving more than others. (For example, ~260 bytes for samus_pd). This change also brings about a new define: GPIO_INT(name, port, pin, flags, signal) And the existing GPIO macro has had the signal parameter removed since they were just NULL. GPIO(name, port, pin, flags) In each of the gpio.inc files, all the GPIOs with irq handlers must be defined at the top of the file. This is because their enum values from gpio_signal are used as the index to the gpio_irq_handlers table. BUG=chromium:471331 BRANCH=none TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power button, keyboard, charging, all still working. TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build fail. TEST=make -j BOARD=peppy tests TEST=make -j BOARD=auron tests TEST=make -j BOARD=link tests Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263973 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cr50: Separate ARM core GPIOs from pinmux configurationBill Richardson2015-02-201-13/+1
| | | | | | | | | | | | | | | | | | | | This separates the configuration of the ARM core GPIOs from the routing of internal peripherals to external pins. Both are still described in the gpio.inc file, but are less dependent on each other. BUG=chrome-os-partner:33818 BRANCH=none TEST=manual Before this CL, running "sysjump rw" or trying to use more than 8 GPIOs caused hangs and reboots. Now it doesn't. Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251015 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: bitmasks should be unsigned valuesBill Richardson2015-02-201-1/+1
| | | | | | | | | | | | | | | Change the struct gpio_info to use uint32_t for the mask field, instead of signed integer. BUG=none BRANCH=none TEST=make buildall Change-Id: I8cc7e3d06a00bd3c890522a896e36e1eb18a862e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251013 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add support for shared interrupts.Myles Watson2014-12-191-0/+1
| | | | | | | | | | | | | | | | | | The nRF51 chips from Nordic have shared interrupts. Having a flag for that makes it easier to implement. BUG=chrome-os-partner:34477 BRANCH=none TEST=make buildall -j Signed-off-by: Myles Watson <mylesgw@chromium.org> Change-Id: I89c78ace99085c359db8515667eaffb5617f0162 Reviewed-on: https://chromium-review.googlesource.com/234390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Myles Watson <mylesgw@chromium.org> Tested-by: Myles Watson <mylesgw@chromium.org>
* g: implement GPIOsVincent Palatin2014-12-101-1/+13
| | | | | | | | | | | | | | | | | | Add a driver for the GPIO controller. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33816 TEST=press the push buttons on the board and see the console text message and the LEDs lighting up. Change-Id: Idb408fe1c341beb8a97f2047ba6740e0d40cedf5 Reviewed-on: https://chromium-review.googlesource.com/233307 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Reduce code duplication in STM32 gpio driverAnton Staaf2014-07-171-0/+16
| | | | | | | | | | | | | | | | | | | | Previously the F0 and L variants had almost identical driver files and the F variant shared about half of its driver. This refactor moves the shared code into gpio.c and gpio-f0-l.c, the latter is for code shared between the F0 and L variants. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=none TEST=make buildall -j Followed by manual testing of interrupt on change and UART functionality on STM32F0 based discovery board. Change-Id: I920babd1861548272af2857c8bd3e4f9dac4985c Reviewed-on: https://chromium-review.googlesource.com/207986 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* gpio: Replace duplication in gpio declarations with X-macro fileAnton Staaf2014-06-261-3/+0
| | | | | | | | | | | | | | | | | | | | | Previously each board.h and board.c contained an enum and an array for gpio definitons that had to be manually kept in sync, with no compiler assistance other than that their lengths matched. This change adds a single gpio.inc file that declares all gpio's that a board uses and is used as an X-macro include file to generate both the gpio_signal enum and the gpio_list array. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=none TEST=make buildall -j Change-Id: If9c9feca968619a59ff9f20701359bcb9374e4da Reviewed-on: https://chromium-review.googlesource.com/205354 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* gpio: Make GPIO_INT_BOTH explicitly RISING|FALLINGRandall Spangler2013-11-231-4/+3
| | | | | | | | | | | | | | | | | | | | | | | For historical reasons on LM4, we defined GPIO_INT_F_BOTH separately from GPIO_INT_F_RISING and GPIO_INT_F_FALLING. This means that the code has weird checks like BOTH || (RISING && FALLING), which have propagated in error-prone ways across the other chips. Instead, explcitly define BOTH to be RISING|FALLING. Ideally, we would have called it GPIO_INT_EDGE to match GPIO_INT_LEVEL, but changing that now would be a big find-replace. Which might still be a good idea, but that is best done in its own CL. BUG=chrome-os-partner:24204 BRANCH=none TEST=build and boot pit, spring, and link; that covers STM32F, STM32L, and LM4. Change-Id: I23ba05a3f41bb14b09af61dc52a178f710f5c1bb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177643 Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-5/+1
| | | | | | | | | | | | | | | | | | | | This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Use low speed clock in deep sleep.Alec Berg2013-10-211-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Changed the low power idle task to use the low speed clock in deep sleep. The low power idle task is currently only enabled for Peppy, Slippy, and Falco. This change decreases power consumption when the AP is not running. Note that the low speed clock is slow enough that the JTAG cannot be used and the EC console UART cannot be used. To work around that, this commit detects when the JTAG is in use and when the EC console is in use, and will not use the low speed clock if either is in use. The JTAG in use never clears after being set and the console in use clears after a fixed timeout period. BUG=None BRANCH=None TEST=Passes all unit tests. Tested that the EC console works when in deep sleep. Tested that it is possible to run flash_ec when in deep sleep and using the low speed clock. Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lm4: Modified clock gating to allow easy expansion to low power.Alec Berg2013-10-101-0/+2
| | | | | | | | | | | | | | | | | | | | | Created a new function to enable or disable clocks to various peripherals. This new function makes it easy to specify if you want the clock enabled in run mode, sleep mode, and/or deep sleep mode. Added infrastructure to specify which GPIOs should interrupt the EC from deep sleep. BUG=none BRANCH=none TEST=Passes all unit tests. Ran on a peppy and verified that the clock gate control registers in run mode (LM4_RCGC regs) were the same before and after this change. Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Support multi-bit mask in STM32L's GPIO functionsVic Yang2013-09-111-1/+1
| | | | | | | | | | | | | | | | | | The definition of GPIO interface allows passing in multi-bit mask, and this is what's done by gpio_config_module(). Fix STM32L's function so that it doesn't accidentally set incorrect GPIO register values. BUG=chrome-os-partner:22605 TEST=On Kirby, do 'led r 0' and check the value of 0x40020800 is 0x01540000. BRANCH=None Change-Id: I9a1c8074aab7345485a590ecf138bf99d0742997 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168739 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org>
* Fix a bug that GPIO cannot be set as input on stm32lVic Yang2013-09-041-22/+26
| | | | | | | | | | | | | | | | | GPIO_INPUT is defined as 0, and any GPIO flag cannot be examined against GPIO_INPUT. Change GPIO_INPUT to non-zero value to avoid this. BUG=chrome-os-partner:22275 TEST=On Kirby, set a GPIO to output and pull it low, and then set it back to input. Check it can be pull high externally. TEST=Build all boards. TEST=Boot link and spring. BRANCH=None (unless this bug hits some other boards.) Change-Id: I84b9936c24af538ac59c36129fda27ca879bf9d1 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167190 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up configuring GPIO alternate functionsRandall Spangler2013-08-071-20/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO alternate functions used to be configured throughout the code, which made it hard to tell which ones you needed to configure yourself in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being configured as alternate functions even if they weren't used on a given board. With this change, every board has a table in board.c which lists ALL GPIOs which have alternate functions. This is now the only place where alternate functions are configured. Each module then calls gpio_init_module() to set up its GPIOs. This also fixes a bug where gpio_set_flags() ignored most of the flags passed to it (only direction and level were actually used). On stm32f, gpio_set_alternate() does not exist, and pins are configured via direct register writes from board.c. Rather than attempt to change that in the same CL, I've stubbed out gpio_set_alternate() for stm32f, and will fix the register writes in a follow-up CL. BUG=chrome-os-partner:21618 BRANCH=peppy (fixes I2C1 being initialized even though those pins are used for other things) TEST=boot link, falco, pit, spring Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64400
* Add build-time checks on board-specific array sizes.Bill Richardson2013-07-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've been declaring a bunch of statically-sized arrays: extern struct foo_t foo[FOO_COUNT]; And then initializing them like so: struct foo_t foo[FOO_COUNT] = { /* blah */ }; That only catches cases where we initialize with too many entries. It doesn't catch cases where we haven't initialized enough. This change tests for both cases like so: extern struct foo_t foo[]; struct foo_t foo[] = { /* blah */ }; BUILD_ASSERT(ARRAY_SIZE(foo) == FOO_COUNT); The affected arrays are: adc_channels[ADC_CH_COUNT] gpio_list[GPIO_COUNT] temp_sensors[TEMP_SENSOR_COUNT] x86_signal_list[X86_SIGNAL_COUNT] i2c_ports[I2C_PORTS_USED] BUG=chrome-os-partner:18343 BRANCH=falco,peppy TEST=build all platforms All platforms should still build, all tests should still pass. Change-Id: Ibb16dc3201f32df7cdc875648e89ba4ffb09f733 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63833 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOWBill Richardson2013-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | GPIO_HI_Z was a bit misleading (it's high impedance by default, but it's actually an output not an input), but when we added GPIO_HI_Z_OPEN to mean "open-drain output, pulled low by default", it got too confusing. This renames those macros to: #define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) #define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) BUG=chrome-os-partner:18788 BRANCH=none TEST=none No functional change, just renaming some macros. If it compiles, it should be unchanged in behavior. Change-Id: Ic84d7be8531f2b240a8eca4f6cfe5291ebd2d5ef Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58596 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* haswell: fix RCIN# GPIO settingAaron Durbin2013-05-221-0/+1
| | | | | | | | | | | | | | | | | | The gpio pin used for RCIN# should be configured as open drain as the rail is pulled up by a non-EC rail. Driving it high would leak power. The current GPIO_HI_Z macro uses GPIO_HIGH as the default state. However, it has been found that this actually drives the pin to ground. It is still unclear how Link works or doesn't. BUG=chrome-os-partner:19355 BRANCH=none TEST=manual: boot on slippy without RCIN# causing reset and the 'apreset warm' EC command works as expected. Change-Id: I71425075f8d77b3d7e576a59fc24f823790e2655 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56269 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Refactor gpio_set_level() and gpio_pre_init()Randall Spangler2013-04-151-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | gpio_set_level() now allows setting the pin level if GPIO_LOW or GPIO_HIGH is specified. Previously, stm32 platforms did this even though the definition of gpio_set_level() said it wouldn't work. Fixed gpio_set_level() not setting level after warm reboot on stm32 because it was checking the GPIO_DEFAULT flag in the wrong place. Fixed LM4 still mucking with alternate function settings and levels even if GPIO_DEFAULT was specified. And checked gpio_list[] and all of the calls to gpio_set_flags() to make sure everything still behaves the same way it did before (or better, in the case of actual bugs). BUG=chrome-os-partner:18718 BRANCH=none TEST=build all platforms; boot spring and link Change-Id: I4b84815f76060252df235ff9a37da52c54a8eac5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48058 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Allow GPIO alternate function 0Randall Spangler2013-04-111-1/+1
| | | | | | | | | | | | | | | | | gpio_set_alternate_function() used 0 to mean "normal GPIO function". But on chips like STM32L, alternate function 0 is actually a function on some pins. So change "normal GPIO function" to -1. Also add support for this on STM32L. BUG=chrome-os-partner:18343 BRANCH=none TEST=build and boot link and daisy Change-Id: I9cdd9ad91a315b616e373a0dc9a50545cf9d20fa Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47903 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move asserting host keyboard interrupt signal to keyboard_scanRandall Spangler2013-03-201-0/+4
| | | | | | | | | | | | | | | | The implementation is identical on all stm32 hardware, so remove all the duplicate copies from board.c files. mccrosskey doesn't have GPIO_EC_INT so stub it out like we do on bds. No functional change, just moving code. BUG=none BRANCH=none TEST=build mccrosskey,daisy,snow,spring Change-Id: I7d4378650d7b4c640c15180c41459a41620f5bd3 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/45920
* Clean up GPIO module.Randall Spangler2012-10-301-3/+3
| | | | | | | | | | | | No functional changes, just code cleanup. BUG=chrome-os-partner:15579 BRANCH=none TEST=gpioget returns reasonable values Change-Id: I4301ccc68ade775f78f4ccd84710d2cd4bc25252 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36800
* Clean up GPIO moduleRandall Spangler2012-10-251-22/+52
| | | | | | | | | | | | | Just code cleanup; no functional changes BUG=chrome-os-partner:15579 BRANCH=none TEST=build code; boot link; gpioget still works Change-Id: If0770c1a5ce0d5c51ba528fbe2944a73fafa949b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36556 Reviewed-by: Simon Glass <sjg@chromium.org>
* Allow GPIOs to be set up laterSimon Glass2012-08-271-1/+1
| | | | | | | | | | | | | | | | | | | | At present GPIOs must be staticly defined in a table. This is efficient but inflexible, and requires error-prone and correponding #ifdefs both in the board's gpio.h and gpio.c files. Create a GPIO_UNSET option for GPIOs. This allows them to be assigned an enum value, but have the actual use under program control. BUG=chrome-os-partner:13064 BRANCH=snow,link TEST=manual build and boot on snow with later changes. See the AC power GPIO does not change when un/plugging power. Change-Id: Iab58275923d7d6cfce62c890b5db9b6758279a4c Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31302 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* gpio: Add fast access to GPIO levelSimon Glass2012-07-021-0/+12
| | | | | | | | | | | | | | | | | | The current gpio_get_level() is pretty slow because it looks things up each time. Add a new function to find out the register address and mask to use to check the value for a particular GPIO. Time-critical code can then use this to check a GPIO. BUG=chrome-os-partner:10146 TEST=manual: build and boot on snow; Power on the board, hold power button for 10s and see that it powers off Power control still works, thus GPIOs are functional Change-Id: Ifc6c56f5cb811e0243e7712725a51948eabd42ab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26175
* Add gpio_set_flags() and system_get_board_version()Randall Spangler2012-05-081-4/+8
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=version; board version should be 0 on proto1 and 1 on EVT Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
* Move gpio list into gpio.h header fileSimon Glass2012-05-081-0/+3
| | | | | | | | | | | | This is referenced by various files, so should be in the gpio.h header. BUG=none TEST=manual: build and boot on daisy, see that USB download still works build on all platforms Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4 Signed-off-by: Simon Glass <sjg@chromium.org>
* Add gpio_get_name() to return the name of a signalSimon Glass2012-05-031-0/+8
| | | | | | | | | | | | Add this to the GPIO API. It seems that the implementation is copied in LM4 and STM32 so I have reluctantly done the same with this new function. BUG=chrome-os-partner:9424 TEST=build and boot on Daisy Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd Signed-off-by: Simon Glass <sjg@chromium.org>
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-191-3/+0
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* add more explicit GPIO typesDavid Hendricks2012-04-131-0/+5
| | | | | | | | | | | | This patch adds explicit handling of open-drain outputs and adds Hi-Z for high-impedence state (floating) outputs. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=compile tested Change-Id: I1a0c2e8366f6a82cd9cd7e83e57122944f2bdc2d
* GPIO interrupts are disabled by defaultRandall Spangler2012-01-131-0/+8
| | | | | | | | | | | | | Added gpio_enable_interrupt() to enable them. This ensures that a module which handles GPIO interrupts doesn't get them until it's ready. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7456 TEST=toggle power button while rebooting; without this fix it triggers a hard fault. Change-Id: I35d926053963a70dd9246ce46a4913603b2b2489
* Move board-specific GPIO lists to board-specific filesRandall Spangler2012-01-121-67/+34
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I47fd5d709a9575e41fdcdf21a7440ebbb762cef5
* Configure all GPIOsRandall Spangler2012-01-121-0/+2
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I0a9be4c689fb72507edcf202073b23c58902d7de
* Tidy GPIO configuration and board-specific configs for modules.Randall Spangler2012-01-121-3/+6
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: Ia06707db78ea9a9313b49a93e8732a7fc9fcc191
* Add constants for all GPIOs.Randall Spangler2012-01-111-8/+62
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I3b77cbbb7f0cc12a4daae7ababd603b5d7af32d1
* Add GPIO get/set commandsRandall Spangler2012-01-111-3/+5
| | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=from debug console, gpioget --> prints current level. Run a few times to see DEBUG_LED value toggle. gpioset debug_led 1 --> turns debug LED on. Run repeatedly to override the idle task toggling it off. Change-Id: I7c64044228697e052a9c20eb052d37a1f640f6e7
* Split power button code into its own fileRandall Spangler2012-01-101-6/+7
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7499 TEST=press and release power button; should see debug messages Change-Id: I8909ae4643afc98753edb690771618ad43135e3e
* Clean up labels and TODOsRandall Spangler2012-01-101-2/+2
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: I8d6e99b3e2b60d32ea3719468590b055e692a67e
* Initial sources import 1/3Randall Spangler2011-12-071-0/+41
source files mainly done by Randall. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
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