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* apply INT_AP_L extension on I2CS interfaceNamyoon Woo2020-05-291-0/+7
| | | | | | | | | | | | | | | | This patch applies INT_AP_L extension on I2CS. It uses GPIO_MONITOR_I2CS_SDA to detect a transaction start during INT_AP_L assertion and to deassert INT_AP_L. BUG=b:148691139 TEST=None Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iedd59b488dfdfaaf71dd71eda6437f1a9402d3c4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2150517 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Reland "smart_battery: add smbus error checking support"Ting Shen2019-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a reland of daccb3adea9394116d7ab2c807e4a360cb5a93a1 Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: http://crrev.com/c/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> BUG=b:138415463 TEST=in addition to the TESTs above, verified this CL boots on hatch(npcx chips), and reef_it8320(it83xx chips). BRANCH=master Change-Id: I67975eee677cfd6e383742d48103662372cac061 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1913940 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Revert "smart_battery: add smbus error checking support"Caveh Jalali2019-10-301-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit daccb3adea9394116d7ab2c807e4a360cb5a93a1. Reason for revert: <INSERT REASONING HERE> broke USB-C charging. all we get now is: 2019-10-30 01:26:15 New chg p0[49.441303 CL: p0 s2 i500 v5000] 2019-10-30 01:26:16 C0 st5 2019-10-30 01:26:16 C0 Req [1] 5000mV 3000mA 2019-10-30 01:26:16 New chg p0[50.305144 CL: p0 s0 i500 v5000] 2019-10-30 01:26:16 C0 HARD RST RX 2019-10-30 01:26:16 C0 st4 2019-10-30 01:26:16 New chg p0[50.354280 CL: p0 s2 i500 v5000] 2019-10-30 01:26:17 C0 st5 2019-10-30 01:26:17 C0 Req [1] 5000mV 3000mA ... Original change's description: > smart_battery: add smbus error checking support > > Jacuzzi/Kodama has a unstable software controlled i2c bus, its data > transmission may be interrupted by other higher priority tasks and > causes device timeout. > > If timeout happens when ec is reading data, it has no knowledge about > what's happening on slave, and keep receiving bad data (0xFF's) until > end. The standard i2c/smbus error handling mechanism can not handle this > case, so we need the error checking feature from smbus 1.1 to ensure our > received data is correct. > > This CL adds the error checking (PEC) functions to i2c and smart battery > module. > > BUG=b:138415463 > TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, > no failure after 100k read/writes. > test code at CL:1865054 > BRANCH=master > > Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 > Signed-off-by: Ting Shen <phoenixshen@google.com> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827138 > Reviewed-by: Denis Brockus <dbrockus@chromium.org> > Tested-by: Ting Shen <phoenixshen@chromium.org> > Commit-Queue: Ting Shen <phoenixshen@chromium.org> Bug: b:138415463 Change-Id: Ibd8a512dd6d43cca95628f698e7a66a695b7fc59 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889435 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* smart_battery: add smbus error checking supportTing Shen2019-10-281-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Jacuzzi/Kodama has a unstable software controlled i2c bus, its data transmission may be interrupted by other higher priority tasks and causes device timeout. If timeout happens when ec is reading data, it has no knowledge about what's happening on slave, and keep receiving bad data (0xFF's) until end. The standard i2c/smbus error handling mechanism can not handle this case, so we need the error checking feature from smbus 1.1 to ensure our received data is correct. This CL adds the error checking (PEC) functions to i2c and smart battery module. BUG=b:138415463 TEST=On kodama, enable CONFIG_CMD_I2C_STRESS_TEST, no failure after 100k read/writes. test code at CL:1865054 BRANCH=master Change-Id: Ibb9ad3aa03d7690a08f59c617c2cd9c1b9cb0ff3 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827138 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* main: Initialize I2C pretty earlyAlexandru M Stan2019-10-241-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (like the keyboard, CBI) need I2C access pretty early. Until now I2C would get initialized pretty late in a hook, which was far too late for some stuff. As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init() function will be called at board boot. Some chips (cr50, host tests) needed a stub i2c_init in order to compile cleanly. BUG=b/138384267 TEST=EFS doesn't happen significantly later than it used to TEST=Recovery keys now work with I2C keyboard on jacuzzi TEST=make buildall TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety of ECs: * ampton (ite EC, x86 AP) * bobba (npcx EC, x86 AP) * jacuzzi (stm32f0 EC, ARM AP) * cheza (npcx EC, ARM AP) BRANCH=master Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* util/comm-i2c: upgrade to host command protocol v3Harry Cutts2019-09-261-0/+6
| | | | | | | | | | | | | | | | | | | | | We can remove the v2 code, as any boards still using it have reached end-of-life, with the exception of Samus's PD, which we only communicate with via the Kernel driver, as far as I can tell. (I verified that an `ectool` built with this change can still be used to communicate with the Samus PD.) BRANCH=none BUG=none TEST=Checked various commands (hello, version, inventory...) with `--interface=i2c` and `comm_init_i2c` modified to hard-code the I2C bus to use (as the board I tested with is not yet in sysfs). The test board is using a MAX32660, so https://crrev.com/c/1716928 was patched in for testing. Change-Id: I1e014c6f747ce29d9bf1541be51c519af98e7f45 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1803977 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: don't scan i2c addresses less than 0x08Jett Rink2019-07-251-0/+10
| | | | | | | | | | | | | | | None of the existing i2c addresses in the EC code base are less than 0x08 and those addresses are reserved by the i2c and SMBus specification. BRANCH=none BUG=b:138156666 TEST=i2c bus scan with a smart battery doesn't "misbehave" any more and other devices can be detected properly. Change-Id: I561b082c4c7e3df7caaa33b6ef6ad467dabbd5a5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715326 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-58/+48
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-49/+113
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* common: add i2c tracing functionalityJack Rosenthal2019-07-171-0/+15
| | | | | | | | | | | | | | | | | | | crbug.com/982442 requests a way for developers to enable tracing of i2c commands when debugging. This adds a new debug feature, the i2ctrace command, which provides that. The command is guarded by CONFIG_I2C_DEBUG. BUG=chromium:982442 BRANCH=none TEST=enabled CONFIG_I2C_DEBUG on arcada_ish, made sure that command functioned as it says on the tin Change-Id: I9c762271237cbf131e5ef7c0f605c89af4f209fd Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699347 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* TCPC: Make tcpc_config handle other bus typesDaisuke Nojiri2019-06-101-0/+6
| | | | | | | | | | | | | | | | | | | | | Currently, tcpc_config assumes TCPCs are on I2C bus. ITE's EC has an embedded TCPC. This patch adds bus_type field to struct tcpc_config_t so that a TCPC location on other type of bus can be specified. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: Ieac733011700b351e6323f46070dcf46d9e1154b Reviewed-on: https://chromium-review.googlesource.com/1640305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* common/i2c_master: Add a subcommand to protect all TCPC portsKarthikeyan Ramasubramanian2019-05-301-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | Currently the I2C tunnels of all TCPC ports are protected implicitly when the system jump is disabled. Depthcharge issues that command after the EC jumps to RW and before the TCPC firmware update is applied. This leads to failure while updating the TCPC firmware and hence a reboot loop. Fix this behavior by adding a sub-command to protect all the I2C tunnels so that depthcharge can issue that command after both EC SW Sync and TCPC Firmware update are done. BUG=b:129545729 BRANCH=None TEST=make -j buildall; Boot to ChromeOS. Force a TCPC FW update and ensure that the reboot loop does not happen. Change-Id: I5dd2314cf82dcfff520dc32ce3ced232326ab3d5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1605260 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-4/+4
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: fix style violations introduced by ab40ba67cVadim Bendebury2019-03-071-7/+6
| | | | | | | | | | | | | | | The patch in question was uploaded with numerous coding style violations. Fixing them to avoid warnings when cherry-picking the patch into different branches. BRANCH=cr50, cr50-mp BUG=none TEST=repo upload does not complain any more. Change-Id: I01e2786a509819ed914370b0ab276bb58e420365 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1500993 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c: Support 16-bit address register read & writeTony Zou2019-02-191-0/+29
| | | | | | | | | | | | | | | | | | | | | | | wireless receiver charger IDT P9221 I2C reg addr is 16bit. command i2cxfer r/r16/w/w16 port offset [value] When offset is 4 digit (e.g. 0x00ab), it reads/writes 16 bit offset registers. Otherwise, it reads/writes 8-bit offset registers. BRANCH=none BUG=b:123504007 TEST=1:) Build flapjack EC and flash to DUT , EC can read/write P9221 register. 2:) Build kukui EC , build pass. TEST=buildall Change-Id: If0df532f5ca136bf1312a1857b13e8455e897943 Reviewed-on: https://chromium-review.googlesource.com/1445133 Commit-Ready: Tony Zou <zoutao@huaqin.corp-partner.google.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* i2c_master: Protect TCPC I2C tunnels as part of EC_REBOOT_DISABLE_JUMPKarthikeyan Ramasubramanian2019-01-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | Currently EC keeps the I2C tunnels open enabling depthcharge to perform firmware update on those ports. Once the firmware update is done, depthcharge triggers a command to protect the I2C tunnels. But not all TCPC ports are registered for firmware update in depthcharge. This causes some I2C tunnels to be left unprotected. Update EC to protect all the TCPC I2C tunnels when depthcharge invokes EC_REBOOT_DISABLE_JUMP command. This usually happens when the EC software sync is complete and the control jumps to OS. Also protect the TCPC I2C tunnels only when the WP is enabled. BUG=b:119130829 BRANCH=octopus TEST=make -j buildall && Boot to ChromeOS and ensure that the TCPC I2C tunnels are protected. Change-Id: Ice681038bbf725b3aa44b13ff71724937c6045e9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/1390944 Commit-Ready: Karthikeyan Ramasubramanian <kramasub@chromium.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* i2c: Don't try to unwedge unpowered busses.Aseda Aboagye2018-08-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | If an i2c bus is known to be unpowered, we should not spend time trying to unwedge it. It's futile, so stop trying. This commit adds a config option, CONFIG_I2C_BUS_MAY_BE_UNPOWERED which can be defined by a board if a bus may be unpowered during runtime. BUG=b:111683988 BRANCH=nocturne TEST=Verify that unwedge attempts are skipped if the bus is deemed unpowered. Change-Id: Ice12b3957121be476ef0173a86f239f183010b47 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1182877 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* i2c: Split i2c_xfer into locked/unlocked versions.Jonathan Brandmeyer2018-08-161-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename i2c_xfer to i2c_xfer_unlocked. Audit all users of i2c_xfer to see if they can use simple locking semantics or require their own locking. Since locked accesses are only safe for I2C_XFER_SINGLE transactions, remove the flags parameter from i2c_xfer. This also makes the audit a bit easier. Some remaining applications hold the bus locked across several transactions that would otherwise be atomic, and a few others implement complex I2C transactions in multiple commands. Add a (nondeterministic) verification on the I2C port locking correctness. This will catch all statically incorrect locking patterns, although dynamically incorrect locking patterns may not be caught. Related: Revise the i2c_port_active_count to be a bitmap of the active ports instead of a count of the active ports. The EC's mutex does not provide an is_locked() primitive, and we would prefer not to have one. - board/glados: Custom locking for battery reset - board/mchpevb1: Custom locking for battery reset - board/oak: Custom locking for battery reset - board/samus: Custom locking for lightbar reset - board/sweetberry: simple locking - board/servo_micro: Custom locking for funky i2c transfers - capsense: simple locking - host_command_master: multi-command transactions - lb_common: manual locking to support samus power sequence - smbus: multi-command transactions - usb_i2c: simple locking - driver/tcpm/fusb302: simple locking and multi-command transactions - driver/tcpm/tcpi: Forward _unlocked and implicitly locked interface to fusb302 - driver/touchpad_elan: simple locking BUG=chromium:871851 BRANCH=none TEST=buildall; very careful audit TEST=grunt clamshell and Coral clamshell, test boot, battery charging, PD communication, and TCPC port low-power mode. Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: Ieabf22bcab42780bdb994fca3ced5d8c62519d56 Reviewed-on: https://chromium-review.googlesource.com/1169913 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* i2c master: Add block read/write commands.Jonathan Brandmeyer2018-08-091-1/+18
| | | | | | | | | | | | | | | | | | | These commands are used by several modules that manage their own block read/write protocols today. This is the first of a series that refactors several modules to use the I2C driver functions instead of their own. BUG=chromium:871851 BRANCH=none TEST=make -j buildall; USB-PD and motionsense testing on Grunt convertible, which exercises several users of the new interface. Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Change-Id: I08475a72031e5fbf49dc344d5b4858622f0d5e93 Reviewed-on: https://chromium-review.googlesource.com/1167957 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* i2c: Add option for calling board-specific functions before and after every ↵Furquan Shaikh2018-03-201-0/+23
| | | | | | | | | | | | | | | | | | | | | | i2c transaction This change adds a new config option CONFIG_I2C_XFER_CALLBACK that makes i2c_xfer callback into board-provided functions before the start and after the end of every I2C transaction. This can be used by boards to implement any I2C device-specific quirks e.g. requiring minimum bus-free time between every I2C transaction when the slave device cannot actually do clock stretching. BUG=b:73147310 BRANCH=None TEST=make -j buildall Change-Id: I452de4f22a81ffd97ca4944e1b940a3537637df9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/956934 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: support large reading in i2c_xfer()Chun-Ta Lin2017-12-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There might be more than one place that will use very similar codes in CL:542716 (usb_i2c.c). To avoid unnecessary duplication of code, we fold the logic into i2c_xfer(). With config enabled (illustrated in this CL), i2c_xfer() will support large reading. An early prototype of potential usage is demostrated in CL:781300. BRANCH=none TEST=For CONFIG_I2C_XFER_LARGE_READ: With proprietary software on slave: ./touchpad_updater -d TEST=For usb_i2c regression: ./touchpad_updater still works (where the reading is less than 255) TEST=For generic EC regression test: On poppy EC (With CONFIG_I2C_XFER_LARGE_READ defined) (1) Prevent override of update /usr/share/vboot/bin/set_gbb_flags.sh 0xa39 (2) flashrom -p ec -w ec_binary_contains_this_CL.bin (3) ectool reboot_ec cold (4) "ectool version" verified that both RO/RW/Build info is local. (5) Test with a type-C DP dongle on DELL 2408WFP. (6) Plug-in type-C charger and external display still works. (7) Confirmed that battery is charging. (7) "ectool battery" reads same data (for fixed field) as before. (8) "ectool usbpdpower", confirmed charger info displayed as before. (9) "ectool usbpd 0", confirmed content exactly as before. (10) For Gyro. Verify under Arc++ Using App: com.gamma.bubblelevel, works the same as before. (11) For Accelerometers. Verify under Arc++ Using App: com.innoventions.sensorkinetics, small movement's charts looks as expected. TEST=For generic EC regression test: On Caroline EC (Without CONFIG_I2C_XFER_LARGE_READ defined). Details in CL:810332 BUG=b:63993891 Change-Id: I654868945fa535e784800177d54eb2d9803f5249 Signed-off-by: Chun-Ta Lin <itspeter@google.com> Reviewed-on: https://chromium-review.googlesource.com/788479 Commit-Ready: Chun-ta Lin <itspeter@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Lock out i2c passthru except for desired portsShawn Nematbakhsh2016-12-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | Lock out all non-essential i2c passthru ports when system is protected. BUG=chrome-os-partner:58859 BRANCH=gru TEST='ectool i2cxfer 0 0 0 0' on locked system, verify that "ACCESS DENIED" is returned. Change-Id: If4119bbb319aa491d0e79a9ed80c94daa7950c2f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403543 Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> (cherry picked from commit d29fdb5484b994937c6586a50dd2818028f15f3f) Reviewed-on: https://chromium-review.googlesource.com/415493 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* g: Added I2CM driver to support chip_i2c_xfer()Scott2016-10-111-0/+6
| | | | | | | | | | | | | | | | | | | | | Added i2cm driver to support chip_i2c-xfer function. The initial use case is for INA chips on the Reef/Gru platforms. Note that this CL does not include any board specific changes and therefore does not include an I2C port definition or required pinmux settings. BRANCH=none BUG=chrome-os-partner:57059,chrome-os-partner:58355 TEST=manual Used console command "i2cxfer r16 0 0x40 0" to read the config register. Read 0x2771 [10097] which is the default value. In addition wrote register 14 and read back the value. Change-Id: If9e377da4c8f4835d4676281872a0f079fe56aa6 Signed-off-by: Scott <scollyer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/388794 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32l4: Add i2c driverDaisuke Nojiri2016-10-051-0/+17
| | | | | | | | | | | | | | This patch adds master and slave drivers for stm32l4 family. Only slave functionality is tested. BUG=none BRANCH=none TEST=Run cts.py -m i2c. Make buildall. Change-Id: Ied77081ca0333ab3fec055cd4f0fcbdf8a79d388 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393329 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Move I2C_MAX_HOST_PACKET_SIZE to i2c.hDaisuke Nojiri2016-10-051-0/+15
| | | | | | | | | | | | | | | This patch moves I2C_MAX_HOST_PACKET_SIZE to include/i2c.h. It's currently used only by i2c-stm32*.c but should be commonly available for other chips. It also moves i2c_get_protocol_info to common/i2c.c for the same reason. BUG=none BRANCH=none TEST=make runtest Change-Id: I28d8bca0167bb7b2ce99574601a6efb62fc20eca Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/393328 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Add i2ctest console commandVijay Hiremath2016-09-231-0/+36
| | | | | | | | | | | | | | | | | | Added i2ctest console command to test the reliability of the I2C. By reading/writing to the known registers this tests provides the number of successful read and writes. BUG=chrome-os-partner:57487 TEST=Enabled the i2ctest config on Reef and tested the i2c read/writes. BRANCH=none Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/290427 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common/i2c: Add I2C passthru_protect commandNicolas Boichat2016-05-241-0/+4
| | | | | | | | | | | | | | | | | | This allows the AP to protect a I2C passthru bus. A board-specific function then defines what I2C commands are allowed, so that we can white/black list some addresses (e.g. I2C address allowing PD chip FW updating). BRANCH=none BUG=chrome-os-partner:52431 TEST=Book elm-rev1 Change-Id: Ib106924418b16388ea8ea53c7b6bda6ef92e1d09 Signed-off-by: Nicolas Boichat <drinkcat@google.com> Reviewed-on: https://chromium-review.googlesource.com/345761 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@google.com>
* stm32f0: i2c: Set timing register values by port clock sourceShawn Nematbakhsh2015-10-301-0/+11
| | | | | | | | | | | | | | | | | I2C1 may be clocked by HSI or SCLK. I2C2 is always clocked by PCLK. Therefore, apply different timing register values according to the selected clock source for a port. BUG=chrome-os-partner:46188 BRANCH=None TEST=Manual on glados_pd. Verify slave i2c communication is functional. Change-Id: Icd2306d25d5863b0fc3379e46885a227efb23cca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309781 Commit-Ready: Gwendal Grignou <gwendal@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: Add i2c 32bit read/writeGwendal Grignou2015-06-171-0/+12
| | | | | | | | | | | | | Add functions and associated test to read/write a 32 bit register BRANCH=smaug TEST=Test on smaug with bm160 driver BUG=chromium:39900 Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c/mec1322: Lock all I2C port before sysjump.Kevin K Wong2015-06-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | sysjump could happen anytime during an I2C transaction. After sysjump and EC reset, I2C pin will be programmed back as GPIO instead of alternate function, which will cause the I2C transacation to failed. MEC1322 I2C also depends on interrupt to handle the I2C transaction, however, sysjump will disable interrupt, which will cause watchdog timeout/reset since interupt for I2C transaction are disabled. BUG=none TEST=After "sysjump <RO/RW>", "i2cscan" is functional and no watchdog reset. BRANCH=none Change-Id: I181084822f0769173c724e48afb59d7099fa1566 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/273710 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Implement i2c_set_timeoutShawn Nematbakhsh2015-06-031-0/+3
| | | | | | | | | | | | | Allow timeout to be set at runtime by controller. BUG=chrome-os-partner:40780 TEST=Manual on Glados. Verify PD I2C communication is functional. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I582e47c7bebfed7a639789c90064d86ffe1a5401 Reviewed-on: https://chromium-review.googlesource.com/274967 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: Make i2c_xfer a wrapper function to chip_i2c_xferShawn Nematbakhsh2015-05-271-2/+21
| | | | | | | | | | | | | | | | i2c_xfer was previously implemented at the chip-level, but now we want to add some global retry logic. Rename the chip-level i2c_xfer functions to chip_i2c_xfer and add a new global wrapper function i2c_xfer. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan, verify that values + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6 Reviewed-on: https://chromium-review.googlesource.com/272939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Support I2C controllers with multiple portsShawn Nematbakhsh2015-04-171-9/+29
| | | | | | | | | | | | | | | | | | | Certain chips have I2C ports mapped to the same controller. In this case, it's necessary to lock out access to the controller during use. This configuration can be supported by adding CONFIG_I2C_MULTI_PORT_CONTROLLER, which can be defined at the chip level, along with an API function to map port index to controller index. BUG=chrome-os-partner:38335,chrome-os-partner:38945 TEST=Manual with subsequent commit. Verify that i2cscan is functional on strago. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I37ffa661a2ad6cd2235cef2ee77637cc3ab92523 Reviewed-on: https://chromium-review.googlesource.com/265942 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
* EC: Add smbus interface read & write APIsSheng-Liang Song2014-08-291-0/+5
| | | | | | | | | | | | | | | | | | Ref: http://smbus.org/specs/smbus20.pdf - Support software CRC8 generation and checking. - Support read/write word (2-bytes) - Support read/write blocks (up to 32 bytes) BUG=chrome-os-partner:24741 BRANCH=ToT,glimmer TEST=Verified with smart battery firmware update application on glimmer. Passed LGC & Simplo Battery. Change-Id: Ic2e7f759af80c06741ed49fee1826213429fbf8a Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209747 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: add support for timeout configuration at runtimeRandall Spangler2014-07-301-0/+8
| | | | | | | | | | | | | | | | | When the EC sends longer commands to the PD chip (such as flash erase/write over the passthru from AP), allow it to take a second instead of the default 100ms timeout. BUG=chrome-os-partner:30935 BRANCH=none TEST=samus boots battery command works from EC console ectool passthru of flash erase to PD works (requires hacked ectool) Change-Id: I08ff94f7ac6aee351aa73c9d28b5fd715d463b3a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209936 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Combined i2c unwedge code into one common functionAlec Berg2014-03-061-4/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored the i2c unwedge code to place it in the common directory so that any EC chip can use it. Added to the STM32F and LM4 boards, code to automatically detect and unwedge the i2c bus at the start of an i2c transaction. Note that STM32L already had this ability. To enable unwedging of the i2c port though, the gpio pins for SDA and SCL must be defined in the i2c_ports[] array in the board.c file. This allows the i2c module to bit bang the unwedging for the given port. If SDA and SCL are not defined for the port, then the unwedge code will not run. BUG=chrome-os-partner:26315, chrome-os-partner:23802 BRANCH=none TEST=Manual testing on machines with different EC chips. Testing made extensive use of https://chromium-review.googlesource.com/66389 in order to force wedging of the i2c bus so that we can attempt to unwedge it. Note that you can easily test if the bus is wedged by running i2cscan. On pit and spring: On pit, after each of the following, I verified that the bus was automatically unwedged. On spring, the unwedge only runs at reboot, so, for the non-reboot wedge commands, I manually ran console command unwedge, and verified that the bus became unwedged. (1) Bit bang a transaction but only read part of the response. Command to wedge: i2cwedge 0x90 0 2 2 (2) Bit bang a transaction to do a "write" and stop while the other side is acking. Command to wedge: i2cwedge 0x90 0 1 (3) Same as (1) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 6 2 (4) Same as (2) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 5 On glimmer: Added code to call i2c_unwedge in accel_init(). Then tested unwedging the accelerometer with the following. One extra difficulty testing this with the accelerometer is that sometimes the bit you stop on is high, which means it won't be wedged at all, the next start transaction will reset the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes it will depending on the acceleration data. (1) Big bang transaction to do a "read" of accelerometer and stop partway: i2cwedge 0x1c 0x0f 2 2 i2cscan to make sure bus is actually wedged i2cunwedge i2cscan to make sure bus is now unwedged. (2) Bit bang transaction to do a "read" and stop partway, then reboot: i2cwedge 0x1c 0x0f 6 2. i2cscan to verify that the bus is working after the reboot. Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188422 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-191-2/+2
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* cleanup: Replace awkward I2C_PORTS_USED macro with constantBill Richardson2013-10-071-0/+1
| | | | | | | | | | | | | | | | | | | | We only used I2C_PORTS_USED to iterate through the list of hardware ports actually in use, but we defined it in board.h at the same place where we matched particular I2C devices to the (possibly shared) buses they're on. This CL makes I2C_PORTS_USED into a global constant, so it can be set automatically where we initialize the ports, and doesn't have to be related to the list of attached devices. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build everything, run all tests, should still work. Change-Id: I65f22f5cadfc4b3afe51af48faa5fb369bc3aa09 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171884
* Add build-time checks on board-specific array sizes.Bill Richardson2013-07-311-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've been declaring a bunch of statically-sized arrays: extern struct foo_t foo[FOO_COUNT]; And then initializing them like so: struct foo_t foo[FOO_COUNT] = { /* blah */ }; That only catches cases where we initialize with too many entries. It doesn't catch cases where we haven't initialized enough. This change tests for both cases like so: extern struct foo_t foo[]; struct foo_t foo[] = { /* blah */ }; BUILD_ASSERT(ARRAY_SIZE(foo) == FOO_COUNT); The affected arrays are: adc_channels[ADC_CH_COUNT] gpio_list[GPIO_COUNT] temp_sensors[TEMP_SENSOR_COUNT] x86_signal_list[X86_SIGNAL_COUNT] i2c_ports[I2C_PORTS_USED] BUG=chrome-os-partner:18343 BRANCH=falco,peppy TEST=build all platforms All platforms should still build, all tests should still pass. Change-Id: Ibb16dc3201f32df7cdc875648e89ba4ffb09f733 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63833 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Move i2cread and i2cwrite functions to i2c_commonRandall Spangler2013-04-301-0/+41
| | | | | | | | | | | | | | | | | | | | Also moves the handy i2cscan command to i2c_common. The platform-dependent interface is now i2c_xfer(). Still more to do in follow-up CLs; for example, i2c_read_string() has platform-dependent implementation, and the i2c/i2cread console commands aren't common yet. BUG=chrome-os-partner:18969 BRANCH=none TEST=i2cscan on link, spring Change-Id: Ia53d57beaa157bece293a4262257e20b4107589e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49492 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Daniel Erat <derat@chromium.org> Commit-Queue: Simon Glass <sjg@chromium.org>
* Move I2C arbitration to its own fileRandall Spangler2013-03-201-29/+1
| | | | | | | | | | | | | | | | | It's only board-specific in that we've only needed it on snow so far. But by that logic, x86_power would be board specific because we've only needed it on link. No functionality change, just moving code between files and renaming the interface to indicate it's not board-specific. BUG=chrome-os-partner:18343 BRANCH=none TEST=build daisy,snow,spring Change-Id: I35debdaa71829d55a2fbc5d3c62b2aaf6e467633 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/45879
* Implement board-level I2C arbitrationSimon Glass2012-06-291-0/+28
| | | | | | | | | | | | | | | | | | Add a way for boards to permit or deny access to the I2C port. This works in a board-specific manner. All I2C master traffic requires that board_i2c_claim() be called first. A dummy function is provided for boards which do not require this. BUG=chrome-os-partner:10888 TEST=manual: build for all boards boot on snow (cannot test i2c as it is broken) Change-Id: I786d4ae17f1d798faf13b303b5389679fb6720cb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26141
* Add a list of I2C portsRandall Spangler2012-05-171-0/+7
| | | | | | | | | | | | | | | | | This cleans up I2C init and debug commands across boards. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=on link and bds: i2cscan lightbar run powerbtn (to power on system) temps (to read i2c temp sensors) battery (to read battery) charger (to read charger) Change-Id: If3fb0cdb8d3178592bf68cbb2e72bc4b7f71dec5
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-191-3/+0
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* Add hooks module so modules can be notified of system-level events.Randall Spangler2012-04-191-16/+9
| | | | | | | | | | | | This will be used for sleep/wake/sysjump/etc. For now it's just wired up to clock frequency changing. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual: use nopll command, should still work Change-Id: Iedcea5830bc18eacfd955c29b8f793aba8905dd8
* Support dynamically changing the system clockRandall Spangler2012-04-091-1/+4
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
* Add I2C transmit/receive functionRong Chang2012-03-061-0/+12
| | | | | | | | | | | | | | | | | | | Implement a generalized I2C transmit-receive function that write-then-read blocks of raw data. Original 8-bit and 16-bit read/write functions are refactored. SMBus read-block protocol for ASCII string is also implemented based on this API. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:8026,8316 TEST=manual: Type 'lightsaber' to check 8-bit read/write. Type 'charger' to check 16-bit read. Type 'charger input 4032' to check 16-bit write. Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
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