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* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Hooks: Add HOOK_CHIPSET_HARD_OFFDiana Z2021-03-181-0/+2
| | | | | | | | | | | | | | | Add a new hook called HOOK_CHIPSET_HARD_OFF which is called upon entry to the G3 power state. BRANCH=None BUG=b:166787955,b:167996216,chromium:1045209 TEST=make -j buildall, runs on waddledee with no linking errors Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If260207910d882d17aeb766c9e99a7a6099006c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2415171 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common:test: refactor test_util.h to accommodate ZephyrYuval Peress2021-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change refactors test functionality in test_util.h to better accomomdate zTests. This is done by: * Removing the shim version of test_util.h. This was causing a conflict that made it harder to tell what's being used. This involved migrating some needed code over: - Defining different TASK_PARAMS. - Defining test_pass for Zephyr tests. * Creating a macro (DECLARE_EC_TEST) that will automatically handle creating the individual test functions for both platform and Zephyr tests. * Creating a macro (TEST_MAIN) that will automatically handle creating the main test entry function. This use to be test_main(void) for Zephyr and run_test(int, char**) for platform/ec. To do this we'll be removing the int, char** arguments from platform/ec. This may result in some tests having to be refactored, but overall should improve the test codebase as tests should remain deterministic (i.e. not depend on any outside arguments/parameters). * Creating some common ztest_ function/macros that will allow writing platform/ec tests in a zephyr like style. see test/base32.c for an example. * Update the type of __shared_mem_buf to match Zephyr. This was causing an issue now with the full test_util.h in zephyr/test/system/. BRANCH=none BUG=b:168032590 TEST=make runhosttests TEST=zmake configure --test -B build/host/base32 zephyr/test/base32 Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I72173a3e94c7df09a2966e7ffeb9f5668d030f29 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2634401 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* zephyr: Add basic support for shared memorySimon Glass2020-12-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | On the EC, shared memory is at the top of RAM, above all linker symbols that are located in RAM. Add a simple shim for this. At present it does enough to compile, but does not actually work. Yuval probably knows what should be done here. Add a Kconfig for the 'shmem' command. BUG=b:174873770 BRANCH=none TEST=build and boot on volteer (nothing useful happens) 20-12-04 15:22:49.267 shmem 20-12-04 15:22:50.011 Size:-537684993 20-12-04 15:22:50.011 Used: 0 20-12-04 15:22:50.011 Max: 0 Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I465c8519476e7c4a4cafba2f06630675f396c252 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2575207 Reviewed-by: Yuval Peress <peress@chromium.org>
* hooks: Introduce chipset resume init and suspend complete hooksWai-Hong Tam2020-07-301-0/+6
| | | | | | | | | | | | | | | | | | | | | These hooks are only enabled through a new CONFIG. The resume init hook will be used to initialize the SPI driver, which goes to sleep on suspend. Require to initialize it first such that it can receive a host resume event, that notifies the normal resume hook. The suspend complete hook is paired with the resume init hook, which reverts the initialization of the SPI driver. BRANCH=None BUG=b:148149387 TEST=make buildall -j TEST=Build successfully on both default off and defining this CONFIG. Change-Id: I615e2bf92c75f83a7b0ab3eded61a1ef241dbdcf Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321875
* hooks: Introduce HOOK_CHIPSET_SHUTDOWN_COMPLETEWai-Hong Tam2020-06-061-0/+2
| | | | | | | | | | | | | | | | | | | A new hook HOOK_CHIPSET_SHUTDOWN_COMPLETE is introduced, which are called from the chipset task, while the system has already shut down and all the suspend rails are already off. It will be used for executing pending EC reboot at the chipset shutdown. The EC reboot should be executed when the chipset is completely off. BRANCH=None BUG=b:156981868 TEST=Built all boards. Change-Id: I12f26957e46a1bb34ef079f127b0bddd133cd4e7 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2228395 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* remove cr50 related filesNamyoon Woo2020-03-091-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:149350081 BRANCH=none TEST=build all, and emerged ec related packages for host and octopus. $ make buildall -j $ cros_workon --host list chromeos-base/chromeos-cr50-dev chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge chromeos-cr50-dev -j $ sudo emerge chromeos-ec -j $ sudo emerge chromeos-ec-headers -j $ sudo emerge ec-devutils -j $ sudo emerge ec-utils -j $ sudo emerge ec-utils-test -j $ sudo emerge hdctools -j $ cros_workon-octopus list chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge-octopus chromeos-ec -j $ sudo emerge-octopus chromeos-ec-headers -j $ sudo emerge-octopus ec-devutils -j $ sudo emerge-octopus ec-utils -j $ sudo emerge-octopus ec-utils-test -j $ sudo emerge-octopus hdctools -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: If751b26b0635b0021c077338e96eaa8e8dcf17a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080631 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* log: Preserve Kukui EC reset logs across every EC reboot on SRAM.Shannon Chen2019-08-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Kukui, we need to put console logs and reset reasons at fixed addresses on SRAM to save the information across each EC resets. Otherwise, EC will lose console logs and reset reasons after resetting EC. This CL ensures that the contents of reset and console logs will not be clobbered or cleared by putting mandatory symbols at a fixed location on SRAM. The values will only be reset when checksum or sanity check fails. BUG=b:133795403 TEST=1. On Kukui, shutdown AP, reboot AP, or sysjump, and see the previous logs before reboot will be kept on /var/log/croc_ec.log 2. Reset reasons can be viewed with ectool uptimeinfo BRANCH=master Change-Id: I19db49101fda1675dc2fdc047b7f14af77cdb6e6 Signed-off-by: Shannon Chen <shannc@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716671 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Shannon Chen <shannc@chromium.org> Tested-by: Shannon Chen <shannc@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* minute-ia: move IRQ definitions to common filesJack Rosenthal2019-06-111-0/+1
| | | | | | | | | | | | | | | | | | | | By moving the __irq_data extern declaration into link_defs.h, the struct can be used in more than just interrupts.c. In addition, this provides a common struct definiton for IRQ definitions consisting of an IRQ number, the assigned routine, and a handler function, which is a fairly common way to store IRQ definitions. BUG=none BRANCH=none TEST=arcada ISH functions as normal Change-Id: Idbb5780ae965faeade74cfe319364f61dd933d9e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1649375 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* USB-PD: Add hook for PD connect eventDaisuke Nojiri2019-05-081-0/+2
| | | | | | | | | | | | | | | | This patch adds a hook for USB PD connect event. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/127228934 BRANCH=none TEST=buildall. Verify a hook is called on BC12 charger connection. Change-Id: I88fcd65d1afce07b6275398c5d0b902ecd7a44a3 Reviewed-on: https://chromium-review.googlesource.com/1597794 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* link_defs.h: Should support __SECTION attr when enable DRAM section.Yilun Lin2019-04-131-1/+1
| | | | | | | | | | | | | | | | DRAM symbols should be specified with __SECTION(dram) so that they can be put into DRAM sections. TEST=None BRANCH=None BUG=b:122058243 Change-Id: Ib8ba9054f27016424faa37d8b20e1f7e93a58c9f Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1563870 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui_scp: Enable CONFIG_LTONicolas Boichat2019-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix the stepping stone code stack_end definition to match the one in vecttable.c (else LTO complains). Add __keep to SECTION_KEEP to prevent LTO from dropping the stepping stone. BRANCH=none BUG=b:129111699 TEST=kukui_scp boots, kernel recognizes it TEST=Saves ~1.5kb of RAM. Before/after: *** 459968 bytes in RAM still available on kukui_scp **** *** 461528 bytes in RAM still available on kukui_scp **** Change-Id: I07e9d9ac003bdc5fce2617aa3aad072b51f89b6b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535089 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* core: Allow .bss and .data sections in DRAMNicolas Boichat2019-02-181-0/+7
| | | | | | | | | | | | | | | | | We manually copy other .data from the original section on boot, and clear DRAM .bss. This way, a single object file (or archive) can be moved fully to DRAM. BRANCH=none BUG=b:122058243 TEST=With next CL, dram_test works Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1445652 Reviewed-by: Jett Rink <jettrink@chromium.org>
* link_defs.h: Renames __ro_end to __data_lma_start.Yilun Lin2019-01-281-1/+1
| | | | | | | | | | | | | | | | | | The name of __ro_end is confusing. The variable is actually used as a label tagging that it is the starting address of .data LMA. Renames to __data_lma_start to be more decriptive. BRANCH=None TEST=make buildall -j BUG=b:122084384 Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1433160 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core/cortex-m: Support prevent chip memory region from GC.Yilun Lin2018-12-231-0/+3
| | | | | | | | | | | | | | | | | | | We would like to keep a symbol in a chip memory region from GC in link time. However __attribute__((used)) cannot fulfill the requirement in such situation. This CL adds a "name.keep" section to prevent all the symbols in this section in a chip memory region from GC. Also, we would like to support a non-NOLOAD section, which can load default value on runtime. BUG=b:120825336 TEST=make buildall -j BRANCH=none Change-Id: I76cf445f6b4c0b61c20182a1aaf5a44f962049ae Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373949 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tcpm:it83xx: GRL-USB-PD TDA2.1.2.2 BIST testRuibin Chang2018-09-071-0/+2
| | | | | | | | | | | | | | | | | | | | In our design once enter BIST test data mode, Hw don't interrupt Fw due to any Rx received packet. But when port partner re-connect in this mode, it will cause that our pd port doesn't respond packet which port partner transmits. When port partner disconnects, so we need to reset our pd port protocol layer and PHY to leave BIST test data mode and let Hw can interrupt Fw. With this modify it can pass GRL-USB-PD compliance TDA2.1.2.2 test item. BUG=b:112602596 BRANCH=none TEST=GRL-USB-PD compliance test. Change-Id: I30526b5d796e3eabc9af2f524071c98bb0ef5abf Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1170718 Reviewed-by: Jett Rink <jettrink@chromium.org>
* common: add BASE_CHANGE hookDmitry Torokhov2018-08-211-0/+2
| | | | | | | | | | | | | | | Add a hook to act when a detachable device is connected/disconnected from a base. BUG=b:73133611 BRANCH=nocturne TEST=Test with evtest that an event is sent to the AP. Change-Id: I21103fff88f19a197124095ee229eebb178dcf3d Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1180538 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cortex-m: add D-cache supportVincent Palatin2018-06-041-0/+5
| | | | | | | | | | | | | | | | | | | | Add support to enable the architectural D-cache on ARMv7-M CPU supporting it. Update the MPU code in order to be able to declare an 'uncached' RAM region (e.g. to store the DMA buffer). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=with the following CL, on ZerbleBarn, boot and capture a finger image. Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285 Reviewed-on: https://chromium-review.googlesource.com/1032776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* core: add chip-specific memory regions definition mechanismVincent Palatin2018-03-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a chip has special/non-contiguous SRAM physical memory region, rather than extending the generic linker file ad nauseam, define a mechanism to declare a chip specific list of those regions. To do so, a chip must declare the CONFIG_CHIP_MEMORY_REGIONS configuration and have a memory_regions.inc with the list of regions. The special-purpose preprocessed chip/<chip_name>/memory_regions.inc file has one region declaration per line using the following macro: REGION(name, attributes, start_address, size) Each region will get a proper MEMORY entry and a section in the linker file. the __SECTION(region_name) helper is provided as a convenience to declare variable in a specific region. Note: those 'special' regions are NOT cleared at startup contrary to .bss. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. Change-Id: I3f156ef6e5feb4a6a0b2ae2468bae8a20483f17c Reviewed-on: https://chromium-review.googlesource.com/946368 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32/usb: Add HOOK_USB_PM_CHANGE, called when USB is resumed/suspendedNicolas Boichat2018-02-021-0/+4
| | | | | | | | | | | | | | | | | | In particular, this will allow touchpad driver and keyboard matrix scanning to be powered off/disabled when the USB interface is disabled without setting the remote wake feature (USB_REQ_FEATURE_DEVICE_REMOTE_WAKEUP), as events would be ignored anyway. BRANCH=none BUG=b:72683995 TEST=With next CLs, touchpad and keyboard matrix scanning are disabled when lid is closed. Change-Id: I3750bfaf8c31cde075adf9da4fef39753b8981c5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/897067 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up CONFIG_CASE_CLOSED_DEBUG usageRandall Spangler2017-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1. All boards which use chip/g either use both CONFIG_USB_SERIALNO and CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on CONFIG_USB_SERIALNO. This is in preparation for making common/case_closed_debug refer only to the usb_pd_protocol version (with mode=disabled/partial/enabled), and cr50 will have its own version (with only enabled/disabled, and tied more closely to CCD config). No functionality changes. BUG=none BRANCH=cr50 TEST=make buildall -j; boot cr50 and see change hook called Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648067 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-07-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: Remove charge_state_v1Sam Hurst2017-02-061-2/+0
| | | | | | | | | | | | | | | | All boards have been transitioned to charge_state_v2.c So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and CONFIG_CHARGER_TIMEOUT_HOURS can be removed BUG=chrome-os-partner:36272 TEST=make -j buildall BRANCH=none Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a Reviewed-on: https://chromium-review.googlesource.com/435467 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: reset only the TPM state on SYS_RST_LRandall Spangler2016-09-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | Rather than doing a full cr50 reset when the system reset SYS_RST_L is asserted, just reset the state of the TPM task and library. Re-clear .bss for those modules, then re-initialize. BRANCH=none BUG=chrome-os-partner:52366 CQ-DEPEND=CL:366792 TEST=make buildall; test on Gru Trigger a SYS_RST_L by using the AP's reboot command, power off/on, log in/out/in. See that the Cr50 does not reboot and the firmware and userspace are still happy about the TPM. Change-Id: I32cd2bb72316f68c74db77a20a8d09112b402d4b Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/361680
* common: Add TABLET_MODE hook.Gwendal Grignou2016-09-071-0/+2
| | | | | | | | | | | | | Add a hook to act when the a device is going in tablet mode and back. BUG=chromium:606718 BRANCH=kevin TEST=Test with evtest that an event is sent to the AP. Change-Id: Ic9c3b158f1178504af41abff18b28de8e07fc7a7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/380412 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* add the 'extension' command frameworkVadim Bendebury2015-11-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a facility which would allow to compile in callbacks for arbitrary commands passed over various communication protocols. Typically this will be used for testing, when various test commands are multiplexed over an existing protocol. The callbacks are associated with 16 bit command codes. On input the callback receives a buffer, containing the command's argument, the size of the command argument and the maximum size of the buffer. On output the callback stores processing result in the same buffer and updates the size to the actual amount of returned data. Callback descriptors are stored in a dedicated read only section which is scanned by extension_route_command() to find a callback associated with a certain command code. A console channel is also being introduced to allow controlling console output generated by extension commands handlers. BRANCH=none BUG=chrome-os-partner:47524 TEST=none yet Change-Id: I8ae16a78ca7d72176a5e7f74dd7a232078e7c06c Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312586 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: export the linker generated addresses of image sectionsVadim Bendebury2015-11-101-0/+5
| | | | | | | | | | | | | | | The values are there, we just need to be able to access them from the code to be able to calculate how much of the flash space needs to be made accessible for the image to run. BRANCH=none BUG=none TEST=used by later patches Change-Id: I4eb59525a50177cc7cc725871c3eab2ff390667b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311319 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* host: mock i2c_xferGwendal Grignou2015-09-161-14/+2
| | | | | | | | | | | | | | | Instead of mocking i2c_read8/16/32, mock i2c_xfer. We can now test code that call i2c_xfer directly and test common/i2c.c BRANCH=samus, ryu BUG=chrome-os-partner:45223 TEST=Unit tests pass. Change-Id: Iaa772515c40cf55d2050d0019e2062d63278adc0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299768 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* common: Add i2c 32bit read/writeGwendal Grignou2015-06-171-0/+4
| | | | | | | | | | | | | Add functions and associated test to read/write a 32 bit register BRANCH=smaug TEST=Test on smaug with bm160 driver BUG=chromium:39900 Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* USB: Fix memcpy routinesAnton Staaf2015-04-131-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memcpy like routines for moving to and from usb packet RAM couldn't deal with all unaligned uses, this fixes their behavior. In particular, a previous caller might assume that the packet RAM addresses were contiguous and attempt to break up a call into two separate chunks (as the queue insertion/removal code does). But this can lead to invalid pointers passed to these memcpy routines. A much cleaner solution is to make the packet RAM address space contiguous. To do so the memcpy routines take packet RAM addresses instead of AHB address space mapped addresses and __usb_ram_start needed to change to be of type usb_uint so that pointer arithmatic on it worked correctly on all platforms, this also allowed the usb_sram_addr macro to be simplified. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verify that USB still works on Ryu and discovery-stm32f072 Change-Id: I479461f07a3203f1e6e0cf9705f512a5a43c4646 Reviewed-on: https://chromium-review.googlesource.com/264764 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* hooks: add hook for battery state of charge changeAlec Berg2015-02-031-0/+2
| | | | | | | | | | | | | | Add hook for battery state of charge change. Hook will be used to cleanup the samus charging workarounds to follow. BUG=none BRANCH=samus TEST=make -j buildall Change-Id: I99cbb8264783802139cac689804b056623063695 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/245252 Reviewed-by: Shawn N <shawnn@chromium.org>
* MKBP event signalling implementationVic Yang2014-10-241-0/+5
| | | | | | | | | | | | | | | | | | | This implements a new API for EC modules to define MKBP event sources and send MKBP event to the AP. Also, a new host command EC_CMD_GET_NEXT_EVENT is added for the AP to query the pending MKBP events. Each event type may have custom event data sent along with the event. BRANCH=None BUG=chrome-os-partner:33194 TEST=Enable MKBP event on Ryu. Set a host event from EC console, run 'ectool nextevent', and see MKBP event 0x01 (HOST_EVENT) and the set host event. Signed-off-by: Vic Yang <victoryang@chromium.org> Change-Id: I28a1b7e826bcc102bbe39016c9bb3e37d125664c Reviewed-on: https://chromium-review.googlesource.com/224905 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: add USB driverVincent Palatin2014-06-181-0/+5
| | | | | | | | | | | | | | | | | | Enough USB support to be able to enumerate the device and use bulk or interrupt endpoints. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28295 TEST=with the following USB console CL, connect a Fruitpie through USB and use its console over USB. Change-Id: I37b7f3b6a754cb82ab5f940ea20122d2e16b3b5b Reviewed-on: https://chromium-review.googlesource.com/193983 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* ite: Port OS layer to Andestar v3m architectureVincent Palatin2013-12-101-0/+1
| | | | | | | | | | | | | | | | | This will be used to support ITE IT8380 chip which contains an Andes N801 core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=make BOARD=it8380dev Change-Id: I91f9380c51c7712aa6a6418223a11551ab0091ce Reviewed-on: https://chromium-review.googlesource.com/175480 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Fake I2C device support for emulatorVic Yang2013-09-171-0/+13
| | | | | | | | | | | | | | | | | To test drivers, we need a way to fake I2C periphrals. With this CL, a fake peripheral can be done by declaring its own I2C read/write functions. The fake I2C peripherals may return EC_ERROR_INVAL to indicate it's not responding. The emulator I2C read/write call scans through all registered I2C peripherals and uses the first response. BUG=chrome-os-partner:19235 TEST=Pass sbs_charging test with the next CL. BRANCH=None Change-Id: I9380dc40e147781b42e09eb6979c864bbd9f2ac4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169511 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32l: Add a "PRE_FREQ_CHANGE" hook to allow other code to prepareDoug Anderson2013-08-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change drivers had no way of knowing that a frequency change was coming. This could cause problems for some drivers (like i2c) that need to make sure that a transaction isn't happening while a frequency change is happening. The PRE_FREQ_CHANGE archiecture is very simple here and we don't allow any way to cancel it. At the moment, we guarantee: - We won't call PRE_FREQ_CHANGE with interrupts disabled, so acquiring locks / sleeping is OK. - We'll call the actual HOOK_FREQ_CHANGE after the PRE_FREQ_CHANGE. PRE_FREQ_CHANGE and HOOK_FREQ_CHANGE should not use deferred function calls. BRANCH=pit BUG=chrome-os-partner:22093 TEST=With all patches together: - on AP: suspend_stress_test - on EC: battery 10000 50 Change-Id: I2731a3e85d41e749fa571fdb74b5c9b12043cda6 Signed-off-by: Doug Anderson <dianders@chromium.org> Previous-Reviewed-on: https://chromium-review.googlesource.com/167101 (cherry picked from commit d84c0dbbf7c5a72917a820e292ecfdfa698d0fb9) Reviewed-on: https://chromium-review.googlesource.com/167148 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add hook for changes in the charge state machineDave Parker2013-08-011-0/+2
| | | | | | | | | | | BUG=chrome-os-partner:20145 BRANCH=falco,peppy TEST=Manual. Tested with charging timeout logic. Change-Id: Iab1c9746dcab5820fcdeb3e0d94bfcb0c47e57f2 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63537 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Pthread-based emulator for unit testingstabilize-4100.38.BVic Yang2013-05-071-0/+63
This is the first version of pthread-based RTOS emulator. With this, we will be able to test high-level modules entirely on the host machine. BUG=chrome-os-partner:19325 TEST='make runtests' and see tests passing. BRANCH=None Change-Id: I1f5fcd76aa84bdb46c7d35c5e60ae5d92fd3a319 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49954 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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