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* include/lpc.h: Expose lpc_aux_put_charRaul E Rangel2020-03-021-0/+8
| | | | | | | | | | | | | | | * Expose lpc_aux_put_char so we can call it from common/keyboard_8042. * Renamed lpc_mouse_put_char to lpc_aux_put_char so it's more generic. * Added the send_irq parameter for parity with lpc_keyboard_put_char. BUG=b:145575366 BRANCH=none TEST=Verified it builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61854ed7c9b9ad1c50e55735747cfb25ca15762b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2079694 Reviewed-by: Edward Hill <ecgh@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* lpc: remove lpc_host_resetJett Rink2018-03-261-5/+0
| | | | | | | | | | | | | | | | | No one is using this method and it implies that all chipset should support the RCIN# Virtual Wire if using eSPI. Only large core chips use RCIN#; small core chips don't. This method was introduced for skylake and has since been replaced since CL:575947 was merged. BRANCH=none BUG=none TEST=build all Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/975904
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-0/+6
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* host_event: Perform lpc_init_mask before keyboard/button initFurquan Shaikh2017-10-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | keyboard/button init are responsible for checking if user requested manual recovery. However, by this time, hook init is not run and hence host event set operation for manual recovery is dropped. This change adds a call to lpc_init_mask before keyboard/button init operations are performed. BUG=b:68189465 BRANCH=None TEST=Verified that manual recovery works fine. Recovery using software command works too: reboot ap-off hostevent set 0x4000 powerb Change-Id: I15cb648d4b253a523293c7ab2cd3e8e08e31a763 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/735799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_event_commands: Add support for always reporting masksFurquan Shaikh2017-10-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new mask type (ALWAYS_REPORT mask) that is set by default to certain host events that should always be reported to the host irrespective of the state of SCI, SMI and wake masks. This mask includes host events like critical events resulting in shutdown or reboot, events that are consumed by BIOS, etc. Now that ALWAYS_REPORT mask is added, this change also updates the way EC manages set/query operations for host events: 1. During set operation, EC will check if the host event is present in any of the 4 masks - SCI, SMI, wake and always report. If yes, then it is set in hostevents. 2. During query operation, EC will extract the lowest set event from hostevents, clear it and return it back to the host. In order to reflect the above change in EC behavior, a new feature bit is used EC_FEATURE_UNIFIED_WAKE_MASKS. This allows the host to decide when wake mask needs to be set before checking for host events. BUG=None BRANCH=None TEST=make -j buildall. Also verified following: 1. Wake from S3 works as expected. Host is able to log correct wake sources (Verified power button, lid open, base key press and tablet mode change on soraka). 2. Wake from S5 works as expected. Host is able to log correct wake sources (Verified power button, lid open on soraka). 3. Wake from S0ix works as expected (Verified power button, lid open on soraka). 4. Software method to trigger recovery still works fine: reboot ap-off hostevent set 0x4000 powerb Change-Id: I62e5c1f82247c82348cd019e082883d86ec2688f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/719578 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-5/+22
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* intel_x86: Make common code for LPC S0 <-> S0ix transitionsVijay Hiremath2017-01-211-3/+0
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=Manually tested on Reef. System can enter and exit from S0iX when LID is closed & opened respectively. Change-Id: I5892da327c2dcdd400d5a7ade867bec1b80cbaa4 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407047 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add function for host reset without RCIN GPIODuncan Laurie2016-10-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | Prior x86 boards have had GPIO for toggling RCIN directly on the PCH, although many likely had HW-assisted methods as well. With eve we need to generate an eSPI Virtual Wire for RCIN, but in reality software control over RCIN Virtual Wire is not available with the npcx EC, so the legacy LPC interface for pulsing KBRST must be used instead as this is the only way to generate RCIN. This method will likely vary on different EC chips, but for skylake it can just be abstracted into the LPC module. BUG=chrome-os-partner:58666 BRANCH=none TEST=successful 'apreset warm' on eve EC console Change-Id: I7f9e7544a72877f75d05593b5e41f2f09a50e1c9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400037 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: set and clear wake masks in S0 <-> S0ix transitionsArchana Patni2016-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the wake masks when the SMI is invoked. For S0ix, EC sets and clears the wake mask via this patch. These functions are directly invoked from the state machine transition states. During S0ix entry, the wake mask for lid open is enabled. During S0ix exit, the wake mask for lid open is cleared. All pending events are also cleared BRANCH=none BUG=chrome-os-partner:48834 TEST=test lidopen in S0ix Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f Reviewed-on: https://chromium-review.googlesource.com/320190 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix assertion crash in __wait_evt()Chiranjeevi Rapolu2015-06-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF interrupt context, causing deadlock and assertion in __wait_evt(). In the interrupt context it now checks for mutex lock first. If the mutex is already locked,, it will disable ACPI interrupts and defer the memmap mutex lock. Added LPC interrupt disable/enable functions as needed. Increased deferred function count where needed. BRANCH=None BUG=chrome-os-partner:40820 TEST=Test for suspend-resume, cold, warm reboots and other general stability. Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280418 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.BShawn Nematbakhsh2015-03-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | Some platforms are unable to access the 900h-9ffh region over LPC and must instead access memmap data through the ACPI CMD / DATA ports. To avoid racing with data updates, disallow changes to multi-byte memmap data while in burst mode. Linux currently enables burst mode when accessing multi-byte data and disables it immediately afterward, though the ACPI spec defines burst mode in a more general way. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap data to ERAM at offset 0x20. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262072 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* baytrail: Workaround for stuck boot processRandall Spangler2014-04-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases, the system will boot to S0 from the point of view of the EC, but PLTRST# will never deassert. Work around this by waiting 50 ms for PLTRST# to deassert. If it doesn't, force the chipset all the way down by deasserting RSMRST#, then pulse the power button to turn it back on. Also add a powerfail debug command to simulate this failure event, so that the recovery process can be tested. Add API to the LPC module to get the state of PLTRST#, and to the power button state machine to force it released when we shut down the chipset and and force another power button pulse as we reset the chipset. BUG=chrome-os-partner:28422 BRANCH=baytrail TEST=1. Boot system. Should boot normally. Shut system down. 2. powerfail 3. Boot system. On the EC console, should see the system come up, go back down through G3S5, then come back up. From the user's point of view, it just boots. 1. Boot system. Should boot normally. (That is, powerfail is not sticky) Change-Id: Ia57f196606f79b9f2fce7d9cd109ab932c3571aa Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197523 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Move ACPI stuff out of chip/lm4 and into commonBill Richardson2013-12-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The port 62/66 ACPI commands were implemented in chip/lm4/lpc.c. They should be handled in common instead of being tied to a particular EC. BUG=chrome-os-partner:23774 BRANCH=none TEST=manual read EC_ACPI_MEM_VERSION # iotools io_write8 0x66 0x80; iotools io_write8 0x62 0; iotools io_read8 0x62 0x01 write & read EC_ACPI_MEM_TEST # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x5a # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x44 read & write EC_ACPI_MEM_KEYBOARD_BACKLIGHT # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 100 (keyboard lights up) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 50 (keyboard dimmer) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 0 (keyboard goes dark) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x00 read & write EC_ACPI_MEM_FAN_DUTY # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 100 (fan on full) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 50 (fan on half speed) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0 (fan off) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x00 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0xff (fan back to EC control) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0xff test EC_CMD_ACPI_QUERY_EVENT # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 On EC console: > hostevent set 0x0f000000 # ectool eventget Current host events: 0x0f000000 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x19 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1a # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1b # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1c # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 # ectool eventget Current host events: 0x00000000 Change-Id: I011a5a2051171ec1d37e55ce03e1ce74b93a7e14 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179692
* More supports for A20 enable/disableLouis Yung-Chieh Lo2012-11-041-0/+3
| | | | | | | | | | | | | | Add i8042 output port commands (0xf0-0xff), I8042_ENABLE_A20 and I8042_DISABLE_A20. BUG=chrome-os-partner:13119, BRANCH=None TEST=Tested on W7 installer. No KB error shown on EC console. Change-Id: I9ad1fd7baa10683ef18ccf13faf09dc0cefcca0a Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/34994 Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* Clean up LPC moduleRandall Spangler2012-10-301-19/+41
| | | | | | | | | | | | | Tidied comments, and removed handling of ACPI events on host command port (not needed since EVT hardware is now EOL'd). BUG=chrome-os-partner:15579 BRANCH=none TEST='ectool hello' succeeds Change-Id: I063382b9981f713ba23f7714b4ccb7faa957b411 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36804
* Simplify host event processingRandall Spangler2012-07-121-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | Now both copies of the event state live in host_event_commands.c, and lpc / memmap just shadows the main copy. BUG=chrome-os-partner:11172 TEST=manual Boot system. should see events 0x2000, 0x80, 0x08 get set and then cleared. At U-boot prompt, type on keyboard. Should set event 0x1000 get set, but only on the first keypress (because U-boot doesn't consume that event). Then from EC console, hostevent clear 0x1000 -> see event 0x1000 clear hostevent clear 0x1000 -> no debug output (it's already clear) hostevent clearb 0x1000 -> see event copy B 0x1000 clear hostevent clearb 0x1000 -> no debug output (copy B is already clear) Change-Id: I855c035865649ba1490cd9027157d5bcdcc9895f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27321
* Fix some behaviors of keyboard command handlers.Louis Yung-Chieh Lo2012-05-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The phenomenon is that there is a char on-hold in port 0x60 and the kernel never picks it up. Hence the keyboard cannnot be recognized after resume. It comes from multiple reasons: 1. The command I8042_CMD_RESET_BAT(0xff) and I8042_CMD_ENABLE(0xf4) didn't clean the buffer. 2. clean_underlying_buffer() has clean the queue, but forgot to clean the TOH (TO Host). Add keyboard_clean_buffer() to clean the TOH (To Host). 3. When KB interrupt is just enabled, the IRQ didn't sent if there is a char queued in buffer already. keyboard_resume_interrupt() solves this. 4. Not all keyboard reset should reset the buffer. Only the enable/disble of controller RAM should NOT reset buffer. Other enable/disable should clean the buffer. 5. i8042 commands (those commands to port 0x64) should NOT return ACK even the parameter byte(s) goes to port 0x60. 6. Keyboard was disabled by kernel, but key stroke still sent to host (this needs the BIOS to fix). Also fix the minor issues: 1. I8042_CMD_RESEND should not return I8042_RET_ACK. 2. I8042_DIS_KB/I8042_ENA_KB should effect the controller RAM content. 3. only send out the scan code when keyboard is enabled. 4. add kblog command for future debug (disabled by default because it neeeds 1KB of memory). Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> BUG=chrome-os-partner:9525 TEST=tested on link. Start from S0. 1. Run powerd_suspend. 2. Expect system is in S3. 3. Press any key to wake up system. 4. Expect system is up and keyboard is working. 5. repeat for 20+ times. Change-Id: I1c48822687d7c1f7ef0e8d8bca54bf9b05fd785f
* Slightly update the host commands APIVincent Palatin2012-05-141-10/+0
| | | | | | | | | | | | | | | | | | | | Preparatory work to use common host command code between ARM and x86. Every command sends back explicitly the size of the response payload. The size of the response defaults to 0 ond can be updated. Add a protocol version number returned as command 0x00 to help with backward compatibility. move a couple of function from lpc specific header to host commands to be able to implement them for the I2C link. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9614 TEST=make BOARD=link Change-Id: I6a28edf02996ddf6b7f32a3831d07d5f0271848f
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-191-14/+10
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* Add wake signal to PCHRandall Spangler2012-03-151-4/+11
| | | | | | | | | | | | | | | | | | | | | | This works similar to SCI/SMI events, but triggers a separate level-sensitive signal to the PCH instead. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8514 TEST=manual From EC console: gpioget PCH_WAKEn --> should be 1 hostevent wake 0x1 close lid switch (with magnet) hostevent -> should show wake mask 0x1, raw events 0x1 gpioget PCH_WAKEn --> should be 0 hostevent clear 0x1 hostevent -> should show raw events 0 gpioget PCH_WAKEn --> should be 1 Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
* Add SMI/SCI supportRandall Spangler2012-03-051-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:8277 TEST=manual On EC console: hostevent set 0x1e From root shell: ectool eventget --> should return 0x1e ectool eventclear 0x02 ectool eventget --> should return 0x1c ectool queryec --> should return event 3 ectool queryec --> should return event 4 ectool queryec --> should return event 5 ectool queryec --> should return no event pending ectool eventsetsmimask 0x1200 ectool eventsetscimask 0x0034 ectool eventgetsmimask --> should return 0x1200 ectool eventgetscimask --> should return 0x0034 On EC console: hostevent --> should show raw=0 SMI mask = 0x1200 SCI mask = 0x34 Change-Id: I33042fa80c0b148cd63209a94a184af493e25ed3
* Refactor LPC status / result codesRandall Spangler2012-03-011-3/+2
| | | | | | | | | | | | | | | This is necessary to support SCI/SMI events. Note that this breaks compatibility with previous ectool builds - and probably also breaks flashrom support. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8253 TEST='ectool hello' and 'ectool flashinfo' still work and 'ectool usbchargemode 3 1' fails with error 2 Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
* Register host commands the same clever way we do console commandsRandall Spangler2012-02-281-2/+0
| | | | | | | BUG=none TEST=run assorted ectool commands Change-Id: I830d3cbf2d1557b3ab455ec8736d3de5e5d3e697
* Reduce LPC command parameters to 128 bytes; add LPC memory-mapped spaceRandall Spangler2012-02-151-1/+5
| | | | | | | | | | | | This will allow more efficient access to EC-provided data (temperature, fan, battery) by the main processor. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7857 TEST='ectool hello' from link main processor should still work Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
* Add UART1 receive support (UART to x86 console)Randall Spangler2012-02-061-0/+3
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7488 TEST=type things into the x86 console UART; should appear on the u-boot prompt Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
* Fix the missing IRQ problem.Louis Yung-Chieh Lo2012-02-021-0/+13
| | | | | | | | | | | | | | | | | | | | The problem comes from the different assumption of interrupt mode in EC and the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge. However, the auto-IRQ functino of EC is level-triggered and uses low-active to assert an IRQ. This makes the deadlock so that the kernel never gets an interrupt until a byte is manually pulled from host. So, the solution is manually firing an IRQ_1 to host after EC puts a byte to port 0x60. Note that the auto IRQ needs to be disabled in order to avoid the interference with manual IRQ generation. This CL also moves chip specific code to lm4/lpc.c and handle some minor keyboard commands. BUG=none TEST=on hacked baord. Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
* Clean up UART codeRandall Spangler2011-12-121-0/+6
| | | | | | | | | | | | LPC module no longer directly talks to UART registers, and vice-versa. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='ectool sertest' on target system Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648 (cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
* Add user-mode LPC endpointRandall Spangler2011-12-081-4/+6
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='ectool hello' on target system Change-Id: I39845c2ea107ea6f85ef556d58e49343f5a0e9c0
* Initial sources import 1/3Randall Spangler2011-12-071-0/+26
source files mainly done by Randall. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
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