| Commit message (Collapse) | Author | Age | Files | Lines |
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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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C++ does not allow enums to be forward declared unless they have a type.
BRANCH=none
BUG=b:144959033
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I6fcdedc81f2b60a44b750554939e60552a4c6a77
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740567
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Move the sleep failure detection logic from intel_x86 power sequence to
a common library, i.e. host_sleep.
This CL simply moves the code, without any logic change.
BRANCH=None
BUG=b:162083524
TEST=Build the hatch board.
Change-Id: Ia3f70804ded8d80c4a079a36fbf1819c05a2090b
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321874
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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BRANCH=none
BUG=b:159571683
TEST=make BOARD=krane -j tests
Change-Id: I0484bbb5b6dcb0703aace88be59248968a662bb5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2256631
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This patch add config: CONFIG_POWER_SUGNAL_RUNTIME_CONFIG
to allow board modified power signal gpio if needed.
BUG=b:150278507, b:152841287
BRANCH=none
TEST=make buildall
Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com>
Change-Id: I5c885f9cb3400f3354a18b6d497340dfe3ad993b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2256624
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Currently, we can only wait for a signal is presented via
power_wait_signals*(). However, we might want to wait a
power signal disappeared. power_wait_mask_signals_timeout()
does the thing, which can wait until a power signal is
disappeared.
BRANCH=master
BUG=b:150341779
TEST=test with CL:2120114
Change-Id: I0bbc04fcf76e67d7cfe86096a42e3b767a136ef9
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2176820
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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Some boards need different mechanisms to enable/disable the 5V rail
that's not simply setting the PP5000_EN GPIO. This commit adds a new
board specific API to control the 5V rail. If a board needs something
more complex, they should define `board_power_5v_enable`.
BUG=b:149794574
BRANCH=None
TEST=Add definition for waddledoo, build and flash, verify that
sub-board 5V is turn on as well.
Change-Id: I333e3fb8f2b4e7f1907c792c0e35581150857f17
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065494
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This commit makes power_signal_get_level() overridable as there are some
boards (like dedede) which have power sequencing inputs which are not
simply just GPIOs nor eSPI VW.
BUG=b:148169171
BRANCH=None
TEST=`make -j buildall`
Change-Id: I16fbf54b0688b432c82312a431f1d9f7cc074278
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2032727
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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Hatch designs buffer the PG_EC_RSMRST# signal from the
Silego power good logic through the EC and out EC_PCH_RSMRST# to the
SoC RSMRST# pin. For power off transitions, this should be as fast as
possible, in the ns region if possible. However this time is ~1 msec.
To reduce this delay as much as possible this CL introduces a new
interrupt handler than can be linked to the rsmrst gpio signal. This
interrupt routine handles high->low transitions directly to minimize
the propagation delay. The power_signal_interrupt is then called which
will wake up the chipset task, and low->high transistions continue to
be handled in the power state machine.
BUG=b:132421681
BRANCH=None
TEST=Shorted PP1050_A_PG to ground to force an abrupt power down and
then measured time via scope between PG_EC_RSMRST and
EC_PCH_RSMRST. The delay is reduced from ~1 msec to 45 uSec.
Change-Id: I266138a2e235ce47f3060f8e1f6f9bc6a75073ae
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757267
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
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This CL annotates __overridable to the following functions:
board_system_is_idle
power_chipset_handle_host_sleep_event
power_board_handle_host_sleep_event
TEST=make buildall
BUG=none
BRANCH=none
Change-Id: I0168b69c49fab5672238711d4f3a6a5517cdd8b3
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1761759
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Removed redundant code in intel_x86 and reusing the common code
for getting power signal's level.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I9cd550a2326456189a087459aeb8e6c88a8cad8e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1667647
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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When S0ix failure detection is enabled and a timeout occurs such that
the SLP_S0 line never actually toggles, then s0ix_transition_timeout()
sets the HANG_DETECT event bit. This doesn't quite work in this scenario,
since the wake mask is only enabled when the power state transitions to
S0ix, which happens when the SLP_S0 line toggles. So the AP never sees the
event, since it's not in the wake mask and so never causes the EC->AP
interrupt line to change.
Detect this situation in the timeout function, and explicitly move the
wake mask to its S0ix value so that when the event bit is set, (if it
is in the wake mask), the system will wake up.
Doing this forcefully gets the wake mask out of sync with the power state.
So upon resume, explicitly restore the wake mask to its S0 state.
BUG=b:131434497
BRANCH=none
TEST=suspend_stress_test -c1 --suspend_min=60 with a firmware where
S0ix fails.
Change-Id: Id2e67c6933a7895fba85ccfdff9b336629eabf24
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1592469
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This change introduces logic in the EC that can detect if the host
attempted to go into S0ix, but never made it. The host already sends
commands indicating its intent to enter S0ix, and the EC has a SLP_S0
line that gets asserted by the AP when it actually enters S0ix.
All that's needed to monitor failures is to arm a timer when receiving
the S0ix suspend message. If the SLP_S0 pin goes low, then the suspend
occurred and the timer is canceled. If the timer expires before SLP_S0
goes low, then the EC wakes the AP up, since it has entered a shallower
idle state than intended, and should be alerted to avoid short battery
life.
The timer is also started when SLP_S0 is deasserted on resume. The
SoC comes out of S0ix to perform housekeeping activities unbeknownst
to Linux. In cases where housekeeping fails to suspend all the way back
down, this timer will wake the AP. Additionally, the number of S0ix
transitions is reported on resume. This enabled the AP to analyze the
amount of "sleepwalking" that is done, and can complain if it seems to
be waking up too often.
Design doc at:
https://docs.google.com/document/d/1mY-v02KAuOyET3td9s5GnxeUgMiAcD058oLEo57DZpY/edit
BUG=b:123716513
BRANCH=None
TEST=Test S0ix on hatch with modified code that forces a timeout,
use ectool to send messages manually before and after timeout,
Hack Linux to fail suspend very late to verify no regressions.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ia64b496675a13dbed4ef74637f51e39eee68aa1a
Reviewed-on: https://chromium-review.googlesource.com/1501512
Commit-Ready: Evan Green <evgreen@chromium.org>
Tested-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
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Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This patch adds power_get_state API, which returns the low-level power
chipset state.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I104fdf9623f64416d8c27d583cd434920808afdb
Reviewed-on: https://chromium-review.googlesource.com/1144447
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit 352276235ca18404a42ca01b75de3fdc7951e271.
This is required to ensure that PMIC VR decay is enabled before
SLP_S0# is asserted. Else, the setting does not take effect and hence
results in higher power consumption.
BUG=b:69337192
BRANCH=None
TEST=make -j buildall
Change-Id: I6885e7447277d853a2414be299dfea25f5547df4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/771054
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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power_board_handle_host_sleep_event was added to allow boards like
poppy to enable/disable PMIC VR decay only once during S0ix
entry/exit. Now that the chipset hooks have been fixed, there is no
need of this board specific callback. If in the future, there is a
need to have such a callback, this change can be reverted.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I1d60e43da6c0d462132593efa26bc52312b81786
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of using HOST_SLEEP_EVENT_S0IX_RESUME as a reset state to
reinitialize S0ix flag, add a new default state
HOST_SLEEP_EVENT_DEFAULT_RESET. This also allows different parts of
the code to take correct action depending upon the state that is
currently triggered.
BUG=None
BRANCH=None
TEST=Verified that SLP_S0# interrupt doesn't get asserted during
runtime S0ix.
Change-Id: Id6fc8f3b015561d2899a9d39796b77a11a57e758
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/745901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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For certain cannonlake designs, the 5V rail can be controlled by both
the chipset task as well as other tasks such as the USB charger tasks to
perform BC1.2 detection. This commit introduces an API that allows the
tasks to enable/disable the 5V rail. Enable requests will immediately
enable the rail, however, attempting to disable the rail will only
result in a request. Once all tasks want to turn off the 5V rail, the
rail will be turned off.
A bitmask is introduced to keep track of the requests. Index 0 is for
the chipset task.
All of this is gated behind a config option:
CONFIG_POWER_PP5000_CONTROL
BUG=b:65991615
BRANCH=None
TEST=With other zoombini code, verify that 5V can be enabled and disabled.
Change-Id: I1722b4a272c4d6ee24408929f5a7402051bb9cf3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/722322
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Add a new flag to allow boards to indicate if a power signal has to be
enabled/disabled at boot.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Ibe7ab74e8191c58433087d8024b344d7e845f17e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679981
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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1. Make power_signal_enable_interrupt visible outside power/common.c
2. Add corresponding power_signal_disable_interrupt function.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: I04b7b053cc1ffe978fcbac5b2cb746d21b198aa2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679980
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Replace structure member "level" in power_signal_info with "flags".
"level" has been used on all boards to indicate active-high or
active-low levels. Addition of "flags" allows easy extension of
power_signal_info structure to define various flags that might be
applicable to power signals (e.g. "level"). Going forward, additional
flag will be added in follow-up CLs.
Also, provide a helper function power_signal_is_asserted that checks
the actual level of a signal and compares it to the flags level to
identify if a power signal is asserted.
BUG=b:65421825
BRANCH=None
TEST=make -j buildall
Change-Id: Iacaabd1185b347c17b5159f05520731505b824b8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/679979
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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This change allows chipset and board to perform any action when host
indicates intention to enter sleep state. Chipset can take action like
enable/disable power signal interrupts and boards can enable/disable
decay of VRs on host intent to enter/exit S0ix.
BUG=b:65732924
BRANCH=None
TEST=make -j buildall
Change-Id: I6298825d4ee96a07b93523c2f366527ae2be8a27
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/677498
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BRANCH=none
BUG=chrome-os-partner:58740
TEST=Build/flash EC and check 'echo freeze > /sys/power/state'
command in OS shell. Verify idle state transitions during display off
and periodic wakes from S0ix do not lead to state transitions in EC.
Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401072
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Picked the code from Glados branch.
Change-Id: I4bf114235c4d542dd7cf0dad6427c771e54d4611
https://chromium-review.googlesource.com/#/c/331358/
BUG=chrome-os-partner:59742
BRANCH=none
TEST=make buildall -j
Change-Id: Ib79f1209dfd9e6a9de0438cb1866bba2939e5393
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410036
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
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PGOOD_AP may go low for a period < 100ms during regulator output voltage
transitions, so ignore such pulses.
BRANCH=None
BUG=chrome-os-partner:54814
TEST=On kevin, verify suspend / resume succeeds for 10 cycles.
Change-Id: I5b6240a570472e1ea74de6e5f2341472ea7afe6b
Reviewed-on: https://chromium-review.googlesource.com/374524
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Allow the host to self-report its sleep state through
EC_CMD_HOST_SLEEP_EVENT, which will typically be sent with SUSPEND
param when the host begins its sleep process. While the host has
self-reported that it is in SUSPEND, don't assert the interrupt
line, except for designated wake events.
BUG=chrome-os-partner:56156
BRANCH=None
TEST=On kevin, run 'ectool hostsleepstate suspend', verify that
interrupt assertion is skipped for battery host event. Run 'ectool
hostsleepstate resume' and verify interrupt is again asserted by the
battery host event.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74288465587ccf7185cec717f7c1810602361b8c
Reviewed-on: https://chromium-review.googlesource.com/368391
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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this is to move the existing code from chipset level to board level
since PseudoG3 is a board feature that required specific hardware.
BUG=none
BRANCH=glados
TEST=use hibernate command to enter PseudoG3
Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/327677
Reviewed-by: Shawn N <shawnn@chromium.org>
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gcc 5.2 bails out on an inline declaration that isn't followed up with
a definition in the same compilation unit.
BRANCH=none
BUG=chrome-os-partner:49517
TEST=compile tested with coreboot's toolchain. samus, oak and others
that failed now build.
Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/324970
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
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On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep
and EC is eligable to enter heavy sleep idle task.
Wakeup from S0ix by lid open, any key press, power button or track pad
will be done by PCH block by asserting SLP_S0.
At S0ix, 1 msec pulse will be generated every 8sec and this signal
should be ignored since this is NOT S0ix entry/exit related and defered
interrupt for SLP_S0 were added.
BRANCH=master
BUG=none
TEST=in OS shell, run following commands.
Following command is valid with coreboot with S0ix patches.
"echo freeze > /sys/power/state"
then,
Measure EC power consumption and compare it with one in S0.
And on EC console, there should be NO periodic message, "power
state 4 = S0ix, in 0x001d" every 8 sec.
Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/307947
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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BUG=none
TEST=Tested on DVT 1.1, verified V3p3A is off in Pseudo G3
BRANCH=none
Change-Id: Id73b42d9f2e49239e82fad7931bbcc63e36a2c0b
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283602
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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In the gpio_info struct, we had a irq_handler pointer defined even
though a majority of the GPIOs did not have irq handlers associated. By
removing the irq_handler pointer out of the struct, we can save some
space with some targets saving more than others. (For example, ~260
bytes for samus_pd).
This change also brings about a new define:
GPIO_INT(name, port, pin, flags, signal)
And the existing GPIO macro has had the signal parameter removed since
they were just NULL.
GPIO(name, port, pin, flags)
In each of the gpio.inc files, all the GPIOs with irq handlers must be
defined at the top of the file. This is because their enum values from
gpio_signal are used as the index to the gpio_irq_handlers table.
BUG=chromium:471331
BRANCH=none
TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power
button, keyboard, charging, all still working.
TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build
fail.
TEST=make -j BOARD=peppy tests
TEST=make -j BOARD=auron tests
TEST=make -j BOARD=link tests
Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/263973
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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We don't have available GPIO pin for power button as the hibernate
(stand-by) wake-up source. Also, we don't want to do board change.
So, put the EC in a decent infinite loop to pretend the hibernate mode
and wait for particular wake-up event. This should be fine because
the AP is already down before EC hibernates.
BUG=chrome-os-partner:25435
BRANCH=Nyan
TEST=see comment #6 of issue for detailed test steps.
Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186061
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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For the better naming for power/common.h, we rename CONFIG_CHIPSET_X86
to CONFIG_POWER_COMMON (no one is actually using it). But keep
CONFIG_CHIPSER_TEGRA for power/build.mk.
BUG=chrome-os-partner:25068
BRANCH=nyan,falco,link,peppy,rambi,samus,squawks
TEST=build only
Change-Id: Ibf1a4c24088dfddac39b38a95b3b887c195152d5
Signed-off-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182732
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Integrate with power/common.c -- a real state machine now. Also remove
duplicate and unused functions/consts.
BUG=chrome-os-partner:24831
BRANCH=nyan
TEST=on nyan rev 3.12.
re-plug AC: PASS, power on 2
reboot: PASS, power on 2
power off (S5), power on: PASS, power off 4, power on 5
power off (G3), power on: PASS, power off 4, power on 5
lid close / power off (S5)/ lid open: PASS, power on 3
lid close / power off (G3)/ lid open: PASS, power on 3
press power button and release: nothing happens after 15s.
button off (S5)/ on: PASS, power off 3, power on 4
button off (G3)/ on: PASS, power off 3, power on 4
power off (S5)/ button on: PASS, power off 4, power on 4
power off (G3)/ button on: PASS, power off 4, power on 4
button off (S5)/ power on: PASS, power off 3, power on 5
button off (G3)/ power on: PASS, power off 3, power on 4
button off (S5)/ lid open: PASS, power off 3, power on 3
button off (G3)/ lid open: PASS, power off 3, power on 3
is off, long press button (60s): power on 4, too long, shutdown, stay off
is on, long press button (60s): power off 3, stay off
apreset cold: entered to S5, power off 3, power on 5
apreset warm: power state is not changed, but reboots to BIOS.
Change-Id: Ie12fa4f79b6156f71f89155b2b01880914809c75
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182348
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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To __CROS_EC_POWER_H which should be done in CL 9867f83.
BUG=None
BRANCH=nyan
TEST=build only
Change-Id: Ic3c1011e127c035c681aeb0ee2023046595b926b
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182102
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Rename x86_* to power_signal_* and X86_* to POWER_*.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy,squawks,snow,spring,nyan
TEST=make -j buildall run_tests
Change-Id: Ifaa06391da5a483851ff56eca91fbf6d038dff0a
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181719
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Renaming file names is the first step. Please see issue tracker
for more details.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy
TEST=build all x86 boards.
make clean BOARD=link && make -j32 BOARD=link && \
make clean BOARD=falco && make -j32 BOARD=falco && \
make clean BOARD=samus && make -j32 BOARD=samus && \
make clean BOARD=rambi && make -j32 BOARD=rambi && \
make clean BOARD=peppy && make -j32 BOARD=peppy
Change-Id: I3a296a0c14f6bebefa858438b1320061ac71dd38
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181400
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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