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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Rename ESPI additional configs to match the name of base config
that selects ESPI as HOST_INTERFACE.
BUG=b:195416058
BRANCH=main
TEST=zmake testall && make buildall
Change-Id: I137449a1a58b1ea0d9794ebc0900e1b68413819d
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3291744
Reviewed-by: Sam Hurst <shurst@google.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: Ic15a2e06f57089f9140347fa44de147190c7c298
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3730387
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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Added base code for Meteorlake power sequencing. Implementation closely
follows Intel Icelake power sequencing as reference and modified the
logic based on Meteorlake Platform Development Guide.
BUG=b:223985632
BRANCH=none
TEST=Able to boot MTLRVP to S0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Change-Id: Ia551a1e226c648d9f23aff05ad3d44c3735a2495
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3516600
Reviewed-by: Keith Short <keithshort@chromium.org>
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In order to support hibernate (suspend to disk) on some systems, there
are normally two choices for hibernate's destination power state: shutdown
and S4. On most systems, shutdown is the logical choice for Chrome OS,
since the wake sources are the same, and device state is properly
saved/restored across an S5/G3 transition.
However on Brya devices with Intel Keylocker technology, there is an IWKey
(intermediate wrapping key) which software by design is not allowed to
read. Intel, being no stranger to the concept of hibernate, provisioned
support to save and restore this register in a platform area, while
still keeping its contents inaccessible to software. However,
architecturally they only guarantee this mechanism works down to S3/S4.
This means in order to preserve keylocker contents during hibernation,
shutdown is no longer an option. We must camp out in the architecturally
designated S4 state during hibernation on devices with Intel Keylocker.
The EC has long ignored this as a state since the OS doesn't support
entering it. This needs to change.
This patch introduces a POWER_S4 state. It's modeled after the S3 state,
but represents itself as a "chipset soft off" state, like S5. Now, on
Intel platforms, we (almost) always transition through S4 on our way up
and down. For example, where we would normally go G3->S5->S3->S0, we now
go G3->S5->S4->S3->S0. The "almost" refers to unusual error cases, where
if power signals are totally wonky we may go from S3 straight to S5.
The S3 <-> S5 state transitions also still exist because non-Intel
platforms transition directly without going through S4. This bit of
consistency was sacrificed to avoid retrofitting a bunch of ARM EC code
to transition though a completely phony state. The "almost" refers to
unusual error cases, where if power signals are totally wonky we may go
from S3 straight to S5.
The common Intel code used to look at SLP_S4 as a signal to transition
between S5 and S3. Now, we look at SLP_S4 as the signal to transition to
S4, and use the SLP_S5 signal to transition deeper, into S5. On
platforms with virtual wire support, we should have access to the
virtual SLP_S5 line already. On platforms that haven't explicitly set
the config for VW_SLP_S5, we merge SLP_S5 and SLP_S4 by making them the
same GPIO, so that the transition through S4 simply slides on through.
This effectively disables S4 residency, so we disallow advertising S4
residency to the AP unless CONFIG_HOSTCMD_ESPI_VW_SLP_S5 is also
enabled. We should then enable this on all new Intel platforms.
Signed-off-by: Evan Green <evgreen@chromium.org>
BRANCH=None
BUG=b:204947672
TEST=hiberman hibernate --test-keys on volteer
Change-Id: Icf4798fa517d40ad652a278bbea2051e4c9fb118
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3265286
Commit-Queue: Evan Green <evgreen@chromium.org>
Tested-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This provides support for the Intel Alder Lake SoC in conjunction with
the Silergy SLG4BD44540 power sequencer.
A new config option (CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540) is provided
to enable this setup.
This is intended to be used by brya and its variants. Other Alder Lake
boards that use the Ice Lake style power sequencing are not affected by
this new config option.
BRANCH=none
BUG=b:173575131,b:177275055,b:177277633
TEST=buildall passes
Change-Id: I74c36f06fc8ad26c163093753140a5ca242d75c7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2675309
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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This makes the headers visible to the Zephyr build.
BUG=b:173798264
BRANCH=none
TEST=buildall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I3b6d27c1234b3924ee8902a86eec5fdb2ccd9998
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2571897
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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