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* COIL: spi_nor: Rename spi_master to spi_controllerCaveh Jalali2021-06-031-5/+7
| | | | | | | | | | | | | | | This renames the spi_master struct member of spi_nor_device_t to spi_controller. BRANCH=none BUG=b:163885307 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I446de6e60fa1e4dfa1266dca04d851fbfb6c250b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932467 Reviewed-by: Harry Cutts <hcutts@chromium.org>
* Add the functions to read and write EAR.Pai Peng2019-07-171-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | EAR (extended address register) is used to access addresses above 16MiB when 3-byte address mode is used. These two functions allow to write to and read from EAR to set up what addresses to access in 3-byte mode. For example, for a 64MiB EEPROM: EAR value Addresses to access 0 0x0000000 - 0x0FFFFFF 1 0x1000000 - 0x1FFFFFF 2 0x2000000 - 0x2FFFFFF 3 0x3000000 - 0x3FFFFFF BUG=b:132252340 BRANCH=none TEST=manual Testing: 1. Writing to EAR returns successfully. 2. Writing different values to EAR, verify that accessing EERPOM in 3-byte mode is to the correct address, e.g., when EAR=2, accessing 0x0FFFFFF is actually to 0x2FFFFFF. Change-Id: I2a8bde7fc4b9069afc80a81042fb47359bffa015 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688150 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Pai Peng <paipeng@google.com> Commit-Queue: Pai Peng <paipeng@google.com>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common/spi_nor: Adds RDID and 64KiB erase supportNadim Taha2016-12-071-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modified the SPI NOR flash driver to implement and expose a read JEDEC ID command as well as support block (64KiB) erase operations. BUG=None BRANCH=None TEST=Built all targets. Tested on two different EEPROMs. Before: ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0x1940ef $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 4m0.440s user 0m6.674s sys 0m11.998s ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0xc21a20c2 $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 5m57.291s user 0m9.964s sys 0m18.363s ------------------------------------------- After: ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0x1940ef $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 1m33.176s user 0m2.327s sys 0m5.050s ------------------------------------------- $ ~/haven_updater$ ./read_jedec_ftdi [+] JEDEC_ID=0xc21a20c2 $ ~/haven_updater$ time ./chip_erase_ftdi [+] Success! real 2m41.923s user 0m4.191s sys 0m8.576s ------------------------------------------- Change-Id: Ic20372ca9966499977a52a700d6492d3f648d7b2 Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/416903 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driverEwout van Bekkum2016-01-281-0/+159
Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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