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* lucid: add support to detect BC1.2 suppliersMary Ruthven2016-02-262-0/+20
| | | | | | | | | | | | | | | | Use built-in USB periperal to detect BC1.2 suppliers and update the charge manager. BUG=chrome-os-partner:48658 BRANCH=None TEST=manual for lucid. Use a samus as the supplier, and insert the charger into Lucid. Verify that it identifies it as SDP. Use a wall charger and verify that Lucid identifies it as DCP. Change-Id: I7842e9f75874f727837df5bfc28690662caf821c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329236 Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Remove gpio_alt_funcs table from common headerAnton Staaf2016-02-222-34/+0
| | | | | | | | | | | | | | | | | | | | Now that the cr50 no longer uses this array to store its pinmux config we can move it out of the header file, removing it from the public interface for GPIO code. This allows us to start modifying this struct more easily. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I9b4ca8b678b102bb9b63ccffe23bf2dc87aeb44a Reviewed-on: https://chromium-review.googlesource.com/328824 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* kunimitsu: hibernate: enable PseudoG3 support at board levelKevin K Wong2016-02-182-10/+0
| | | | | | | | | | | | | | this is to move the existing code from chipset level to board level since PseudoG3 is a board feature that required specific hardware. BUG=none BRANCH=glados TEST=use hibernate command to enter PseudoG3 Change-Id: I309ef89e0ff7057ce46c634baa9791731a771984 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/327677 Reviewed-by: Shawn N <shawnn@chromium.org>
* config: it83xx: remove "CONFIG_IT83XX_PECI_WITH_INTERRUPT"Dino Li2016-02-171-3/+0
| | | | | | | | | | | | | | | | IT839x and the new series all support interrupt of PECI, so we remove it. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make -j buildall Change-Id: Ib126cb418a4ba5ef313ee93948bc2fbb96bc936d Reviewed-on: https://chromium-review.googlesource.com/327643 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: upgrade command extensionVadim Bendebury2016-02-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch suggests a firmware upgrade mechanism implemented through an extended TPM command. The firmware is transmitted in chunks, each chunk accompanied by its checksum (first 32 bits of SHA1) and the base address. The first chunk is of size zero and has the base address set to zero. When the first chunk is received, the command handler determines the destination flash space (A or B), erases it, and returns its base address to the caller, such that the firmware update agent can tell in which of the two spaces it should write the update. The ultimate verification happens after the device is reset - the integrity and authentity of the firmware upgrade is verified at that point, the new firmware will not be started unless it is properly signed. BRANCH=none BUG=chrome-os-partner:37754 TEST=with all patches applied it is possible to upgrade firmware in both spaces A and B. Change-Id: I6aedc587ec630d65ba81000496f372c9044959a0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327415 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* skylake: set and clear wake masks in S0 <-> S0ix transitionsArchana Patni2016-02-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the wake masks when the SMI is invoked. For S0ix, EC sets and clears the wake mask via this patch. These functions are directly invoked from the state machine transition states. During S0ix entry, the wake mask for lid open is enabled. During S0ix exit, the wake mask for lid open is cleared. All pending events are also cleared BRANCH=none BUG=chrome-os-partner:48834 TEST=test lidopen in S0ix Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f Reviewed-on: https://chromium-review.googlesource.com/320190 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: clock: Use full-speed 48MHz processor clock during EC bootShawn Nematbakhsh2016-02-091-0/+2
| | | | | | | | | | | | | | | | | | | EC boot / hash computing can be a bottleneck for system boot time. Reduce this bottleneck by running our processor at 48 MHz through boot, until vboot hashing of RW completes. BUG=chrome-os-partner:49583 TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and 'cbmem' delta between 'vboot select&load kernel' and 'finished EC verification' is reduced to ~250 ms (which includes sysjump time). BRANCH=glados Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/326792 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* CR50: Add initial elliptic curve crypto implementation.nagendra modadugu2016-02-081-0/+1
| | | | | | | | | | | | | | | | This change adds support for NIST-P256 curve operations. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=new tests under test/tpm2/ pass. Change-Id: I03a35ff3ab8af3c52282d882937880bfa2bdcd32 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/324540 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Add support for CONFIG_LOW_POWER_S0.Mulin Chao2016-02-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To get better power consumption in S0, we add FW support for CONFIG_LOW_POWER_S0. Before entering deep idle in S0, we must enable Host interrupt to wake up EC if it needs to service LPC bus. This version also add a new bit of sleep_mask (SLEEP_MASK_FAN) in system.h to prevent EC enter deep idle if fan's duty isn't zero. Normally, the freq of PWM fan is 25 kHz. It means we must select apb2 clock as the source clock of PWM fan. Or fan would stop when ec enters deep idle because of no PWM signal. In hwtimer.c, we reset the preload counter to maximum value in ITEI32's ISR since preload counter is changed by __hw_clock_source_set all the time. We also found there're no event set if it's deadline is over 32 bits but current source clock isn't. To prevent ec doesn't wake-up in deep-idle even if ITIM32 expires, FW set an event for ITIM32 after process_timers(). Modified sources: 1. wheatley/board.h: Add CONFIG_LOW_POWER_S0 definition. 2. clock.c: Enable Host interrupt for LPC. 3. clock.c: Disable LP_WK_CTL for better power consumption. 4. gpio.c: Add ISR for Host interrupt. 5. uart.c: Introduce bit 6 of USTAT to make sure transmitting is completed. 6. register.h: Add uart_clear_pending_wakeup function. 7. hwtimer.c: Fixed watchdog issue when ITIM32 is closed to overflow. 8. fan.c: Enable deep sleep if duty cycle is zero. 9. include/system.h: Add SLEEP_MASK_FAN for fan control loop. 10. core/cortex-m/task.c: Add "isb" to flash the garbage data in the instruction pipeline. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ibe3630d0d68cf3f32206adb2afa1b5958916a2be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/324651 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Fix signed vs unsigned typingShawn Nematbakhsh2016-02-031-1/+1
| | | | | | | | | | | | | | | | | | - ec_response_thermal_get_threshold.value is unsigned, so it can not be less than zero. - make power_button_wait_for_release() take a signed int, to match its existing usage. BUG=None TEST=`make buildall -j` BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie5748df3d9904d1e417adc38fee18f8cb3ce9750 Reviewed-on: https://chromium-review.googlesource.com/325840 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Enforce compilation without system headersStefan Reinauer2016-02-034-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces HOST_CPPFLAGS to be used for all objects being compiled with HOSTCC rather then the target compiler. Since glibc is not linked into the EC, no glibc include files should be included in the EC code base. Hence, create local definitions for clock_t and wchar_t that match what the glibc include would have done, and remove some unneeded includes. Due to very eager optimization, we have to give gcc a little notch to not kick out memset. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> BUG=chrome-os-partner:43025 BUG=chrome-os-partner:49517 BRANCH=none TEST=compile tested Change-Id: Idf3a2881fa8352756b0927b09c6a97473358f239 Reviewed-on: https://chromium-review.googlesource.com/322435 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* charger/Kunimitsu: Fix for boot from cut-off batteryVijay Hiremath2016-02-021-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery in cut-off mode wakes when voltage is applied to the PACK and takes approximately 2 to 3 seconds to initialize before capable of providing the power. Hence made the battery present status to BP_NO in case of cut-off mode. Once the battery is ready new status is updated as BP_YES. When the battery status changes from BP_NO to BP_YES, charger input current is set to board specific charger input current which is not sufficient to boot the AP hence the system reboots. To avoid this issue, added code to write charger manager negotiated current to charger input current when the battery status changes from BP_NO to BP_YES. BRANCH=none BUG=chrome-os-partner:49224 TEST=Manually tested on Kunimitsu. Used console command 'cutoff' to put the battery in cut-off mode. Inserted the adopter to wake the system, system doesn't reboot & the battery charges. Change-Id: Ia5a1457506b4bef0b3dd27993e4b60ae64c8f746 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/322430 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Don't declare functions inline that aren't always defined as suchPatrick Georgi2016-02-022-3/+3
| | | | | | | | | | | | | | | | | | gcc 5.2 bails out on an inline declaration that isn't followed up with a definition in the same compilation unit. BRANCH=none BUG=chrome-os-partner:49517 TEST=compile tested with coreboot's toolchain. samus, oak and others that failed now build. Change-Id: Ic9c28fc12c80e24ea0dbf85f35846fd6a0b56a2d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/324970 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* system: Add hibernate board-level callbackShawn Nematbakhsh2016-01-281-0/+7
| | | | | | | | | | | | | | | | | Allow boards to take action (such as entering a custom low-power hibernate-like state) before putting the chip into hibernate state. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual with subsequent commit on chell. Verify board-level hibernate callback is called when "hibernate" is run on EC console. Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324086 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Fixes the SFDP_BITFIELD() macro.Nadim Taha2016-01-291-1/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=<redacted> Change-Id: If6e2732a29e084417ba1d2f80732ac412028342a Signed-off-by: Nadim Taha <ntaha@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324622 Reviewed-by: Ewout van Bekkum <ewout@chromium.org>
* common: Adds a JEDEC SFDP v1.* based Serial NOR Flash driverEwout van Bekkum2016-01-282-0/+177
| | | | | | | | | | | | | | | | | | | | | Adds a JEDEC SFDP v1.* compatible Serial NOR Flash driver to control multiple Serial NOR Flash devices (NOR EEPROMs, etc.). The SFDP tables are used to discover parts' page sizes and capacities. This driver only supports parts with capacities under 4GiB. If the parts are larger than 16MiB, then the 0xB7 4-Byte addressing mode entry opcode and 0xE9 4-Byte addressing mode exit opcode are required. This driver also assumes that a 4KiB erase opcode of 0x20 is always available. BRANCH=none BUG=none TEST=Tested on cr51 with multiple EEPROMs with various SFDP revs Change-Id: I5c2b757267e23c4f22ac89c6d5048a54b04de0c3 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321922 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* common: Adds JEDEC SFDP v1.0 & v1.5 encoding and decodingEwout van Bekkum2016-01-281-0/+807
| | | | | | | | | | | | | | | Adds a header with JEDEC SFDP v1.0 (JESD216) & v1.5 (JESD216A) encoding and decoding support to enable a part agnostic Serial NOR Flash driver. BRANCH=none BUG=none TEST=Tested through the spi_nor driver Change-Id: I00b3f0434bfb8582aebad7cd0682445980b57773 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/321921 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* tcpc: add support for TCPC with integrated high-speed muxesVincent Palatin2016-01-272-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | The TCPCI specification defines ane optional register 18h 'CONFIG_STANDARD_OUTPUT' providing a standardized way of steering the high-speed muxes. Implement the feature as a usb_mux_driver, under the conditional flag CONFIG_USB_PD_TCPM_MUX. The USB PD port index should be set in the port_addr field of the 'usb_mux' structure. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:49605 TEST=run pdeval-stm32f072 connected to a Parade PS8751 board and test USB/DP muxing. Change-Id: I7e5f0b8ec70b1910b2cff9d106514baca8c899e5 Reviewed-on: https://chromium-review.googlesource.com/322956 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Remove gpio_get_level_reg functionAnton Staaf2016-01-271-12/+0
| | | | | | | | | | | | | | | | | | | | After talking with Simon Glass about this we concluded that this was an optimization that is not needed, as such, and since it is only used in one location and only available from one chip family I'm removing it. This further simplifies the GPIO API and removes more uses of port/mask pairs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a Reviewed-on: https://chromium-review.googlesource.com/323827 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Remove GPIO_TO_PORT_MASK_PAIRAnton Staaf2016-01-271-5/+0
| | | | | | | | | | | | | | | | | This macro is no longer used, removing it so that it doesn't get used as we work towards removing port/mask from the public GPIO API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ic924cd520689c0805a2784be5005dbecfe89f389 Reviewed-on: https://chromium-review.googlesource.com/323873 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: update ec2i moduleDino Li2016-01-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. The previous EC2I module does not meet section '7.17.5 EC2I Programming Guide'. We need to correct it to prevent conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps long wait states. NOTE: If EC is using EC2I internal bus to access PNPCFG registers while host accessing EC ram through H2RAM interface at the same time, the symptom will appear. 2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'. We don't allow the host access PNPCFG registers. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and there is no error code return. 2. To create a stress test for this change. - EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG registers per-10ms. - run ectool 'version' command per-100ms. Before the change was made, LPC will keep in long wait states immediately. After the change, we run the test of ectool 'version' command over 20000 times. Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da Reviewed-on: https://chromium-review.googlesource.com/323563 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: Add temporary secure storage for the host during bootDuncan Laurie2016-01-252-0/+52
| | | | | | | | | | | | | | | | | | | This adds a temporary secure storage interface for the EC to be able to store small amounts of data from the host that is locked until the chipset resets. This is used by pre-memory verified boot on x86 systems where we need to know which RW slot to boot and what the hash is to ensure that we can resume from S3 safely. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315222 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-253-0/+12
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: hibernate: Don't reconfigure all GPIOsShawn Nematbakhsh2016-01-252-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good idea: - INPUT / PULL_UP is not necessarially the lowest-power state (for example, if there is an onboard pull-down). - Most GPIOs should already be in lowest-power state when we're in S5. - For the few GPIOs that need to be in a different state for hibernate, we can use a board-level callback. In addition, remove mec1322 code related to restoring from hibernate state, since we always reset coming out of hibernate. BUG=chrome-os-partner:49608 BRANCH=glados, strago TEST=`hibernate` on chell console when in S5 and AC removed. Verify that EC power is roughly equivalent to low-power idle power. Attach Zinger, verify that device wakes and boots, and charges from charger. Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322937 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* skylake: Add support for asserting RTCRST if power sequencing failsDuncan Laurie2016-01-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pulse RTC reset to the PCH when power sequencing exit fails we need to watch for SLP_S4 to deassert and if it does not then assert RTCRST using a board specific method. This is attempted up to 5 times before giving up and staying in G3. On skylake the RSMRST passthru needs to be honored when the task is woken up, so while waiting call handle_rsmrst() if woken up early. This is needed because it is RSMRST that actually tells the PCH to try and wake. This is all wrapped in a config option and board specific method because not all boards have a GPIO to control RTCRST and if they do they may not all use the same method to assert it. BUG=chrome-os-partner:49564 BRANCH=glados TEST=manually tested on chell EVT: First, ensure board sequences properly if everything is OK for a normal boot. Next, modify handle_rsmrst() to not pass through the signal in order to simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST and power up again 5 times before giving up and staying in G3. Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322724 Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Simplify configurationAnton Staaf2016-01-201-18/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Previously there were only two uses of gpio_config_pins, one was gpio_config_module, which passed in GPIO_CONFIG_ALL_PORTS (the only place this is used), the other was the common I2C code when it needs to return the SDA and SCL lines to their alternate function after unwedging the bus. These uses are so different that it doesn't make much sense to keep a single API for them. This change adds a gpio_config_pin that is simpler to use as it just takes a gpio_signal enum to select the GPIO to configure and makes gpio_config_pins and GPIO_CONFIG_ALL_PORTS internal to gpio.c Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I92bfb0b520b0aa2165655b2ff5076e428c88631f Reviewed-on: https://chromium-review.googlesource.com/322437 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* GPIO: Add gpio_reset functionAnton Staaf2016-01-191-0/+11
| | | | | | | | | | | | | | | | | The gpio_reset function returns a GPIO to its initialy configured state. Using it removes a few more uses of gpio_list. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie24e8e8a96d0ff50f521a918e80ed2b379f8c1a9 Reviewed-on: https://chromium-review.googlesource.com/321951 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Initial RSA implementation.stabilize-7821.Bnagendra modadugu2016-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | Includes support for encrypt / decrypt, and sign / verify; padding schemes OAEP / PKCS1; supporting bignum library. RSA key sizes must be a multiple of 32-bits (with the top bit set). Keying material, input and output buffers are required to be word-aligned. BRANCH=none TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested BUG=chrome-os-partner:43025,chrome-os-partner:47524 Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/316942 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* charger: Change unlocked battery level ignore conditionsShawn Nematbakhsh2016-01-062-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | x86 systems will auto-power-on when power is applied to the EC. When the battery level is critically low, power-on is prevented, except when the system is unlocked. So, when unlocked, some systems will auto-power-on regardless of battery level, overcurrent the charger / battery, and then repeat forever. Prevent this reboot loop by ignoring auto-power-up when the battery is critically low, regardless of system unlocked status. BUG=chrome-os-partner:48339 TEST=Verify power-up is prevented on no-battery chell w/ donette. Then, run 'powerbtn' on EC console and verify system powers on (and overcurrents). BRANCH=None Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319187 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* lucid: add LED supportMary Ruthven2015-12-221-0/+7
| | | | | | | | | | | | | | | Implement LED control for lucid with red, blue, and green LEDs. BUG=chrome-os-partner:48661 BRANCH=none TEST=make sure lucid builds Change-Id: I97ed56daa8fdb40daf8ab06e53913dcff2e41dea Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/319224 Commit-Ready: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Move rand_bytes implementation from tpm2 to chip/g.nagendra modadugu2015-12-221-0/+9
| | | | | | | | | | | | | BRANCH=none TEST=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: Ic7a850fdf2594ac1981237edda8dceb16cc7cbe6 Reviewed-on: https://chromium-review.googlesource.com/319155 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: adc: Add support for DMA continuous modeShawn Nematbakhsh2015-12-212-2/+16
| | | | | | | | | | | | | | | | | | | Add support for continuously writing ADC samples to a circular buffer. CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an appropriate sized buffer must be passed to adc_read_all_channels(). BUG=chromium:569994 TEST=Manual on snoball. Verify 'adc' continues to function (single mode). With pending commit, verify that continuous conversion interrupt is called at appropriate frequency and values look consistent. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e Reviewed-on: https://chromium-review.googlesource.com/318505 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: adds the SPI master driverEwout van Bekkum2015-12-212-1/+5
| | | | | | | | | | | | | | | | | Adds the SPI master driver with support for both SPI masters with support for using GPIOs as chip selects or using the hardware's dedicated chip selects. Note this has not been enabled in the cr50 board. BRANCH=none BUG=none TEST=verified through use of the SPI_FLASH module on cr51 Change-Id: I88719f8d03e217ab44249172b1340011fdcfdad5 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317329 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: Include host/console commands based on HAS_TASK_HOSTCMD/CONSOLEShawn Nematbakhsh2015-12-182-1/+10
| | | | | | | | | | | | | | | | | | | | | Don't build a table of host / console commands if the HOSTCMD or CONSOLE task is not present. This saves space in the .hcmds / .cmds section and allows the linker to prune command handler functions which will never be called. BUG=chrome-os-partner:41959 TEST=Verify ec.RO.flat shrinks on snoball and glados_pd, and remains the same size on chell and samus. Also verify basic functions are still working on snoball and glados_pd. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I79975c18ec1d87fedda8d1f299f30ffc43c24f69 Reviewed-on: https://chromium-review.googlesource.com/319112 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cr50: add ability to include two identical RW sections in the EC imageVadim Bendebury2015-12-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical EC image includes two similar in their functionality subsections, RO and RW. CR50 has a small RO subsection, all it does - detects a proper RW image to run and starts it up. To provide for reliable firmware updates, the CR50 image needs to include two RW sections, while the code is running from one RW subsection, the other one can be upgraded. This patch adds the ability to generate two identical RW sections, mapped half flash size apart, and include them into the resulting EC image. To keep things simple the previously existing RW section's name is not being changed, while the new (identical) RW section is named RW_B. Two configuration options need to be defined to enable building of the new image type: CONFIG_RW_B to enable the feature and CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the flash. A new rule added to Makefile.rules allows to generate a different lds file from the same source (core/cortex-m/ec.lds.S) by defining a compile time variable to pick a different base address for the rewritable section, when RW_B is built. BRANCH=none BUG=chromium:43025 TEST=as follows: - make buildall -j still succeeds - verified that regular CR50 image starts successfully - modified chip/g/loader/main.c to launch RW_B first, re-built and re-run the image, observed on the console: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv cr50 bootloader, 20151118_11218@80881, no USB, full crypto Valid image found at 0x00084000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com] [0.001148 Inits done] This FPGA image has no USB support Console is enabled; type HELP for help. > [0.002212 task 2 waiting for events...] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (note that the image base address is 0x840000, which is RW_B). Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316703 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: pwm: Allow configuration of pwm frequency + complementary outputsShawn Nematbakhsh2015-12-041-3/+8
| | | | | | | | | | | | | | | | | | | Allow boards to customize both the PWM frequency / period and the enabling of complementary output signals. BUG=chrome-os-partner:48044 TEST=Manual with snoball w/ subsequent commit. Run `pwm <ch> 50` for each channel, verify with `adc` that each PD output voltage is approximately VBUCK / 2. BRANCH=None Change-Id: I61cbb4a5b656f41ec7cec59339f5247902256295 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315141 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pwm: Add common initialization for PWM pinsShawn Nematbakhsh2015-12-041-9/+7
| | | | | | | | | | | | | | | | | | | Rather than having various PWM module groups initialized from various HOOK_INIT functions, group them all into a single module and initialize them all from a common function in pwm.c. BUG=chromium:563708 TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that samus fan + KB backlight control is functional and samus_pd correctly sets PWM output. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941 Reviewed-on: https://chromium-review.googlesource.com/314882 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cr50: add extension command for testing hash primitivesVadim Bendebury2015-12-031-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new extended subcommand code (1) is being added to handle hash testing. The new subcommand handler keeps track of multiple sha1 and sha256 contexts the host might want to exercise. The number of available contexts is limited by the amount of available free memory. One of four hash operations could be requested by the host: 'Start', 'Continue', 'Finish' - when hashing a single stream over multiple extended command messages, and 'Single' when the entire message to be hashed is included in one extended command payload. The command payload had the following format: * field | size | note * =================================================================== * mode | 1 | 0 - start, 1 - cont., 2 - finish, 3 - single * hash_mode | 1 | 0 - sha1, 1 - sha256 * handle | 1 | seassion handle, ignored in 'single' mode * text_len | 2 | size of the text to process, big endian * text | text_len | text to hash As soon as the first 'Start' message is encountered, the handler tries to allocate shared memory to keep track of the test contexts, the amount of available memory determines how many contexts the handler can support concurrently. As soon as the last 'Finish' command is encountered, the handler returns the shared memory to the 'heap'. BRANCH=none BUG=chrome-os-partner:43025 TEST=after adding the host side implementation and fixing a couple of bugs, hash tests pass (see upcoming patches). Change-Id: Iae18552d6220d670d1c6f32294f0af1a8d0d5c90 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314692 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: reduce hash implementation stack requirementsVadim Bendebury2015-12-031-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stack space is pretty tight on cr50, and since there is no need to support SHA digest sizes in excess of 256 bits, the digest buffer size should be reduced. This patch makes the maximum expected digest size dependent on the set of configured hash algorithms, moves hash size related asserts from run time to compile time, and passes compile time definition to the TPM2 library to increase its hash state container (it became too small when SHA384 was disabled). The sw context requirements should be reduced, but this is a task for another day. We also do not have to store a local digest copy if the API allowed reading a partial digest. CQ-DEPEND=CL:314883 BRANCH=none BUG=chrome-os-partner:43025, chromium:564862 TEST=all tests pass: $ ./test/tpm_test/tpmtest.py Starting MPSSE at 800 kHz Connected to device vid:did:rid of 1ae0:0028:00 SUCCESS: AES:ECB common SUCCESS: AES:ECB128 1 SUCCESS: AES:ECB192 1 SUCCESS: AES:ECB256 1 SUCCESS: AES:ECB256 2 SUCCESS: AES:CTR128I 1 SUCCESS: AES:CTR256I 1 SUCCESS: sha1:single 0 SUCCESS: sha256:single 0 /New max timeout: 1 s SUCCESS: sha256:finish 1 SUCCESS: sha1:finish 3 SUCCESS: sha256:finish 2 Change-Id: Iaef3a230469de129e72418814e1d113b447c0137 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314695 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* usb: Put HID descriptor in the correct orderBill Richardson2015-12-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the "Device Class Definition for Human Interface Devices" spec: When a Get_Descriptor(Configuration) request is issued, it returns the Configuration descriptor, all Interface descriptors, all Endpoint descriptors, and the HID descriptor for each interface. It shall not return the String descriptor, HID Report descriptor or any of the optional HID class descriptors. The HID descriptor shall be interleaved between the Interface and Endpoint descriptors for HID Interfaces. That is, the order shall be: Configuration descriptor Interface descriptor (specifying HID Class) HID descriptor (associated with above Interface) Endpoint descriptor (for HID Interrupt In Endpoint) Optional Endpoint descriptor (for HID Interrupt Out Endpoint) This makes that happen. BUG=chrome-os-partner:34893 BRANCH=none TEST=manual "make buildall" works, this image seems to work on the Cr50. Also, before this CL, I see this: 0x00060f5c 0x00000000 .rodata g NOTYPE __usb_desc 0x00060f5c 0x00000009 .rodata g OBJECT usb_desc_conf 0x00060f65 0x00000009 .rodata g OBJECT usb_desc_iface0_0iface 0x00060f6e 0x00000007 .rodata g OBJECT usb_desc_iface0_1ep0 0x00060f75 0x00000007 .rodata g OBJECT usb_desc_iface0_1ep1 0x00060f7c 0x00000009 .rodata g OBJECT usb_desc_iface1_0iface 0x00060f85 0x00000007 .rodata g OBJECT usb_desc_iface1_1ep81 0x00060f8c 0x00000009 .rodata g OBJECT usb_desc_iface1_2hid 0x00060f95 0x00000000 .rodata g NOTYPE __usb_desc_end and after, this: 0x00060f5c 0x00000000 .rodata g NOTYPE __usb_desc 0x00060f5c 0x00000009 .rodata g OBJECT usb_desc_conf 0x00060f65 0x00000009 .rodata g OBJECT usb_desc_iface0_0iface 0x00060f6e 0x00000007 .rodata g OBJECT usb_desc_iface0_2ep0 0x00060f75 0x00000007 .rodata g OBJECT usb_desc_iface0_2ep1 0x00060f7c 0x00000009 .rodata g OBJECT usb_desc_iface1_0iface 0x00060f85 0x00000009 .rodata g OBJECT usb_desc_iface1_1hid 0x00060f8e 0x00000007 .rodata g OBJECT usb_desc_iface1_2ep81 0x00060f95 0x00000000 .rodata g NOTYPE __usb_desc_end The HID descriptor comes before the endpoint. Change-Id: I8035a4cc884d8bb900bc1eb25fd3e4e9aba05bf8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314832 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ectool: provide lid angle infoKevin K Wong2015-11-252-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | Added new host command to support returning lid angle. New output from ectool: System with lid angle support: ------------------------------------------ localhost ~ # ectool motionsense lid_angle Lid angle: 72 System without lid angle support: ------------------------------------------ localhost ~ # ectool motionsense lid_angle EC result 3 (INVALID_PARAM) BUG=none BRANCH=none TEST=run "ectool motionsense lid_angle" verify the value matches the physical lid angle position Change-Id: I4179172c778f643640561e819216f7adfee679d2 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/313345 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Add support for multiple distinct TCPC alert signalsShawn Nematbakhsh2015-11-251-0/+8
| | | | | | | | | | | | | | | | | | | | | If multiple TCPCs are present on a system then we may have multiple alert signals, each of which alerts us to the status of a different TCPC. Make boards with external non cros-ec TCPCs define tcpc_get_alert_status, which returns alert status based upon any alert GPIOs present, and then service only ports which are alerting. BUG=chromium:551683,chrome-os-partner:47851 TEST=Verify snoball PDCMD task sleeps appropriately when no devices are inserted, and verify ports go to PD_DISCOVERY state when we attach samus. Also verify that glados / glados_pd can still negotiate PD. BRANCH=None Change-Id: Iae6c4e1ef4d6685cb5bf7feef713505925a07c8c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313209 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cr50: SHA1 and SHA256 implementation with hardware supportnagendra modadugu2015-11-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | This change includes hardware and software support for SHA1/256 on CR50. When running in the RO image, only hardware sha256 support is included. When running in the RW image, the code auto-selects between the software and hardware implementation. Software implementation path is taken if the hardware is currently in use by some other context. Refactor the CR50 loader to use this abstraction. The existing software implementation for SHA1 and SHA256 is used for the software path. CQ-DEPEND=CL:*239385 BRANCH=none TEST=EC shell boots fine (implies that SHA256 works) BUG=chrome-os-partner:43025 Change-Id: I7bcefc12fcef869dac2e48793bd0cb5ce8e80d5b Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313011
* usb_mux: Add a callback for board specific initDuncan Laurie2015-11-241-0/+9
| | | | | | | | | | | | | | | This adds a callback for board specific initialization that is called after the driver init function. This will allow a board to apply port-specific tuning (such as USB EQ settings) to the mux chip. BUG=chrome-os-partner:47074 BRANCH=none TEST=build and boot on chell Change-Id: Ib162f9a2c5239678c46b80e5517823b336f6b66c Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313746 Reviewed-by: Shawn N <shawnn@chromium.org>
* Kunimitsu: Add S0ix on SLP_S0 assertionKyoung Kim2015-11-193-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On assertion of SLP_S0, EC goes to S0ix while system is in Lucid sleep and EC is eligable to enter heavy sleep idle task. Wakeup from S0ix by lid open, any key press, power button or track pad will be done by PCH block by asserting SLP_S0. At S0ix, 1 msec pulse will be generated every 8sec and this signal should be ignored since this is NOT S0ix entry/exit related and defered interrupt for SLP_S0 were added. BRANCH=master BUG=none TEST=in OS shell, run following commands. Following command is valid with coreboot with S0ix patches. "echo freeze > /sys/power/state" then, Measure EC power consumption and compare it with one in S0. And on EC console, there should be NO periodic message, "power state 4 = S0ix, in 0x001d" every 8 sec. Change-Id: Ia9cf5256b1ad7234815d4b6dbe2b45788aaf49dd Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/307947 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion: improve readability by adding units to variable names.Gwendal Grignou2015-11-191-1/+1
| | | | | | | | | | | | | | | Throughout the code, there are comparison between frequency (in mHz) and period (in us). To improve readability, append units (_mhz, _us) after variable names. BRANCH=smaug BUG=none TEST=compile. Change-Id: Icc9c66d9f06c526fc3b74fd85ca9759b702ee416 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313221 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* motion: wake up main task for all changes in EC parameter.Gwendal Grignou2015-11-191-1/+3
| | | | | | | | | | | | | | | | | We need to wake up the main task, even if we disable a sensor. It will force sending the sensors samples in the FIFO and put a timestamp behind them. Also, reduce the interrupt period by 10us to be sure we fire interrupt to the AP even if there are some variation in the timing calculation. BUG=b:24367625 BRANCH=smaug TEST=Run ts.SingleSensorTests overnight. Change-Id: I6d966d52b5cbb72ba5eb936bc2fad6c06c7d8605 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312986 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* power: Add power signal interrupt storm detectionShawn Nematbakhsh2015-11-191-0/+7
| | | | | | | | | | | | | | | | Power signal interrupt storms are difficult to detect without extensive debugging, so add a config option to help detect them in SW. BUG=chromium:557988 BRANCH=None TEST=None Change-Id: I590ac8883e7615d05fd326245abade212b79e297 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313170 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* motion: Change units of ec_rate from us to ms.Gwendal Grignou2015-11-181-4/+4
| | | | | | | | | | | | | To ease finer calculation of ec rate change units from ms to us. BRANCH=smaug BUG=b:24367625 TEST=compile Change-Id: I52057c8ca1b1180a64b58d1ba0af9ec53f40b026 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312984
* add command multiplexer to the TPM driverVadim Bendebury2015-11-181-0/+1
| | | | | | | | | | | | | | | | | | | | This code allows to send extension commands over TPM protocol, no callbacks have been registered yet. The same buffer is used as input and output data. The header is stripped off before the callback is called and then re-added after processing. This could be used for testing, for proprietary firmware update protocol, etc. BRANCH=none BUG=chrome-os-partner:47524 TEST=none yet Change-Id: I91f692cc6e20abe774ee4ef001be28e5af102b2a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/312587
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