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* rose: add stm32f4 SPI master supportRong Chang2017-04-261-0/+3
| | | | | | | | | | | | | | | | This change adds stm32f4 stream DMA support and a config option to use first SPI port as master. BUG=chromium:688979 TEST=build and load on stm32f4 dev board BRANCH=none Change-Id: I2b504be70e0fbb17f16ce070119ae4715c88333a Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438911 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig/update_fw: Prevent race in rollback protectionNicolas Boichat2017-04-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a window where the rollback information in RW could potentially be updated during RW signature verification. We make sure this cannot happen by: - Preventing update over USB while RWSIG is running - When system is locked, only update rollback information if RW region is locked: this guarantees that RW cannot be modified from boot until RW is validated, and then until rollback information is updated. Also, remove rollback_lock() in rwsig_check_signature: rwsig_jump_now() protects all flash, which also protects rollback. This reduces the number of required reboots on rollback update. BRANCH=none BUG=b:35586219 BUG=b:35587171 TEST=Add long delay in rwsig_check_signature, make sure EC cannot be updated while verification is in progress. Change-Id: I7a51fad8a64b7e258b3a7e15d75b3dab64ce1c94 Reviewed-on: https://chromium-review.googlesource.com/479176 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/usb_update: add support for extra commandsNicolas Boichat2017-04-261-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 4 extra commands that are required to update hammer: - UPDATE_EXTRA_CMD_IMMEDIATE_RESET - UPDATE_EXTRA_CMD_JUMP_TO_RW: Tells the RWSIG task to jump to RW as soon as possible (assuming the image verifies) - UPDATE_EXTRA_CMD_STAY_IN_RO: Tells the RWSIG task to not jump to RW, and stay in RO, to leave enough time for AP to update RW. - UPDATE_EXTRA_CMD_UNLOCK_RW: Tells EC to unlock the RW section so that it can be updated (on next reboot). BRANCH=none BUG=b:35587171 TEST=Test RO+RW update cd extra/usb_updater; make # Jump to RW sudo ./usb_updater2 -j sleep 0.5 # Update RO, then reboot sudo ./usb_updater2 ../../build/hammer/ec.bin sleep 0.5 # Update RW (first tell RO to not jump to RW) sudo ./usb_updater2 -s sudo ./usb_updater2 ../../build/hammer/ec.bin TEST=Test RW update only, with RO protected On EC console: flashwp true; reboot cd extra/usb_updater; make # Tell RW to unprotect RW and jump back to RO sudo ./usb_updater2 -w sudo ./usb_updater2 -r sleep 0.5 # Update RW, then reboot sudo ./usb_updater2 -s sudo ./usb_updater2 ../../build/hammer/ec.bin Change-Id: I5e8df7bdb4f06f2ac7b47de53dcde69c5002f578 Reviewed-on: https://chromium-review.googlesource.com/458470 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Include stdint.h from ec_commands.h.Carl Hamilton2017-04-251-3/+5
| | | | | | | | | | | | | | | | | | | The ec_commands.h header uses types defined in stdint.h. To make the ec_commands.h header more portable, ensure that includes what it uses. Running "make -j buildall" worked for all boards except "gru" and "hammer", which were broken before this change. BRANCH=none BUG=none TEST=make -j buildall Change-Id: I1ffe41a69b7296736616b9250c45f2749a66f22c Reviewed-on: https://chromium-review.googlesource.com/483283 Commit-Ready: Carl Hamilton <carlh@chromium.org> Tested-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Makefile: Allow different task list for RO and RWNicolas Boichat2017-04-252-14/+50
| | | | | | | | | | | | | | | | | | | | | | | This adds new macros for tasks (_RO and _RW), which allows to enable a task only for RO or RW section. We also create a new task_filter.h include file, that helps pre-filter those tasks, and can be used either from Makefile, or included from task_id.h. BRANCH=none BUG=b:35582031 TEST=make buildall -j; make savesizes Apply this CL make buildall -j; make newsizes => No size change Change-Id: I472bc6d4ab250a0a0e1fa6aeb4b748ba6968bedf Reviewed-on: https://chromium-review.googlesource.com/479491 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nick Sanders <nsanders@google.com>
* npcx: gpio: Add support for npcx7 series ec.Mulin Chao2017-04-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add gpio_chip-npcx5/7.h files and move all macro functions related to chip family to them. (Move wui macro func from gpio_wui.h to them.) 2. Replace alternative and low-voltage mapping table with macro function NPCX_ALT_TABLE and NPCX_LVOL_TABLE. 3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR. 4. Add gpio register definitions of npcx7 family in registers.h. 5. Add GPIO_LOCKED flag for lock functionality. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Passed validation for all GPIO functionalities on npcx5m6g and npcx796f evb. Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481561 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/update_fw: Board/chip-specific first_response_pduNicolas Boichat2017-04-211-12/+50
| | | | | | | | | | | | | | | | | | | | | | | | | cr50 and hammer/common code are such different chips that reusing the same first_response_pdu does not make much sense. Instead, we can use 2 different headers, the updater knows which response to expect based on USB product ID. In the common code answer, we can reply with the EC version string, as well as rollback information and key version ID, which will be required for reliable updating. BRANCH=none BUG=b:35587171 BUG=b:36375666 TEST=usb_updater2 can update hammer, and read its version, rollback version and key version. Change-Id: I20b04070606767c71df3e6286d53e238e13375c0 Reviewed-on: https://chromium-review.googlesource.com/476452 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-211-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* USB: Remove usb_charge_ports_enabledDaisuke Nojiri2017-04-201-8/+0
| | | | | | | | | | | | | usb_charge_ports_enabled is not used. BUG=none BRANCH=none TEST=make buildall Change-Id: I9465b65e9fab2603a4258adc4ae5f16d6bfc93c4 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/481076 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/usb_update: Statically allocate update bufferNicolas Boichat2017-04-172-8/+3
| | | | | | | | | | | | | | | | This makes error handling simpler, and also guarantees at compile time that EC will be able to allocate that much memory. BRANCH=none BUG=b:35587171 TEST=Update hammer using usb_updater2 Change-Id: Ifd4c5da80e98ee93b558679ab1cac8d5d89512e3 Reviewed-on: https://chromium-review.googlesource.com/479175 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* power_button_x86: Fix power button pulse enabling/disablingFurquan Shaikh2017-04-171-2/+2
| | | | | | | | | | | | | BUG=b:37277943 BRANCH=None TEST=Verified that wake from power button works in S3. Also, verified that menu selection works fine with this change. Change-Id: I8e644af3fb7fbc0147f1acb12b6df945815b5e73 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/475974 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/update_fw: Remove board-specific rw_sectionsNicolas Boichat2017-04-151-19/+0
| | | | | | | | | | | | | | | | | | | | | | rw_sections is defined in the exact same way on all common code boards, let's remove it, and hard-code the values in update_fw.c instead. Take this as an opportunity to fold set_valid_section in fw_update_start (this will be useful later on, as we also want to return the inactive region version). BRANCH=none BUG=b:35587171 TEST=make buildall -j TEST=Can update hammer over USB using usb_updater2 Change-Id: I4dd3224f17f89c1851c379255f1195dc54528b3d Reviewed-on: https://chromium-review.googlesource.com/476451 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common/update: Update common code updater to latest chip/g versionNicolas Boichat2017-04-151-5/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's move to protocol version 6, which provides most of the new features we want to update generic EC firmware. Note that this matches chip/g version as of commit 0e5497db6, plus the following uncommited chip/g patches (CL:458364): c73af7dd2 chip/g/upgrade: Clarify pdu/frame terminology baea0a8c7 chip/g/upgrade: Rename SIGNED_TRANSFER_SIZE to UPDATE_PDU_SIZE d6e41b75c chip/g/upgrade: Remove cr50-specific upgrade subclass and protocol 3dc0b9a25 chip/g/upgrade: Rename upgrade to update 13436f9b9 chip/g/upgrade: Split rdpu initialization to a separate function fab9a0936 chip/g/upgrade: Minor formatting fixups 8161ef7c0 chip/g/upgrade: Fix valid_transfer_start logic bd6d79434 chip/g/upgrade: Fix logic for short USB packets within frames b09e252ed chip/g/upgrade: Improve error handling Then: diff -u include/update_fw.h chip/g/upgrade_fw.h diff -u common/usb_update.c chip/g/usb_upgrade.c diff -u common/update_fw.c chip/g/upgrade_fw.c Only shows chip/g specific differences. BRANCH=none BUG=b:36375666 BUG=b:35587171 TEST=make buildall -j TEST=Can update hammer over USB using usb_updater2 Change-Id: I5b0f0281d844972dab572955d5495f808127e523 Reviewed-on: https://chromium-review.googlesource.com/458321 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* system: Shutdown AP before entering hibernate modePhilip Chen2017-04-141-0/+6
| | | | | | | | | | | | | | BUG=chromium:702451 BRANCH=none TEST=manually test on gru: confirm 'Alt+VolUp+h' puts gru in hibernate mode and AC plug-in wakes it up. Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 Reviewed-on: https://chromium-review.googlesource.com/470787 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kahlee: Modify PD port2 I2C address and clean up unused functionCloud_Lin2017-04-111-3/+0
| | | | | | | | | | | | | | | 1. PD vender suggests to use chip default address setting (0x16). 2. Clean up board_print_tcpc_fw version function and related define. BRANCH=None BUG=None TEST=Plug in type-c device and check behavior Change-Id: I44b7156c914b8de67630696e4534147cc3b7f2c3 Reviewed-on: https://chromium-review.googlesource.com/469449 Commit-Ready: Lin Cloud <cloud_lin@compal.com> Tested-by: Lin Cloud <cloud_lin@compal.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig: Make it possible to run as a taskNicolas Boichat2017-04-112-2/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Optionally) split rwsig verification into a separate task. This allows us to initialize other components (e.g. USB) while the verification is in progress, speeding up the boot process to active USB in RO case. After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section if no action is taken by the AP (such as a forced request to jump to RW, or starting an update). Note: This comes with a ~36ms boot time regression, as other code gets to run before verification starts. BRANCH=none BUG=b:35587171 TEST=Flash, board boots to RW after 1s TEST=Change jump timeout to 5s, add 5s delay in check_signature, add console command to manually abort/continue rwsig verification. 'rwsig continue' works => Board jumps to RW after check_signature is completed (or immediately while waiting for timeout) 'rwsig abort' works => Board does not jump to RW. Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef Reviewed-on: https://chromium-review.googlesource.com/468709 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-112-61/+78
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rollback: Update and lock rollback block as part of rwsig verificationNicolas Boichat2017-04-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done at RO stage. If the rollback region is unprotected, update it to match the version in the RW image. If the rollback region is protected, we can't do that update, so we wait for RW to unlock that region (presumably after AP has verified that image is somewhat functional) before updating it. BRANCH=none BUG=b:35586219 TEST=flashwp true; reboot => hammer reboots twice flashinfo shows RO+rollback protected: Flags: wp_gpio_asserted ro_at_boot ro_now rollback_at_boot rollback_now Protected now: YYYYYYYY YYYYYYYY Y....... ........ TEST=Hack version.c to add "+1" to rollback_version, check that RO updates ROLLBACK info block on first boot. TEST=Use hack above, convert rwsig to separate task, add 5000 ms delay in rwsig just before rollback information is updated. Then: Quickly type: flashwp true; reboot; flashwp all; reboot => Wait for system to jump to RW rollbackinfo => minimum version 0 flashwp norb; reboot; wait for jump to RW rollbackinfo => minimum version 1 Change-Id: I78e502315c611c5edaf34b8d70a12fedd3e57bdf Reviewed-on: https://chromium-review.googlesource.com/452816 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Fixups in emulated sysrq codeNicolas Boichat2017-04-064-10/+16
| | | | | | | | | | | | | | | | Follow-up to CL:456520, addressing a few more comments. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I692afa7c911882f00d92b8e6d83889c52821e171 Reviewed-on: https://chromium-review.googlesource.com/468506 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-064-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kahlee: initial board settingJimmy Wang2017-04-051-0/+4
| | | | | | | | | | | | | | | | | | | | 1. GPIO initial 2. board config 3. led control 4. power control of Stoney 5. battery setting BRANCH=None BUG=None TEST=power on device and test manually Change-Id: I14cc60bf2cdd40032b3cbdfacf68d7a3c17fe87c Reviewed-on: https://chromium-review.googlesource.com/461624 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: Lin Cloud <cloud_lin@compal.com> Tested-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Danny Kuo <Danny_Kuo@compal.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add support for emulated sysrqNicolas Boichat2017-03-313-0/+16
| | | | | | | | | | | | | | | | | | | | On keyboard-less design, we will implement a special debug mode, based on button sequences, to transmit sysrq events to the AP. This implements the new MKBP event to send sysrq, and a console command to test it. Later CL will implement debug mode itself. BRANCH=none BUG=b:35775099 TEST=sysrq available in EC console TEST=sysrq h => help message in AP console TEST=sysrq b => AP reboots Change-Id: I71d3f77497baf8cc7fac65cd040ce20513b507bc Reviewed-on: https://chromium-review.googlesource.com/456520 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash: ensure proper pstate alignmentVincent Palatin2017-03-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The pstate structure is written using the low-level flash_physical_write() function. As a consequence, it is supposed to meet the CONFIG_FLASH_WRITE_SIZE alignment constraint. Add a build-time assertion to avoid silent failures. Slightly decrease the maximum size of the serial number string, so the structure has a natural 32-byte alignment which is compatible with a large number of platforms (including STM32L4 which requires 64-bit alignment). Of course, this change is not fully backward-compatible. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:571477 b:35648258 TEST=on STM32L442, build and run 'flashrom --wp-enable' without failure. Change-Id: Ia8f82790a61a6c7d2cf9bfeb95bfdaf7b8c52d11 Reviewed-on: https://chromium-review.googlesource.com/458201 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: Move pwm open-drain functionality from gpio to pwm driver.Mulin Chao2017-03-241-0/+4
| | | | | | | | | | | | | | | | Setting PWM IO type in gpio driver seems not a proper way. This CL moves this functionality to pwm driver and introduces a new flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it in board driver. BRANCH=none BUG=none TEST=test pwm functionality on npcx_evb. Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: add vendor command to restore corrupted headerVadim Bendebury2017-03-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The upcoming move of the Cr50 firmware update to the background requires postponing the activation of the newly uploaded Cr50 image to a later point in time, when the AP is ready to switch to start using the new Cr50 image. The suggested way of achieving it is as follows: when downloading the new image, the current Cr50 code modifies the header's 'image_size' field, setting its top bit to 1. This both makes the size invalid and guarantees that the new image would not verify on the following Cr50 restarts. When the AP is ready to switch to running the new Cr50 image, it will send a vendor command, which would trigger the currently running Cr50 image to restore the other image's size field. This vendor command would also communicate the timeout for the Cr50 to wait before rebooting, if there has been at least one header (ro or rw) restored. Rebooting the Cr50 would trigger rebooting the AP, resulting in the entire system running the updated firmware. Response sent to the AP will indicate if there has been a header restored and the reboot is indeed upcoming, this would allow the AP to quiesce the state of the device to handle the reboot gracefully. BRANCH=cr50 BUG=b:35580805 TEST=with the rest of the patches applied observed the system properly after the new header version was restored. Change-Id: Ia1edee67b6aa8f458810d5dc2931477cfaab1566 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/457676 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* tcpm: Call usb_mux board_init on exit from low power modeDaisuke Nojiri2017-03-162-2/+4
| | | | | | | | | | | | | | | | | PS8751 does not restore all register contents when resuming from low power mode. This change makes tcpm call board_init when it stops auto-toggling so that register contents can be restored. BUG=b:35585399 BRACH=none TEST=On Snappy, the board_init funciton is called every time a device is plugged in and register contents are restored. Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/454139 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb: Cleanup headersNicolas Boichat2017-03-161-3/+0
| | | | | | | | | | | | | | | | | | | Let's split the usb headers in 3 different parts, instead of having usb_descriptor.h pull in usb_hw.h and usb_api.h. - usb_api.h: EC functions related to usb (e.g. connect/disconnect) - usb_descriptor.h: common USB names and structures - usb_hw.h: Functions required for interactive with EC's USB HW BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e Reviewed-on: https://chromium-review.googlesource.com/454861 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add minimal fpc1140 driverVincent Palatin2017-03-162-0/+8
| | | | | | | | | | | | | | | | | | Add a basic driver for FPC1140 sensor similar to the kernel fpc1020 driver. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, run the FP sensor 'int_test' with the FP MCU pass-through. Change-Id: Ib042b890b5848f66cf6ab9284fd26e7b641f68c1 Reviewed-on: https://chromium-review.googlesource.com/454700 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* eve_fp: minimalistic fingerprint sensor passthroughVincent Palatin2017-03-161-0/+14
| | | | | | | | | | | | | | | | | | Simple hack to provide a pass-through relaying the fingerprint sensor commands coming from the host. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, read sensor HWID from the kernel. Change-Id: I04e7641fe4067f8378e0b798c529aded0f708b47 Reviewed-on: https://chromium-review.googlesource.com/452500 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* version: Store image size data in version structShawn Nematbakhsh2017-03-161-5/+7
| | | | | | | | | | | | | | | | | | | | | Store our image size (known at build time) in our version struct (now renamed to image_data). This will allow us to more efficiently determine the size of an image in a follow-up CL. Note that compatibility is broken for old ROs that do not include this CL. BUG=chromium:577915 TEST=Verify on kevin + lars + lars_pd that stored image size matches output of system_get_image_used() for both RO and RW images. BRANCH=None Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/450858 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* led: Add options for left and right ledDuncan Laurie2017-03-131-0/+4
| | | | | | | | | | | | | | Add LED types for left and right so they can be addressed properly with ectool. BUG=b:36150361 BRANCH=none TEST=manual testing of 'ectool led <left|right> <color>' behavior Change-Id: Iea25cc69db2d35416e787dcb5a324d2e2cf5d3a6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/453126 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* common: add feature bit for fingerprint supportVincent Palatin2017-03-131-0/+2
| | | | | | | | | | | | | | | | Add a new 'feature' bit to allow the host to auto-detect a FP MCU. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=manual, on Eve, look at the features bit on the kernel interface. Change-Id: If21320bb29d58f0a6dfadba03d8892e4183e5430 Reviewed-on: https://chromium-review.googlesource.com/452341 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* spi: extend spi master API on STM32Vincent Palatin2017-03-131-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | Extend the SPI master API to be able to do fancier transactions: - allow to read the incoming bits while transmitting. If SPI_READBACK_ALL is set in 'rxlen' when calling spi_transaction(), then the received data during transmission is recorded in rxdata buffer and the function assumes that the real 'rxlen' is equal to 'txlen'. - add spi_transaction_wait() which is similar to spi_transaction_flush() but without de-asserting the chip select, so we can chain several transfers in a single transaction. Implement them for STM32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, use the FP sensor with the passthru. Change-Id: Iebff617acd3230277d36a4f565766b7748721a1d Reviewed-on: https://chromium-review.googlesource.com/452898 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* Include "config.h" in include/watchdog.h.Jeff Andersen2017-03-101-0/+2
| | | | | | | | | | | | | | | | | Without this include, the `watchdog_reload()` function will be compiled as a noop unless "config.h" is included before "watchdog.h" in whatever compilation unit requires watchdog functionality. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I311019753f6d61890be1e475664bd528e5250729 Reviewed-on: https://chromium-review.googlesource.com/449694 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* battery: Allow BATTERY_LEVEL_NEAR_FULL to be defined by boardDuncan Laurie2017-03-092-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow the board to override the hardcoded 97% value for reporting to the host (and controlling LED behavior) when the battery is "near full". When enabling "discharge on ac" with a full battery the battery stops taking a charge until it reaches ~94% SOC (the actual value is not set but rather comes from a smart battery status bit) but the user will see the device as discharging between 97% and 94%. The host side view can be worked around with a powerd preference. The LED behavior is all inside the EC, so you end up with the LED showing discharging when it should not. If we allow the board to override this to 94% then the LED and host behavior is consistent. BUG=b:36024657 BRANCH=none TEST=make -j buildall Change-Id: Ie5ab8e41b87101e201073276bf441e25be7daca4 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/450949 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* chip/stm32/usb: Add support for USB SET_FEATURE control requestsNicolas Boichat2017-03-081-0/+5
| | | | | | | | | | | | | | | | | | | | This is required so that the kernel can enable/disable remote wake-up capabilities, and in particular for the kernel to enable autosuspend. Also, properly implement GET_STATUS. BRANCH=none BUG=b:35579996 TEST=echo auto > /sys/bus/usb/drivers/usb/X-Y/power/control, device autosuspends after 2 seconds, and wakes on keypress. Note that this introduces other bugs, where keys are missing, repeated, see b/35775048. Change-Id: I7ddd257ac3877d27fb2da813f20583a614a0169b Reviewed-on: https://chromium-review.googlesource.com/450826 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pdcontrol: Suspend port individuallyDaisuke Nojiri2017-03-072-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pdcontrol suspend command will be used to prevent tcpm from putting the chip into sleep while firmware update is taking place. Currently the command suspends or resumes port 0. This patch makes the command apply to ports individually. pd enable console command now takes a port number: pd <port> enable/disable. This patch also replaces CONFIG_USB_PD_COMM_ENABLED with _DISABLED. When it's defined, PD communication is disabled at startup. Plankton undefines CONFIG_USB_PD_COMM_ENABLED enable, intending to disable PD communication at startup. Therefore, this patch defines CONFIG_USB_PD_COMM_DISABLED in its board.h. BUG=b:35586859 BRANCH=none TEST=From AP console: localhost # /tmp/ectool pdcontrol suspend 1 [600.188013 TCPC p1 suspended!] > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: SUSPENDED, Flags: 0x0020 localhost # /tmp/ectool pdcontrol resume 1 [678.516613 TCPC p1 resumed!] > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 From ec console: > pd 1 disable Port C1 disable > pd 1 state Port C1 CC1, Dis - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 > pd 1 enable Port C1 enabled > pd 1 state Port C1 CC1, Ena - Role: SNK-UFP State: DRP_AUTO_TOGGLE, Flags: 0x0020 Change-Id: Ia0cc4904ac52adc4b89de20918968c8df78b9c80 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447968 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add option to adjust compiler optimization on RSAVincent Palatin2017-03-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Using -O3 optimization level rather than -Os results in a large speed-up for a minor code size increase for the RSA code with our current GCC toolchain. Add the CONFIG_RSA_OPTIMIZED option to do it on platforms which are not too size-constrained. On cortex-M4 based STM32L432, I'm measuring a 37 to 40% speed increase (depending on CPU frequency) for a 200 bytes code size delta. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manual: benchmark RSA2048 with F4 exponent on STM32L432: -Os -O3 @16Mhz 185163 us --> 111942 us @80Mhz 39286 us --> 24582 us Change-Id: I8c2e4b757f037f4f645fb73ba0faaaa471b24896 Reviewed-on: https://chromium-review.googlesource.com/445218 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* charger: Add state for discharge + fullDaisuke Nojiri2017-03-032-0/+9
| | | | | | | | | | | | | | | | | | When battery is fully charged, Reef starts discharging to protect battery and starts charging again when charge level goes down around 95%. To prevent the battery LED from showing blue with the charger plugged in, this patch adds a new state for discharge + nearly full. Reef shows a color indicating battery is full if an external charger is present. BUG=b:35775017 BRANCH=none TEST=Fully charge Electro. Plug in OEM charger. LED lights blue. Change-Id: I4c7c62f2c51c1d39188d1b271331984e89d5d7a3 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/448961 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Include <stdint.h> in include/watchdog.h.Jeff Andersen2017-03-021-0/+2
| | | | | | | | | | | | | | | | Previously, the int types used in the watchdog_trace() function signature were not being included properly. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ib4666285c314cbdb101e3ba602e4f27540a1346c Reviewed-on: https://chromium-review.googlesource.com/448345 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Carl Hamilton <carlh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* switch: Initialize switch state earlier during HOOK_INITShawn Nematbakhsh2017-03-021-6/+8
| | | | | | | | | | | | | | | | | | | | The host may ask for our switch state at any time, so do initialization immediately after lid + power button are initialized. BUG=chrome-os-partner:63073 BRANCH=gru TEST=On kevin, verify system boots when EC reset is triggered with lid open. Verify lid close and power button press still succeed to power-down from dev screen. Change-Id: I8e37c02ef4f4d2d7c06beb383cdbda8eea67bc5c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444322 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 106d33cd3a8e4f3356950a3b2b92ea587977b4e7) Reviewed-on: https://chromium-review.googlesource.com/445276 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* gpio: Add function to clear pending interruptDuncan Laurie2017-03-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently if an interrupt is pending before it is enabled the interrupt will fire immediately. In most cases this is fine, but if we want to use the interrupt to trigger something like waking the AP it should be sure that it won't immediately fire once enabled. For example: on the Eve board we have the trackpad interrupt run to the AP and the EC in order to support wake from Deep S3 (magic AP state that only the EC can wake it from). This interrupt is used in S0 by the AP while ignored by the EC, and then enabled on the transition to S3 in order to be able to wake. Since it has been active the interrupt may be pending in the EC (depending on the chip), which can result in the interrupt firing immediately and waking the AP. BUG=chrome-os-partner:62224 BRANCH=none TEST=This has been functionally tested on npcx only as that is what I have a use case and system for, the others compile and look right but have not been directly tested. Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/446962 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32/usb: Add support for remote wake-upNicolas Boichat2017-03-012-0/+14
| | | | | | | | | | | | | | | | | | | | USB uses a special mode the trigger remote wake-up during host suspend, by setting the K-state on the data differential pair, and setting a bit in the USB config descriptor attributes field. Let's enable that so that hammer can wake up host from S3. BRANCH=none BUG=chrome-os-partner:62325 TEST=Connect hammer to chell, put chell in S3. Press a key (or use ("kb 3 3 1; kb 3 3 0" in console), or touch trackpad => host wakes. Change-Id: Ib7b1e9047e01869f07ddd771c9c9bc640eef10d6 Reviewed-on: https://chromium-review.googlesource.com/446240 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32/usb: Add support for USB suspendNicolas Boichat2017-03-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This follows the basics of what is decribed in RM0091 Reference Manual 30.5.5 Suspend/Resume events . We call enable/disable_sleep at suspend/resume, to make sure the EC stays awake when USB is connected and active. We also call clock_enable/disable_module, which is stubbed on stm32f0, but can be used on other devices in the family. This also fixes interrupt handling in usb_interrupt, by only clearing interrupt bits that were handled instead of resetting them all, which is racy, and can potentially lead to issues if reset comes soon after a resume event. BRANCH=none BUG=chrome-os-partner:62325 TEST=build and flash hammer, connect to chell, suspend/resume, and see that hammer prints USB suspend and USB resume lines. Change-Id: Ie9d02fd4a114add3ebc98dc9393680bc9a64a522 Reviewed-on: https://chromium-review.googlesource.com/446239 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Store console lock state in NvMem vars.Aseda Aboagye2017-02-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | This commit enables the use of the nvmem vars module. The console lock state is migrated from using the long life scratch register, to nvmem vars instead which will persist across power on reboots. BUG=b:35586145 BRANCH=None TEST=Flash a dev image. Lock the console. Remove all power from the system. Power on system and verify that console is still locked. Unlock the console, remove power from the system, power on the system, verify that the console is now unlocked. TEST=Repeat the above test, but using the nvtestvar console command instead. Change-Id: I03a2098bb0017cfca59889457a332eafb0e95db6 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/445804 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32f09x: fix flash protection offsetRong Chang2017-02-271-0/+8
| | | | | | | | | | | | | | | | | | | | | STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB), which doesn't fit the layout requirement in config_std_internal_flash.h. This CL hardcodes the layout and flash bank mapping. BUG=chrome-os-partner:62372 BUG=chromium:694972 TEST=load on elm and manually enable write protect using flashrom # flashrom -p ec:dev=0 --wp-enable check ec console write protect option bytes, bank 31 is writable > rw 0x1ffff808 read 0x1ffff808 = 0xff00ff00 > rw 0x1ffff80c read 0x1ffff80c = 0x7f80ff00 BRANCH=oak Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446176
* hostcmd: Remove EC_CMD_VBNV_CONTEXT handler for most boardsShawn Nematbakhsh2017-02-252-5/+4
| | | | | | | | | | | | | | | | | Most boards do not keep VBNV storage on the EC, so leave out the host command handler by default. BUG=chromium:693210 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia202ec7d73d1804d8430fe7516cc783afd86e89a Reviewed-on: https://chromium-review.googlesource.com/446716 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* flash: Add ROLLBACK flash region, that can be protected separatelyNicolas Boichat2017-02-253-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ROLLBACK region will be used to store rollback information, and can be protected independently of RW (it can only be protected when RO is protected, though). This is only supported on stm32f0 currently. BRANCH=none BUG=chrome-os-partner:61671 TEST=on hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW+RB protected flashwp noall; reboot => only RO protected flashwp rw; reboot => only RO+RW protected flashwp rb; reboot => RO+RW+RB protected flashwp norb; reboot => RO+RW protected flashwp all; reboot => RO+RW+RB protected flashwp norw; reboot => RO+RB protected TEST=on reef, rb/norb commands not available Change-Id: I45ffc66d91cf3699ecff025e5114c59a73dc8274 Reviewed-on: https://chromium-review.googlesource.com/430519 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-241-6/+25
| | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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